DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR

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1 e-issn Volume 4 Issue 9, September 2018 pp Scientific Journal Impact Factor : DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR Hemant Singh Bisht ECE Dept., ABES Engineering College, bisht5hemant@gmail.com Abstract Subtractor is an important part of the combinational circuit, which is used in the arithmetic circuit using conjugation of many logic gates. The main motive of this paper is to design a four-bit binary signed Subtractor having zero error and which can be easily comparable with the result, which we get when calculating without using any tool, i.e. solving manually in decimal form. With the above motive, subtraction of lower number with a higher number is possible, which is a drawback of the four-bit binary full subtractor. This implementation is designed using basic logic gates and simulated using the ISE Design Suite. The resulted logic diagram of four-bit binary signed subtractor shows its efficiency as well as advantages in terms of understanding and reduced complexity compared to basic four-bit binary Subtractor. Keywords Binary Parallel Subtractor, Full Adder, Sign Magnitude, 1 s Complement, 2 s Complement, End Around Carry I. INTRODUCTION Nowadays, with the increase in demand of latest technologies, technologies have improved in terms of power, performance, area, and efficiency. The arithmetic logic unit plays the main part in the development of digital circuits. As most of them require N-Bit Adder and N-Bit Subtractor for performing addition and subtraction of N-bit. It s the work of the control unit (CU) to consider operation needs to be performed by ALU. To reduce the complexity of subtraction operation, the complement method has been used. In complement method, an additional bit, i.e., most significant bit (MSB) is represented as a sign bit, and rest others bits are magnitude. 0 in the sign bit represents positive number and 1 in the sign bit represents negative number. This method of representation is called as sign-magnitude representation. Developing circuit applications, which are not liable to error, are the main focus of researchers as time goes by. Full Subtractor/Adder, being one of the fundamental building blocks of all the aforementioned circuit applications. So to perform an unerring four-bit binary signed subtractor, we designed a logic which is 100% error free and easily understandable in binary terms. This circuit can be further used in applications like Scientific Calculator, where when subtracting low magnitude number with high magnitude number gives 2 complement of output, which is not easily comprehensible. II. CONCEPT AND LOGIC A. FOUR BIT BINARY PARALLEL SUBTRACTOR Using complement methods, we can perform subtraction of two binary numbers. A Four-Bit Binary Parallel Subtractor is a combinational circuit designed to perform subtraction between two inputs having 4 bits binary each. 1) Subtraction Using 1 s Complement One of the biggest benefit of using subtraction method is that complication can be reduced using 1 s complement, which means inverting bits of a binary number having a negative sign and using parallel adder adding with other input, i.e., A-B is similar to A+(-B) or All rights Reserved 9

2 Circuit for subtracting A-B consists of a parallel adder with inverters placed between each data input B and corresponding input of the full adder. Figure 1. 1 s complement Subtraction using Parallel Adder Here we will be subtracting two number 9 and 6 using 1 s Complement. Subtracting 9 with 6 using simple subtraction produce 3 as result. A: 910 in binary: B: 610 in binary: Consider, A = A3A2A1A0 and B = B3B2B1B0 First, we need to invert the second binary number, i.e. B using 1 s complement method. So, one s complement of 0110 is equal to Adding the first number and complement of the second number gives: The result from above is 0010, while the overflow/ end around carry needs to be added, to convert it back from 1 s complement result to its original result Converting to decimal will give 310. But, there comes a drawback with which we have to move on ahead to 2 s complement to make our logic more accurate. When subtracting 0000 with 0000, it gives wrong result ) Subtraction Using 2 s Complement To minimize the drawback of subtraction using 1 s complement, 2 s complement comes into work. Simply to obtain 2 s complement of any binary number, we take 1 s complement of the number and then add binary one with the complement All rights Reserved 10

3 Figure 2. 2 s complement Subtraction using Parallel Adder Example1: Taking 9 and 6 as the number in which subtraction is being performed. 9 A= B= s complement of B = 1 s complement of B Adding first number and 2 complement of second number gives: The result from above is 0011, while the overflow/ end around carry needs to be discarded. Converting to decimal will give 310. But, there comes a drawback in parallel adder when subtracting using 2 s complement method. This method is applicable only when A>B when A-B will give a result. But when A<B, it produces a 2 s complement result. Example2: Taking 6 and 9 as the number in which subtraction is being performed. 6 A= B= s complement of B = 1 s complement of B All rights Reserved 11

4 Adding first number and 2 complement of second number gives: The result from above is 1101, resulting in 2 s complement result of original result, while the overflow/ end around carry needs to be discarded. Figure 3. Circuit diagram of Four Bit Binary Parallel Adder using Logic Gates Figure 3(a). Circuit diagram of Half Adder using Logic Gates Figure 3(b). Circuit diagram of Full Adder using Logic All rights Reserved 12

5 Figure 4. Waveform of Four Bit Binary Parallel Adder using Logic Gates Above waveform shows the limitation of Figure 2 and Figure 3 as we need to convert 2 s complement result to the original result, which is not mentioned in Figure 2 and Figure 3. So, for overcoming all above-explained limitations we have designed Unerring Four Bit Binary Signed Subtractor. III. PROPOSED DESIGN AND WORKING The modified four-bit binary signed subtractor works on the principle of 2 s complement. The proposed schematic circuit has 8 inputs excluding RESET (which is used for resetting all inputs to zero) and 5 outputs. A3, A2, A1, A0 represents first four-bit input A and B3, B2, B1, B0 represents another four-bit input B. Y3, Y2, Y1, Y0 represents four-bit output Y, while S_Y is signed representation of Y. In S_Y, 1 refers to the Negative Sign representation of Y. 0 refers to the Positive Sign representation of Y. In Fig 5., First four-bit binary parallel subtractor named as Four Bit Full Subtractor will works similar to Subtraction Using 2 s complement process, and will produce a result which is 2 s complement output of original result. Let s take the above result from Example 2, i.e. SIGNBITfirst = 0, S3first =1, S2first =1, S1first =0, S0first = In Second four bit binary parallel subtractor, the circuit will be having one input as the output of the previous one, i.e. B3=S3 first =1, B3=S3 first =1, B3=S3 first =0, B3=S3first=1 While, A3=A2=A1=A0=0 Now internal circuitry of Second four bit binary parallel subtractor will do the same process as the first one. So, we need to invert the second binary number, B using 1 s complement method. So, one s complement of 1101 is equal to All rights Reserved 13

6 2 s complement of B = 1 s complement of B Adding first number and 2 complement of second number gives: ? 0011? is discarded in second four bit binary parallel subtractor. SIGNBIT =? (discard), S3 second =1, S2 second =1, S1second=0, S0second=1 So, output will be, where sign bit output will be invertor of SIGNBITfirst =0, that is, 1. Converting to decimal will give But, now to have more clarity and accuracy on this circuit, as above output will be considered only, when A<B while calculating A-B. So, the Multiplexer comes into play. The work of multiplexer here is to choose out of the first and second four-bit binary parallel subtractor, which one is having required output. So, this will depend on the select line, i.e. SIGNBITfirst. If SIGNBITfirst=0, then the output of the second four bit binary parallel subtractor will be considered. If SIGNBITfirst=1, then the output of the first four bit binary parallel subtractor will be considered. If we consider Example 1, then it will select the first four bit binary parallel subtractor and will result in changing S_Y to 0, as SIGNBITfirst=1 in Example 1. Figure 5. Manually designed schematic of Modified and Unerring Four Bit Binary All rights Reserved 14

7 Figure 5(a). Manually Designed Schematic of Multiplexer IV. WAVEFORM STUDY Figure 6 shows waveform result of Modified and Unerring Four Bit Binary Subtractor. 1us to 2us Input is A= (0000)2 and B= (0000)2 S_Y=0 which means result is positive, Y3=0, Y2=0, Y1=0, Y0=0 so the final result is (0)10. 2us to 3us Input is A= (1111)2 and B= (0000)2 S_Y=0 which means result is positive, Y3=1, Y2=1, Y1=1, Y0=1 so the final result is (+15)10. 3us to 4us Input is A= (1111)2 and B= (1111)2 S_Y=0 which means result is positive, Y3=0, Y2=0, Y1=0, Y0=0 so the final result is (0)10. 4us to 5us Input is A= (0000)2 and B= (1111)2 S_Y=1 which means result is negative, Y3=1, Y2=1, Y1=1, Y0=1 so the final result is (-15)10. 5us to 6us Input is A= (1001)2 and B= (0110)2 S_Y=0 which means result is positive, Y3=0, Y2=0, Y1=1, Y0=1 so the final result is (+3)10. 6us to 7us Input is A= (0110)2 and B= (1001)2 S_Y=1 which means result is negative, Y3=0, Y2=0, Y1=1, Y0=1 so the final result is (-3)10. Figure 6. Waveform simulation result of Modified and Unerring Four Bit Binary All rights Reserved 15

8 V. CONCLUSION From above analysis, it is clear that the modified design of four Bit Binary Subtractor is significantly more efficient in terms of accuracy, calculability as well as readability, which is not present in the previously defined method, when A<B. In the previous method, we need to calculate 2 s complement result to the original result. This modified circuit is not limited to four bits, we can appertain for more than four bits also, where MSB (most significant bit) will always be the sign of output number obtained. This circuit is easily suitable for digital applications, where calculation can play an important part. By using this method, I have designed a binary calculator which can perform addition, subtraction, multiplication with reset and accuracy of this circuit is 100%. REFERENCES [1] D. Ghosh, K. Kanti and S. Saha, Design of 4 bit binary arithmetic circuit using 1 s complement method,, Volume 2 Issue 4, April 2016, pp [2] M. Morris Mano, Michael D. Ciletti Digital Design Pg [3] Google Search, Binary Subtractor [4] Wikipedia, Adder-subtractor, All rights Reserved 16