A COMPARATIVE ANALYSIS OF AN ULTRA-LOW VOLTAGE 1-BIT FULL SUBTRACTOR DESIGNED IN BOTH DIGITAL AND ANALOG ENVIRONMENTS

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1 A COMPARATIVE ANALYSIS OF AN ULTRA-LOW VOLTAGE 1-BIT FULL SUBTRACTOR DESIGNED IN BOTH DIGITAL AND ANALOG ENVIRONMENTS Suchismita Sengupta M.Tech Student, VLSI & EMBEDDED Systems, Dept. Of Electronics & Communication Engineering, Capgs, Rourkela, BPUT, Odisha. Ananya Dastidar Asst. Professor, Dept. Of Instrumentation & Electronics, Cet, Bhubaneswar, BPUT, Odisha. Abstract Combinational logic finds extensive applications in low power VLSI design, quantum and optical computing. This paper studies a Full Subtractor that has been implemented in both Digital and Analog environments. The Analog design has been carried out in Cadence Virtuoso Generic Process Design Kit 45 (gpdk45). In the 45nm regime the design was tested with load and no load conditions in a temperature ranging from º Celsius to 52º Celsius in order to check the circuit s stability in the temperature range of Rourkela. The Digital design has been carried out in Xilinx ISE Design Suite The Full Subtractor has been implemented using different design techniques. Verilog HDL has been used to implement the digital design. The aim of this work is to design a low power and low voltage circuit that may be utilized in current trends of design. The Full Subtractor implemented and investigated here gave an average power dissipation of nw (under no load conditions) and 1µW (under load conditions) at 27º Celsius. Keywords: Full Subtractor, Cadence, 45nm, Xilinx. 1. Introduction One of the important modules of any processor is its Arithmetic and Logical Unit (ALU). It contains adders, subtractors, and multiplication and division blocks to handle the arithmetic operations. In this paper, a Full Subtractor has been considered for our study. A 1-bit Full Subtractor [1] has three inputs and two outputs. It is used for subtraction of its inputs. A Full Subtractor finds its application in optical communication as well. [2] Figure 1: Full Subtractor Block Diagram An Adder and a Subtractor circuits can be used inter changeably. Moreover the other arithmetic operations like Multiplication and Division can also be implemented using this basic block. [7][1]. Reduction of complexity of processor is the main goal of Design Engineers [4].Using a Subtractor for implementing the other blocks of an ALU will result in reduction of the number of Logic Blocks in an Integrated Circuit (IC). This reduction in area can be utilized to implement more number of functions in the same substrate area. 25

2 time in ns The study of this circuit comes from the fact that many research is being carried out to using advanced techniques for use in current integrated circuit designs [8][9][1] Table 1: Full Subtractor truth table [1] X Y Bin D Bout Digital Implementation of a Full Subtractor Circuit A Full Subtractor was implemented using Verilog in Xilinx ISE 14.5 Design Suite. The implementation was done using only NAND gates, using only NOR gates and using basic Logic gates and compared for different Field Programmable Gate Array (FPGA) configurations. The objective was to analyze the different attributes of the FPGAs namely Spartan 6 Low Power, Kintex 7 Low Voltage and Artix 7 Low Voltage. The register transfer level (RTL) schematic of the Full Subtractor can be seen in the Figure 2. Figure 2: Full Subtractor RTL Schematic generated via Xilinx ISE Design Suite 14.5 The supply voltages of the three mentioned FPGAs are in the Ultra-Low Voltage range and are as follows:- V dd for Spartan 6 Low Power =.95 V V dd for Kintex 7 Low Voltage =.87 V V dd for Artix 7 Low Voltage =.87 V The different attributes has been analyzed and presented in graphical form. The delay of Spartan 6 Low Power was found to be ns, which was found to be the highest. Delay of Kintex 7 Low Voltage was found to be 1.17 ns and Figure 3: Graphical Representation of Delay that of Artix 7 Low Voltage was 1.49 ns. The frequency of these FPGAs was calculated and is as follows: SPARTAN 6 LOW POWER Frequency (F) = Eq n (1) DELAY COMPARISON KINTEX 7 LOW VOLTAGE ARTIX 7 LOW VOLTAGE NAND NOR BASICS Therefore, F Spartan6 =.1325 GHz, F Kintex7 =.983 GHz, F Artix7 =.953 GHz. Taking the ideal voltage for C load to be 6fF, we have calculated the Dynamic Power Dissipation. Dynamic Power was calculated using the formula, P dyn = C load *V 2 dd *F Eq n (2) Hence, the Dynamic Power Dissipation for the mentioned FPGAs are as follows:- 251

3 POWER in nw Total Power Dissipation in nw P dyn Spartan 6 Low Power = nw Figure 4: Graphical Representation of Dynamic Power Dissipation The Static Power Dissipation was generated by the Xilinx ISE Design Suite 14.5 and is as follows:- P static Spartan 6 = 196 nw P static Kintex 7 = 3872 nw P static Artix 7 = 375 nw We have drawn a comparison amongst the Total Power Dissipation. Comparison of Total Power Dissipation Static Dynamic Total DYNAMIC POWER DISSIPATION technology and are highly suitable for advanced applications. It also provides zero power option in hibernate power down mode. [3] ARTIX 7 Family provides high DSP and logic throughput and are ideal for cost sensitive applications. They are highly preferable for low power applications. [3] From the Figure 5, we find that the KINTEX 7 Family provides the best price-performance and high speed applications. [3] 3. Analog Implementation of a Full Subtractor Circuit After the study of the Full Subtractor design in Digital domain we went on to the implement and study the behavior of the same in Analog domain. Since, the three different implementations of the Full Subtractor circuit i.e. only NAND gates, only NOR gates and only basic Logic gates rendered the same delay and power values, therefore, we designed the Full Subtractor by implementing two Half Subtractors in the Analog domain. The Analog design of the Full Subtractor circuit was done in Cadence Virtuoso Tool. In this paper, we have made our design in 45nm regime only. The Full Subtractor circuit was made by cascading two Half Subtractor circuits. NAND NOR BASICS Figure 5: Graphical Representation of Total Power Dissipation Comparison SPARTAN 6 Family provides the most cost effective FPGAs in the industry. They are built in 45nm Figure 6: Full Subtractor Schematic made in Cadence Virtuoso gpdk

4 Average Power in nw The implemented circuit was tested with load and no load conditions. The supply voltage that given was 9mV, which is in the ultra-low voltage range. The (W) Nmos is 12 nm and hence (W) Pmos is 3 nm. The propagation delay of the concerned circuit was found to be in the range of nano seconds and it varies with varying temperatures. It was observed that the delay decreases with falling temperatures i.e. the implemented circuit gives faster outputs in colder regions or temperatures. Variation of Average Power with varying Temperature º 5º 1º 27º 32º 38º 48º 52º Temperature in degree Celsius Figure 7: Graphical Representation of Average Power Dissipation Comparison The implemented design was simulated with no load conditions and Transient Analysis was performed. The output of the Transient Analysis is given below:- The zero-width glitch/spike in the Difference(D) signal is due to no-load condition and has no effect in the output. This zero-width glitch/spike in the Difference (D) signal was then successfully eradicated under load conditions. Figure 8: Transient Analysis of Full Subtractor circuit in Cadence Virtuoso Tool under no load Figure 9: Full Subtractor under load conditions Figure 1: Transient Analysis of Full Subtractor circuit in Cadence Virtuoso Tool under load 253

5 The Average Power Dissipation of the circuit under load conditions was found to be 1µW at room temperature. 4. Conclusion The Full Subtractor implemented in both digital and analog domains of designing have proved to have High-Speed operation, runs on an Ultra-Low Voltage supply and even has Low Power dissipation.i.e. the implemented design is Energy-Efficient. As mentioned in the Introduction section, a Full Subtractor function as an Adder, a Multiplier and a Divider. Hence it can replace the other three individual circuits. Hence based on this paper we can design an Arithmetic Logic Unit (ALU) which can prove to be an apt component for an Internet of Things (IoT) processor. [5] 5. References [1] M. Morris Mano, Michael D Ciletti, Digital Design with an introduction to the Verilog HDL, 5 th edition 213. [2] Ajay Kumar et al, Implementation of full-adder and full-subtractor based on electro-optic effect in Mach Zehnder interferometers, Elsevier Journal on Optics Communications, 214. [3] [4] Guang-Ming Tang, Kensuke Takata, Masamitsu Tanaka, 4-bit Bit-Slice Arithmetic Logic Unit for 32- bit RSFQ Microprocessors, IEEE Transactions on Applied Superconductivity, 215 [5] Ala Al-Fuqaha, et al, Internet of Things: A Survey on Enabling Technologies, Protocols, and Applications, IEEE communication surveys & tutorials, 215 [6] y_forums [7] Prvinkumar G. Parate et al, ASIC Implementation of 4 Bit Multipliers, International Conference on Emerging Trends in Engineering and Technology, 28. [8] Kai-Wen Cheng et al, Quantum full adder and subtractor, Electronic Letters, IET, 22. [9] Milind Gautam et al, Reduction of leakage current and power in Full Subtractor using MTCMOS technique, International Conference on Computer Communication and Informatics (ICCCI), IEEE, 213. [1] Li Ding et al, Carbon Nanotube Field Effect Transistors for use as Pass Transistors in Integrated logic gates and Full Subtractor Circuits, American Chemical Society,