DIGIT SERIAL PROCESSING ELEMENTS. Bit-Serial Multiplication. Digit-serial arithmetic processes one digit of size d in each time step.

Transcription

1 IGIT SERIAL PROCESSING ELEMENTS 1 BIT-SERIAL ARITHMETIC 2 igit-serial arithmetic processes one digit of size d in each time step. if d = W d => conventional bit-parallel arithmetic if d = 1 => bit-serial arithmetic d in the range 1 4 is probabl a good choice Potential advantages: Bit-Serial Addition and Subtraction X = x x 1 x 2 x Wd 1 Y = 1 2 Wd 1 MSB LSB X Y Reset Sum C X Y iff C + Smaller chip area ±? Power consumption LSB first is commonl used ±? esign complexit ±? Available tools The MSB first case is more difficult, but it is sometimes used SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se Bit-Serial Multiplication 3 Special case when data is positive, x 4 Serial/Parallel Multipliers In a serial/parallel multiplier the multiplicand, x, arrive bit-seriall while the multiplier, a, is applied in a bit-parallel format ( a a 1 a 2 a 3 a 4 ) x Wd 1 ( a a 1 a 2 a 3 a 4 ) x Wd 2 ( a a 1 a 2 a 3 a 4 ) x 2 ( a a 1 a 2 a Wc 1 ) x W d 1 ( a a 1 a 2 a Wc 1 ) x W d 2 ( a a 1 a 2 a 3 a 4 ) x 1 ( a a 1 a 2 a 3 a 4 ) x ( a a 1 a 2 a Wc 1 ) x Wd +W c 3 W d +W c 2 ( a a 1 a 2 a Wc 1 ) x 1 ( a a 1 a 2 a Wc 1 ) x x.x 1 x 2... x Wd 1 a a 1 a 2 a 3 a Wd +W c 3 W d +W c 2 Man different schemes for bit-serial multipliers have been proposed, but all are based on the add-and-shift principle. The differ mainl in which order bit-products are generated and added and in the wa subtraction is handled. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

2 uring the first W d clock ccles, the least significant part of the product is computed and the most significant is stored in the flip-flops. In the next W c 1 clock ccles, zeros are therefore applied to the input so that the most significant part of the product is shifted out of the multiplier. 5 Signed Multiplicand two s-complement The subtraction of the bit-products required for the sign-bit can be avoided b extending the input b W c 1 copies of the sign-bit. ( a a 1 a 2 a 3 a 4 ) x W d 1 6 Hence, the multiplication requires W d +W c 1 clock ccles. ( a a 1 a 2 a 3 a 4 ) x Wd 2 Two successive multiplications must therefore be separated b W d +W c 1 clock ccles. ( a a 1 a 2 a 3 a 4 ) x 2 ( a a 1 a 2 a 3 a 4 ) x 1 ( a a 1 a 2 a 3 a 4 ) x 1 1 Wd +W c 3 W d +W c x.x 1 x 2 x 3 x 4 x 5 a a 1 a 2 a 3 a 4 W c 1 x x x x x.x 1 x 2 x 3 x 4 x 5 W d +W c 1 SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se A 16-bit serial/parallel multiplier implemented using two-phase logic in a.8-µm CMOS process requires an area of onl 9 µm 55 µm ª.5 mm 2. An alternative version that is the more favorable. 7 Transposed Serial/Parallel Multiplier An alternative realization of the serial/parallel multiplier which adds the bit-products diagonal-wise Lon s multiplier 8 a 4 a 3 a x.x 1 x 2... x Wd 1 a 2 a 1 x.x 1 x 2... x Wd 1 a a 1 a 2 a 3 a 4 Transposed serial/parallel multiplier Modified Serial/parallel multiplier No obvious advantages, but is commonl referred to in the literature! SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

3 Serial/Parallel Multiplier Accumulator 9 Bit-Serial Adaptor 1 = a x + z a 2 a 1 Add Shimming delas b 1 a 4 a 3 x.x 1 x 2... x Wd 1 a a 2 a 1 z Sub Trunc b 2 Serial/parallel multiplier with an inherent input for addition Sign ext. a a 1 a 2 a 3 a 4 Restrictions on the accumulators wordlength built-in truncation SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se In order to avoid limit ccles in wave digital filters we should quantize the outputs of the adaptors: 11 RAM bus 12 b i ( n ) Q < b i ( n ) exact (Magnitude truncation) Sign bit Hence, we must know the sign-bit and the guard-bit! If sign-bit π guard-bit => overflow! RAM Select ata, Max, or Min Shift Register Overflow Logic HA HA Sub a 1 (n) Q a 2 (n) a 1 (n) a 2 (n) Q Shift Register a 2 (n) Shift Register a 1 (n) Sign bit Magnitude truncation in two-port adaptors Shimming elas Sign bit Guard bit Bit-serial PE Shimming elas Examples of performing operations during data transport! Bit-serial PE with overflow correction SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

4 S/P MULTIPLIERS WITH FIXE COEFFICIENTS Serial/Parallel Multipliers with a Positive Coefficient Example Fixed positive coefficient a = (.111) 2C. Serial/parallel multiplier with AN gates removed First, we remove unnecessar AN gates. Next, we notice that the flip-flops are cleared at the beginning of the multiplication. Hence, the left-most therefore has onl zeros as inputs. Hence, it will alwas produce sum and carr bits that are zero, and can therefore be removed. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se Next step Simplified serial/parallel multiplier SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se 1. Remove all AN gates. 2. Remove all s and corresponding flip-flops, starting with the most significant bit in the coefficient, up to the first 1 in the coefficient. 3. Replace each that corresponds to a zero-bit in the coefficient with a feedthrough. The number of s is one less that the number of 1 s in the coefficient. The number of flip-flops equals the number of 1-bit positions between the first and last bit positions. Thus, substantial savings can be made for fixed coefficients. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

5 Serial/Parallel Multipliers with a Negative Coefficient Special case of CSC! 17 A number in CSC representation can be written c = ± c ± c ± c ± c ± ± c Wc 1 2 Wc+1 18 Serial/Parallel Multipliers with a CSC Coefficient The serial/parallel multiplier can be simplified significantl if the coefficient is fixed. The cost is essentiall determined b the number of nonzero bits in the coefficient. In CSC, the average number of nonzero bits is onl about W c /3, compared to W c /2 for two s-complement numbers. Further reductions in hardware resources are therefore possible. where most of the bits are zero. The number c can be rewritten as a difference between two numbers with onl positive coefficients, c = c + c A multiplication can now be written = c x = (c + c ) x = c + x +c ( x) = c + x + c (x + 2 Wd+1 ) where x represents the original value with all bits inverted. Obviousl, the multiplication can be implemented using the technique discussed above, except the x-inputs to the s in bit positions with negative coefficient weights are inverted, and the corresponding carr flipflops are initiall set. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se Example Fixed coefficient a = (.111) 2C using CSC. We first rewrite the coefficient, as just discussed, using CSC. a = (.111) 2C = (.11) CSC = (.1) 2C (.1) 2C 19 MINIMUM NUMBER OF BASIC OPERATIONS There are man applications of fixed-point multiplications with fixed coefficients. In such cases the implementation cost can often be reduced if the multiplications are replaced b elementar operations. The most interesting cases are when the multiplication is realized b onl using the following operations: Serial/parallel multiplier with CSC representation of the coefficient a = (.11) CSC Addition onl Addition and subtraction Addition and shift Addition and subtraction and shift Onl one and four flip-flops are needed, while an implementation using the two s-complement coefficient would require two s and five flip-flops. Hence, the CSC implementation is better in this case. As before, we will not differentiate between addition and subtraction, since their implementation cost is roughl the same. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

6 A shift operation corresponds to a multiplication with a power-of-two. 21 Multiplication with a Fixed Coefficient 22 A shift operation can be implemented either in bit-parallel arithmetic b a barrel shifter if the number of shifts var or simpl b a skewed wiring if the number of shifts is fixed - almost negligible cost. In bit-serial arithmetic a shift operation corresponds to a cascade of flipflops. Thus, both the chip area and power consumption are significant in bit-serial arithmetic. As discussed before, a multiplication with a fixed coefficient (multiplicand) can be simplified if the latter is expressed in canonic signed digit code, CSC). The number of add/sub operations equals the number of nonzero digits in the multiplicand minus one. However, the number of adders/subtractors required b this approach is not alwas a minimum if the multiplicand is larger than 44. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se For example, (45) 1 = (1111) CSC requires three additions (subtractions) Another more efficient alternative representation is (45) 1 = (2 3 +1)( ) which requires onl two additions. Hence, it is of great interest to find the best algorithm to perform the multiplication with fewest basic operations Alternative graphs representing multiplication with 45 Graphs with one and two adders/subtractors multipliers Graphs for three adders/subtractors multipliers SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

7 There are seven different graphs with three adders/subtractors. 32 different graphs with four adders/subtractors. 25 Multiple-Constant Multiplication 26 All numbers in the range [ 496, 495], which correspond to a 12-bit word length, and, of course, man outside this range can be realized with onl four adder/subtractors. x c 1 c 2 c N The number of possible graphs grows rapidl with the number of adders/ subtractors. 1 2 N Multiple-constant multiplication Obviousl there must exist a representation that ields a minimum number of elementar operations (add/subtract and shift), but this number ma not be unique. x 1 x 2 x N Note that for some numbers the CSC representation is still the best. c 1 c 2 c N For a 12-bit word length, the optimal multipliers achieve an average reduction of 16% in the number of adders required over CSC. Transposed multiple-constant multiplication Note, however, that for a particular multiplicand the reduction ma be much larger. The same problem the same solution! SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se 27 IGIT-SERIAL ARITHMETIC 28 x d 1a d 2a d 3a From speed and power consumption points of view it ma sometimes be advantageous to process several bits at a time, so-called digit-serial processing. d 1b d 1c d2b d 2c Exploiting common subexpressions to simplif multiple-constant multiplication The number of bits processed in a clock ccle is referred to as the digit size, d. Most of the principles, to be discussed above, for bit-serial arithmetic can easil be extended to digit-serial arithmetic. Active research topic Look at our web site for recent papers! The motivation for digit-serial processing is to find an optimum trade-off between power, chip area and processing capacit. Active research topic! SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se

8 Traditionall, digit-serial multipliers has been obtained either via unfolding of a bit-serial multiplier or via folding of a bit-parallel multiplier. 29 The latenc of digit-serial processing elements are convenientl described in terms of number of clock ccles. 3 x d-1 d-1 x 1 1 x s d-1 s 1 s critical path An adder has a latenc of zero clock ccles while a serial/parallel multiplier has a latenc of W f d clock ccles, where W f is the number of fractional bits of the coefficient. The clock frequenc will be determined b the longest critical path, which basicall is the number of adjacent operations. igit-serial adder with digit-size d obtained from unfolding an bit-serial adder The problem with these approaches is that the obtained circuits have not been pipelinable at the bit-level. Introducing a pipelining stage will increase the latenc with one clock ccle, but the critical (electrical) path will be decreased, and, thus, the clock frequenc increased. The recursive loop prohibits the insertion of pipelining to reduce the critical path to less than d full-adders, but solutions to this problem has been proposed b Oscar Gustafsson. Look at our web site for techniques to find the optimal level of pipelining in maximall fast, digit-serial, implementations and much more. SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se SP Integrated Circuits epartment of Electrical Engineering larsw@is.liu.se