Low Power FIR Filter Design Based on Bitonic Sorting of an Hardware Optimized Multiplier S. KAVITHA POORNIMA 1, D.RAHUL.M.S 2

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1 ISSN Vol.03,Issue.38 November-2014, Pages: Low Power FIR Filter Design Based on Bitonic Sorting of an Hardware Optimized Multiplier S. KAVITHA POORNIMA 1, D.RAHUL.M.S 2 1 PG Scholar, Dept of ECE, DVR & Dr. HS MIC College of Technology, JNTUK, Kanchikacherla, AP, India, kavitha.ammu22@gmail.com. 2 Assistant Professor, Dept of ECE, DVR & Dr. HS MIC College of Technology, JNTUK, Kanchikacherla, AP, India, rahul.d171986@gmail.com. Abstract: The major important metrics of the digital signal processing circuits are area, power and delay. The main objective of the project is to design a low cost Finite Impulse Response (FIR) filter by jointly considering the optimization of coefficient bit width and hardware resources. The direct FIR structure with faithfully rounded multiple constant multiplication accumulation leads to design this FIR filter for the smallest area, cost and power consumption without effecting the frequency response and output signal precisions. Non uniform co efficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/ accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers are used to achieve the best area and power results. Keywords: Digital Signal Processing (DSP), Faithful Rounding, Truncated Multipliers, Finite Impulse Response (FIR). I. INTRODUCTION Finite impulse response (FIR) filters are widely used in various DSP applications. In some applications, the FIR filter circuit must be able to operate at high sample rates, while in other applications the FIR filter circuit must be a low- power circuit operating at moderate sample rates. The low- power or low- area techniques developed specifically for digital filters can be found in parallel (or block) processing can be applied to digital FIR filter to either increase the effective throughput or reduce the power consumption of the original filter. It is also widely used in many portable applications with limited area and power budget. A general FIR filter of order M can be expressed as the adders. In transposed form there is no extra pipeline registers in order to reduce the delay. So the area of the delay will be high in transpose form when compare to the direct form. (1) FIR filters can be implemented with multiplier blocks through the use of Multiple Constant Multiplication (MCM). MCM is an efficient way of implementing several constant multiplications with same input data. The coefficients are expressed using shifters, adders. The generation of multiplier block of set of constant in MCM block. A finite impulse response (FIR) filter is usually implemented by using a series of delay elements, multipliers and adders to create the filter s output as shown in fig.1. FIR filters can be easily designed to be linear phase. Linear phase has a constant group delay, where all the frequency components have equal delay time. So the filter does not cause any phase distortion or delay distortion. There are two types of FIR filter structures namely direct form and transposed form. In direct form the delay of the adders can be reduced by extra pipeline registers between Fig.1. Structure of linear- phase even order FIR filter in direct form. In direct form the MCM performs concurrent multiplication of delayed input signals and their respective co efficient followed by accumulation of all product. In order to decrease the area cost the hardware implementation of digital FIR filter is classified into multiplier-less and memory based FIR filter system. In multiplier-less, multipliers can be replaced by the adders and shifter that leads to the reduction in silicon 2014 IJSETR. All rights reserved.

2 area. Using Common Sub expression Elimination (CSE) and Canonic Signed Digit (CSD) can reduce the common sub operation in multiplier-less technique. In memory based FIR filter can be implemented on LUT look up table based FPGA. The transpose form FIR filter is best suitable for the memory based FIR filter. An important design issue of FIR filter implementation is the optimization of the bit widths for filter coefficients, which has direct impact on the area cost of arithmetic units and registers. Moreover, since the bit widths after multiplications grow, many DSP applications do not need full- precision outputs where the total error introduced in quantization and rounding is no more than one Unit of the Last Place (ulp) defined as the weighting of the least significant bit (LSB) of the outputs. The Multiplication Constant Multiplication and Accumulation (MCMA) module is realized by accumulating all the Partial Products (PPs) where unnecessary PP Bits (PPBs) are removed without affecting the final precision of the outputs. The bit widths of all the filter coefficients are minimized using non uniform quantization with unequal word lengths in order to reduce the hardware cost while still satisfying the specification of the frequency response. II. FIR FILTER DESIGN The generic flow of FIR filter design and its implementation show in fig.2 is divided into 3 stages namely (1) Finding the order and the coefficients of the filter, (2) Quantizing the filter coefficient and (3) Optimizing the hardware resources of the filter. The first stage is to determine the filter order and filter co efficient with respect to the frequency response of the filter. The second stage is to quantize the obtained filter coefficients to obtained filter coefficients to obtain finite bit accuracy. The third stage describes the area cost can be optimized using the various methods. S.KAVITHA POORNIMA, D.RAHUL.M.S might need only the 12 most significant bits for subsequent processing. II. COEFFICIENT QUANTIZATION AND OPTIMIZATION The direct FIR structure with MCMA because the area cost of the flip-flops in the delay elements is smaller compared with that of the three design stages in Fig. 2 in order to achieve more efficient hardware design with faithfully rounded output signals. Unlike conventional uniform quantization of filter coefficients with equal bit width, the non uniform quantization technique with possibly different bit widths is adopted. The most efficient method for designing optimum magnitude FIR filters with arbitrary specifications is the Remez multiple exchange algorithm. Initially Parks McClellan ( ) is used to fine the filter order M for the given frequency response. It is an iteration algorithm that accepts filter specifications in terms of pass band and stopband attenuation. Remez ( ) is to find the coefficients for the FIR filter of order M. then, quantize the coefficients with enough bits and generate the set of uniformly quantized coefficients with equal bit width B. Fig.3.Multiplication/accumulation using (a) individual PP compression and (b) combined PP compression. Fig.2.Generic flow of FIR filter design and its implementation. After FIR filter operations, the output signals have larger bit width due to bit width expansion after multiplications. In many practical situations, only partial bits of the fullprecision outputs are needed. For example, assuming that the input signals of the FIR filter have 12 bits and the filter coefficients are quantized to 10 bits, the bit width of the resultant FIR filter output signals is at least 22 bits, but we The FIR filter design in this brief adopts the direct form in Fig. 1 where the MCMA module sums up all the products a i. Instead of accumulating individual multiplication for each product, it is more efficient to collect all the PPs into a single PPB matrix with carry-save addition to reduce the height of the matrix to two, followed by a final carry propagation adder Fig. 3 illustrates the difference of individual multiplications and combined multiplication for. III. TRUNCATED MULTIPLIER A. FIR filter design using MCMAT In the faithfully rounded FIR filter realization and it is required that the total error introduce during the arithmetic operations are no larger than one ulp. We modify a recent truncated multiplier design in so that more PPBs can be deleted, leading to smaller area cost. Fig.5 compares the twp approaches. In the removal of unnecessary PPBs is composed of three processes: deletion, truncation, and rounding. Two

3 Low Power FIR Filter Design Based on Bitonic Sorting of an Hardware Optimized Multiplier rows of PPBs are set undeletable because they will be removed at the subsequent truncation and rounding. The fault ranges of deletion, truncation, and rounding before and after adding the offset constants. The gray circles, crossed green circles, and crossed red circles represent respectively the deleted bits, truncated bits, and rounded bits. minimized area cost in the FIR filter implementation. Fig. 5 shows the illustrative architecture of MCMA with Truncation (Multiple constant multiplication/ accumulation with faithfully rounded truncated multipliers) that removes unnecessary PPB. Fig.4. Truncated multiplier designs using MCMAT-I & MCMAT-II. In this brief, we propose an improved version of the faithfully rounded truncated multiplier design as shown in Fig.4. Only a single row of PPB is through undeletable (for the subsequent rounding), and the PPB elimination consists of only deletion and rounding. The error range of deletion and rounding in the improved version is twice large than that in more PPBs can be deleted leading to smaller area in the successive PPB compression. While most FIR filter designs use minimum filter order, we observe that it is possible to minimize the total area by slightly increasing the filter order. Therefore, the total area of FIR filter is estimated using the subroutine area_cost_estimate using the approach. Indeed, the total number of PPBs in the MCMA is directly proportional to the number of FA reduces one PPB. After the uniform quantization and filter order optimization the non uniform quantization in gradually reduces the bit width of each coefficient until the frequency response is no longer satisfied. Finally, we fine-tune the nonuniformly quantized coefficients by adding or subtracting the weighting of LSB of each coefficient and check if further bit width reduction is possible. Using the algorithm, we can find the filter order M and the non uniformly quantized coefficients that lead to Fig.5. FIR filter architecture using MCMAT. The white circles in the L- shape block represent the undeletable PPB. The deletion of the PPB is represented by gray circles. After PP compressions the rounding of the resultant bits is denoted by cross circles. The last row of the PPB matrix represents all the offset and bias constants required including the sign bit modifications. IV. USING BITONIC SORTING The process of rearranging the elements of an array so that they are in ascending or descending order is called sorting. Sorting is one of the most important operations for many embedded computing systems. Sorting networks operates in parallel over the input elements, processing them through a network of comparison-exchange elements. After every comparison-exchange stage elements are permuted such that a sorted sequence is obtained at the final stage. Sorting networks offer great performance and are particularly attractive for hardware implementations due to their inherent parallelism and input-independent structure. However, this solution becomes prohibitively expensive for large data sets because of the area cost or since elements can no longer be provided at the same time. We introduce sorting networks that can offer a variable streaming width, while maintaining high throughput capabilities. The main advantage of the sorting network is that the sequence of comparisons is fixed. Thus it is suitable for parallel processing and hardware implementation, especially if the number of sorted elements is small. The number of compare swap components and delay are two crucial parameters of any sorting network. By delay we mean the minimal number of groups of compare swap components that must be executed sequentially. This algorithm ensures the number of comparators and delay used for given input and reduces the number of comparisons and computation time.

4 S.KAVITHA POORNIMA, D.RAHUL.M.S Select problem specification parameters: input set size and data type. Select parameters controlling implementation in order to balance the performance and cost of the desired implementation: architecture, streaming width. Fig.7. Block diagram final adder unit. VI. RESULTS The simulation result of FIR filter structure using improved truncated multiplier design is shown in Fig. 8. Fig.6. Processing Element (PE). A basic comparison unit, or processing element (PE) used in the algorithm is defined as one two-input comparator and two two-input multiplexers, which determined the higher and lower element of two inputs. A PE is shown in fig.6 with registered outputs for pipelining the stages. We utilized a bitonic sorting- based method and the number of comparison units required to filter. V. CARRY- SAVE ADDITION Carry- save addition is one of the carry- propagate free methods of addition. Carry-Save Adders (CSA) is mainly used when adding three operands or more. An efficient way of designing a carry-save adder to achieve fast performance is by designing it based on a 3-operand carry-save adder. A k-operand CSA adder (where k > 3), is constructed out of several blocks of 3-operand CSAs. This k-operand CSA could be implemented in two common ways: cascade or tree. The cascade structure accepts one new operand at each level except at the first level where three new operands are accepted. The number of levels in this structure is more than the number of levels in the tree structure, which implies more delay. However, the cascade structure remains a preferred option sometimes due to its regular layout, which implies more simplicity in the VLSI design. On the other hand, the tree structure, which is known as the Wallace tree accepts as many operands as possible at the first level. The following levels are used to add the sum and the carry vectors in addition to the operands remaining from the first level, which must be at most two remaining operas. When using the tree structure to build a CSA, the number of levels will be less than the cascade structure as shown in Fig.7. Fig.8. Simulated Filter Output. Fig.9. Power analysis of the FIR filter. The given input signal X is multiplied with constants a 0, a 1, a 2 and a 3 which is delayed and the final addition provides the required output f2 is shown in Fig.9.

5 Low Power FIR Filter Design Based on Bitonic Sorting of an Hardware Optimized Multiplier TABLE I: Comparative Results VII. CONCLUSION This brief has presented low-cost FIR filter designs by jointly considering the optimization of coefficient bit width and hardware resources in implementations. By using a new truncated multiplier design by jointly considering the reduction, deletion, truncation, and rounding of the PP bits. The faithfully truncated multiplier has a total error of no more than 1 ulp and can be used in applications that require accurate results. Moreover, the proposed method reduces the silicon area and power consumption. The comparison results shows that a significant reduction in area and power. The results prove that the proposed method is more conventional one in terms of area and power. VIII. REFERENCES [1] Shen-Fu Hsiao, Jun-Hong Zhang Jian, and Ming-Chih Chen Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/ Accumulation ieee transactions on circuits and systems ii: express briefs, vol. 60, no. 5, may 2013 [2] M. M. Peiro, E. I. Boemo, and L. Wanhammar, Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,vol. 49, no. 3, pp , Mar [2] C.-H. Chang, J. Chen, and A. P. Vinod, Information theoretic approach to complexity reduction of FIR filter design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 8, pp , Sep [3] F. Xu, C. H. Chang, and C. C. Jong, Contention resolution A new approach to versatile subexpressions sharing in multiple constant multiplications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp , Mar [4] F. Xu, C. H. Chang, and C. C. Jong, Contention resolution algorithms for common subexpression elimination in digital filter design, IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 52, no. 10, pp , Oct [5] I.-C. Park and H.-J. Kang, Digital filter synthesis based on an algorithm to generate all minimal signed digit representations, IEEE TransComput.-Aided Design Integr. Circuits Syst., vol. 21, no. 12, pp , Dec [6] C.-Y. Yao, H.-H. Chen, T.-F. Lin, C.-J. J. Chien, and X.- T. Hsu, A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp , Sep [7] O. Gustafsson, Lower bounds for constant multiplication problems, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp ,Nov [8] Y. Voronenko and M. Puschel, Multiplierless multiple constant multiplication, ACM Trans. Algorithms, vol. 3, no. 2, pp. 1 38, May [9] D. Shi and Y. J. Yu, Design of linear phase FIR filters with high probability of achieving minimum number of adders, IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 58, no. 1, pp , Jan [10] R. Huang, C.-H. H. Chang, M. Faust, N. Lotze, and Y. Manoli, Signextension avoidance and word-length optimization by positive-offset representation for FIR filter design, IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 58, no. 12, pp , Oct Author s Profile: S. Kavitha Poornima received the B.Tech degree in Electronics and Communication Engineering from Jawaharlal Nehru Technological University (JNTU) Kakinada, in Where she is pursuing the M.Tech degree in VLSI & Embedded Systems. Her current research area focuses on VLSI. Mr. D.Rahul, working as Assistant professor in DVR & Dr. HS MIC college of Technology, kanchikacherla, krishna District. He has 3 years of Experience. He has completed B.Tech (ECE) from Jawaharlal Nehru Technological University (JNTU) Hyderabad, Vijayawada (AP), India in 2008 and M.S from Alpen-Adria Klagenfurt University, Klagenfurt, Austria in Since 2011 he is working as faculty member in different Engineering Colleges in AP in different capacities. He is doing research work on Signal Processing & Communication. His fields of interest are Signal Processing, communication networks, Digital electronic etc.