Copyright 2005 UMC Corporation and Ansoft Corporation

Transcription

1 Copyright 25 UMC Corporation and Ansoft Corporation 1

2 Table of Contents Table of Contents...2 Executive Summary...3 RFC Design Challenge...3 Design Flow Solution...6 Applications...15 UMC Ansoft Collaboration...15 UMC.13um RFCMOS Solution...15 Ansoft EDA Technology...16 Benefit...16 Conclusion...16 About the Companies...17 UMC...17 Ansoft...17 RFC Design and erification 2

3 Executive Summary Applications such as WLAN, Bluetooth, 3G, Gigabit Ethernet, and portable communications devices are fueling the demand for advanced Mixed Signal/RFCMOS semiconductors. Requirements for lower cost, lighter weight and longer battery life drive greater functional integration leading to sophisticated single-chip solutions. Modern portable consumer electronic systems, for example, combine high digital content for advanced user experience with high analog and radio frequency (RF) resources for connectivity to remote systems and services. This results in complex System on Chip (SoC) solutions that combine mixed-signal circuits, embedded high-performance analog and sensitive RF front-end blocks together with complex digital circuitry on the same chip. UMC delivers advanced SoC solutions that address the needs of communications and networking industries for high-performance and low power digital and analog circuits. UMC has paid particular attention to the sensitive analog and RF circuits that are critical to the success of an C design project. Addressing the analog section of the system with rigor can eliminate costly re-spins. To ensure high yield, the analog blocks must be as robust as the digital blocks and must take into account analog nonlinearities, parametric yield and process variations. Complexities in achieving this robustness force design organizations to search for new technologies and methods to deliver solutions that are rigorous and reliable. Of critical importance is the design flow and modeling for custom integrated circuits that include RF circuits on the analog front-end, analog and mixed-signal circuits at baseband, and digital signal processing on the back-end. UMC and Ansoft have teamed to develop a design solution for complex systems that include custom RF and analog circuits. UMC s advanced RFCMOS process combined with electronic design automation (EDA) tools from Ansoft and other established vendors provide the platform upon which advanced RFCs can be developed. Advanced simulation technologies provided by Ansoft s Nexxim simulator and HFSS 3D electromagnetic extractor enhance the Cadence RFC design flow. This joint effort leverages UMC s production-proven.13um RFCMOS process with advanced circuit simulation and electromagnetic extraction tools from Ansoft. This document describes RF and analog design and verification in the RFC design flow. Circuits from an on-going project to develop an ultrawideband (UWB) multi-band orthogonal frequency division multiplexed (MB-OFDM) radio will be used as the vehicle to demonstrate the process technology, EDA tools and design flow. RFC Design Challenge RFC designers face several significant challenges. Large RFCs, such as wireless transceivers, contain analog and digital components including voltage-controlled oscillators (COs), phase locked loops (PLLs), mixers, filters, amplifiers, automatic gain control (AGC) loops, digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Characterizing these elements requires detailed simulation in the time- and frequencydomains. n addition, simulating multiple radio elements cascaded to form a complete transceiver chain often exceeds the limits of traditional EDA tools. Too often designers are forced to compromise on the breadth of their verification simulations due to long simulation run time and short design schedules. New technology is needed to provide the accuracy and robust convergence required for sensitive analog blocks and the capacity and speed necessary for handling the large numbers of transistors and parasitic elements typical in mixed-signal SoC designs. Modern radio systems operate at GHz frequencies under advanced signaling methods like orthogonal frequency division multiplexing (OFDM) and fast frequency hopping to maximize link reliability and minimize interference with other services. Circuits that perform at high frequency with high switching speed are extremely sensitive to active and passive device models, distributed layout parasitics, substrate coupling effects, inter-stage impedances, C packaging, and power supply noise. Providing new methods that accurately characterize layout and other parasitic effects is more critical than ever to first pass success. RFC design requires specialized and unique analysis techniques specific to RF design. Nonlinear effects of harmonic distortion, gain compression, oscillator phase noise, and mixer noise figure are most often simulated and reported in the frequency domain. Switching behavior, circuit initial start-up, and transceiver response to instantaneous events such as frequency hopping are best examined in the time domain. Technology to allow RFC Design and erification 3

4 simulation in the time- and frequency-domains with consistent results between is required for modern RF circuit simulation and verification. ntegrated circuits are eventually assembled into an C package. n many cases, RF circuits are added to large SoCs in a single-chip solution. Another approach is to integrate RF circuitry by using system-in-package (SiP) techniques leading to similar verification challenges as found in SoC solutions. The most comprehensive system approach allows for a multi-die package that may include a digital SoC together with wireless, sensor and actuator die as necessary. New technologies for circuit simulation capacity and speed that add value to a ready established flow can be integrated into existing design solutions. For analog and RF circuits, the most popular flow is the Cadence irtuoso Analog Design Environment (ADE). Ansoft s products for advanced circuit and electromagnetic simulation are linked into that environment. Many RFCs contain the analog-to-digital converter (ADC), digitalto-analog converter (DAC), phase-lock loop (PLL), and possibly a digital synthesizer. These functions are generally created through a different environment and integrated on-chip. erification of these blocks is still performed using CE-level circuit simulators for critical accuracy. The addition of Nexxim new technology for high-performance circuit simulation combined with the reliability of the High-Frequency Structure Simulator (HFSS ) component and layout electromagnetic extraction into the design flow creates new opportunities for SoC designers to achieve first-pass silicon success. RFC Design and erification 4

5 System Design and Behavioral Modeling Testbench Development Circuit Specifications Circuit Design w/ dealized nterconnect Foundry Design Kit Time and Frequency Domain Circuit Simulation Design/Extraction of Critical On-Chip Passives Design/Extraction of Package Parasitics Layout Electromagnetic Layout Extraction erification in System Testbench Tapeout or Chip ntegration Figure 1. RFC Design and erification Flow. RFC Design and erification 5

6 Design Flow System Design and Behavioral Modeling Schematic Entry and Design Environment Design Tools Ansoft Designer Matlab HDL Spreadsheet Cadence irtuoso Schematic Time and Frequency Domain Circuit Simulation Layout Ansoft Nexxim Cadence Spectre Cadence Ultra-sim Cadence irtuoso-xl Cadence Encounter P&R Electromagnetic Extraction Ansoft HFSS Ansoft Q3D Ansoft TPA Parasitic Extraction, DRC, and LS Cadence Assura DRC/LS Mentor Calibre DRC/LS erification in System Bench Ansoft Nexxim + Designer Figure 2. Design and erification Tools used in the RFC Design Solution. Design Flow Solution Figure 1 is a flow chart depicting the typical RFC flow and Figure 2 is a functional chart that indicates tools used in that flow. The process begins with system design and behavioral modeling test bench development. Common modeling approaches are to use Matlab, a high-level language like C, a hardware description language (HDL) like erilog-a or HDL-AMS, or dedicated system simulators like the one found in Ansoft Designer. These tools are effective in creating a behavioral simulation of a system that may contain RF, analog, and digital sections. Figure 3 depicts a behavioral block diagram of a wireless system with blocks displaying the baseband digital signal processing (D), data converters, radio transmitter and receiver, and the radio channel. Behavioral models for each of these blocks can be created using the aforementioned tools. The level of detail in each behavioral model depends upon the requirements of the analysis and the maturity of the project. By modeling the full chip within a top-level test bench, verification of critical system performance in terms of constellation plots and metrics such as error-vector magnitude (EM) or bit-error rate (BER) can be performed. Circuit block specifications are developed to define such metrics as gain, return loss, noise figure, sensitivity, effective number of bits (ENOB) for the data converters, etc. This behavioral test bench ultimately serves as the framework for more complex mixed level simulations, where blocks can be inserted at the transistor level and verified in a system context. This allows designers to make a tradeoff between analysis rigor and simulation speed by inserting critical blocks at the transistor level and wellcharacterized blocks at the behavioral level. Continuous verification of system performance as blocks mature can be performed to track system evolution during the design process. Problems can be detected and mitigated early in the design cycle allowing corrective measures to be performed. Block design by disparate design teams can occur concurrently and assembled into the top-level simulation as they become available. RFC Design and erification 6

7 PHY MAC SCR PRE HDR COD NT MODFFT PAYSCRCOD NT MODFFT D D Baseband Transmitter / Receiver RF Transmitter / Receiver BSRC RANDOM PRE82153A HDR82153A PAY82153A DATA CCOD82153A PUNCT82153A NT82153A SCR82153A CCOD82153A PUNCT82153A NT82153A MPSKMOD82153a 1 11 Q 1 MPSKMOD82153a 1 11 Q 1 R82153A x x x* x* R82153A x x x* x* ADDPLOT82153A ADDPLOT82153A FFT FFT PRE HDR PAY CYCLC_PREFX S x x ( f ) DAC U2 DAC1 TFCOD82153A Sx x ( f ) AGPP FC=1GHz U22 Synthesizer1 MXER3P N OUT LO FL=1GHz FU=2GHz FL=1GHz FU=2GHz U36 Antenna Channel CAWGN N/2 BSRC RANDOM TX82153A TFCOD82153A U24 Synthesizer1 Sx x ( f ) 5 U37 Antenna ndoor SNK SNK CDMUX U25 ADC ADC AGC LO OUT N AMP 1 2 FL=1GHz FU=2GHz BERP SCR82153A DEC ptn DPUNCT82153A DNT82153A 1 Q x* x* x x x 11 1 DR82153A MPSKDEM82153a REMPLOT82153A FFT CDMUX CYCLC_REMOE AGPP Sx x ( f ) FC=1GHz MXER3P Figure 3. Full transceiver behavioral model of UWB radio for early system-level trade-off studies. Circuit includes all baseband D and signal conditioning circuits, radio circuits, and a multipath fading radio channel model. The behavioral modeling tool used for the UWB project is Ansoft Designer. t provides very comprehensive models for radio blocks such as mixers, filters, amplifiers, radio channel models, and antennas. Ansoft Designer also provides D and mixed-signal blocks often encountered in modern radio systems such as fast Fourier transforms (FFTs), data converters, symbol mappers, random bit sources, and detectors. A very significant advantage of this solution is that it can co-simulate with Matlab models and allows customization of user-defined blocks using standard C programming. For this RFC project, Ansoft and UMC created a custom library of behavioral components for the UWB baseband signal processing including data scrambling, convolutional encoding, puncturing, symbol mapping and OFDM symbol generation. These models represent a Multiband OFDM Alliance 1 (MBOA)-compliant system library that is available to UMC and Ansoft customers. The next step in the flow is circuit design using idealized interconnect and foundry design kit device models. Circuits at this level are used for early design trades to select designs that meet performance specifications. Circuit simulation is performed in the time- and frequency-domains to characterize critical performance metrics. The choice of domain depends on the circuit, type of simulation, and desired output. The Nexxim circuit simulator performs time-domain simulation with an optimized transient simulation engine; it performs frequency-domain simulation using a high-performance harmonic balance engine. UMC has been a leader in the adoption of this new and powerful technology. The Nexxim simulator is fully integrated into the Cadence RFC design flow. Figure 4 illustrates the tight integration directly within the menu structure of Cadence ADE. The value of transient plus harmonic balance in a single simulator is made apparent by time- and frequency-domain simulations on RF circuits. Figure 5 is the schematic for the UWB receiver analog baseband including the baseband filter and variable gain amplifier for automatic gain control (AGC). Peripheral elements surrounding the core circuit represent the circuit test bench that provides in-phase () and quadrature (Q) inputs and outputs and various control and power supply voltages. This circuit is designed using the UMC.13um Foundry Design Kit (FDK) models and simulations were performed using Ansoft s Nexxim circuit simulator. Figure 6 provides typical frequency-domain results for this circuit including swept frequency results using linear network analysis, harmonic distortion results using Nexxim harmonic balance analysis, and gain compression. Figure 7 provides typical timedomain results for the same circuit including the input waveform for a complex OFDM input and the output and Q channel responses for a single UWB frame using Nexxim transient simulation. A single process design kit and associated environment enables a smooth determination and selection of the simulation algorithm desired. Results are presented through a display appropriate for the selected simulation type. As circuits are completed at block level, they are verified within the top-level context with behavioral stimulus and descriptions for the surrounding chip. 1 The Multiband OFDM Alliance is a special interest group organized to develop, publish, and promote the best overall solution for global UWB standardization. See for more information. RFC Design and erification 7

8 Cadence ADE Tool Select Launch Nexxim Figure 4. Ansoft s Nexxim circuit simulator is fully integrated into Cadence ADE UMC. 13um 1. 2 /3. 3 Twin, Tr ipp le Wel lmixed_mode E mos_corner=tt UMC. 13um 1. 2 /3. 3 Twin, Tr ipp le Wel lmixed_mode mos_corner=tt res_case=res_typ UMC. 13um 1. 2 /3. 3 Twin,Tripple We l RFC MOS 1776 LPF_tun BBp BBn BBqp U1 BB1 ADD PD Outp Outn QOutp R k C e- 12 E175 E1752 coremos_corner=tt iomos_corner=tt cirspl_case=typ sqskspl_case=typ mimcap_case=typ varmis12_case=typ varmis33_case=typ vardio_case=typ npn_vn_case=ty p npn_vs_case=ty p pnp_vn_case=ty p rnhr_case=typ rnnpo_case=typ rnppo_case=typ diodn_esd_case=ty p diop_esd_case=typ pad_rf_case=typ 1777 E1782 E176 BBqn Qoutn test ct rl_1p ct rl_1n ct rl_2p ct rl_2n E1761 AGND GNDdump E1765 R k C e- 12 E (min gain)<=ctrl1<=.2(max gain) (min gain)<=ctrl2<=.2(max gain) Figure 5. Analog baseband of UWB receiver including baseband filter and variable gain AGC amplifier. RFC Design and erification 8

9 (a) (b) (c) Figure 6. Example frequency-domain results for the baseband circuit in Figure 5. (a) Swept frequency response for various gain states, (b) Harmonic distortion as reported by harmonic balance simulation, and (c) Gain compression plot as computed by harmonic balance. (a) (b) Figure 7. Example time-domain results for the baseband circuit in Figure 5. (a) OFDM digitally modulated input waveform using PWL source, (b) and Q output as predicted by Nexxim. RFC Design and erification 9

10 To improve the fidelity of the simulation, on-chip passive elements like spiral inductors and metal-oxide-metal (MoM) capacitors can be synthesized, extracted, and added to the circuit simulations. The foundry design kit passive models are highly accurate so long as design rules are followed and parameter ranges are not exceeded. UMC has provided a novel mechanism for device topologies outside those provided in standard design kits to enhance designer s innovation. UMC s Electromagnetic Design Methodology (EMDM) uses full-wave 3D simulation to create models for the on-chip passives with accuracy traceable to the foundry process. For spiral inductors, the inductance and quality factor (Q) is computed by Ansoft s HFSS using advanced full-wave finite element simulation. To simplify the process of using full 3D EM for circuit designers, UMC and Ansoft collaborated on the EMDM project. Ansoft created a tool called the Component Wizard for UMC to develop parameterized models that match their foundry design process. Figure 8 depicts the Component Wizard and the process used by UMC to create ready-to-solve parametric HFSS projects. The wizard uses the Cadence layout P-cell and layer stackup technology file to create HFSS projects. A library of fully parameterized spiral inductor geometries in HFSS has been produced using this method. The library is available to UMC customers as a foundry-validated EMDM design kit. The kit contains fully parameterized HFSS projects for spiral geometries including circular, rectangular, octagonal, and symmetric inductors. A methodology to back annotate the optimized design to common layout tools was also provided. Figure 9 provides plots that compare HFSS simulated results with measured results for two circular spiral geometries. As can be seen in the figures, agreement is excellent for both inductance and quality factor. Component Wizard P-Cell (User- Defined Primitive) Parametric HFSS Project Stackup Compression SiO2 Si M3 M1 M2 2 ε Stackup Tech File Figure 8. Component Wizard reads UMC process technology file and P-cells to create ready-to-solve parametric HFSS projects. RFC Design and erification 1

11 ND62 real-comparison ND65 comparison nductance[nh] ND62_m_L ND62_S_L ND62_m_Q ND62_S_Q Quality Factor nductance[nh] ND65_m_L ND65_S_L ND65_m_Q ND65_5_Q Quality Factor Frequency[GHz] Frequency[GHz] (a) (b) Figure 9. Comparison of HFSS simulated vs. measured inductance and Q for circular spiral inductor. (a) 15um outer diameter, (b) 3um outer diameter. The next step in the process is to perform circuit layout. Automated design-rule-driven and connectivity-driven layout may be used judiciously, especially to take advantage of direct ties to schematic and design-rule-checking (DRC). Critical analog blocks, however, are generally manually routed using a full custom approach to ensure that highly sensitive analog circuitry meet specifications. As layouts are completed, electromagnetic simulation is used to provide highly accurate models for interaction of passive components and interconnect. For example, several spiral inductors may be selected as highly critical and a target for EM simulation in a single project. These EM simulation models can replace the models that were created earlier in the design process, and can be mixed and matched with the existing models. This gives the designer full control over the passive modeling process, and again enables the ability to tradeoff runtime vs. accuracy. An emerging capability for extremely sensitive blocks like COs allows the extraction of the full layout at the block level using full-wave 3D electromagnetic simulation. The performance of simulation tools like HFSS and computer platforms continues to improve and hence it is now possible to use 3D simulation on critical radio blocks. The advantage is that this rigorous method simulates all high-frequency layout effects including on-chip inductors, interconnect, coupling between on-chip passives and to other interconnect structures, and substrate coupling. No assumptions are made regarding parasitics or coupling. Of course the net-based RLC extractors have their place in the RFC flow, but there is always designer input to manage which parasitic effects to include. t is not always clear which parasitic effects are most critical in the circuit context. Rigorous EM extraction of the entire block removes any doubt in the process. Figure 1 depicts an HFSS simulation project for the layout of an entire CO block. All active elements and MoM capacitors have been removed and their terminals were replaced with lumped ports. The HFSS project contains 142 ports and was solved on a dual processor PC in just over nine hours. Simulation required 2.15 GBytes of RAM. Although the simulation is lengthy, it is still reasonable to run overnight and the results for this case were well worth the effort. Figure 11 shows plots of the CO negative resistance generator S 11 magnitude (blue) and phase (red). S 11 must be above the green dashed line (S 11 > db) in order for the device to oscillate. t is shown here that when extracted parasitics computed by full-block extraction are included the device no longer oscillates. Such a failure would not have been discovered until after tapeout, fabrication, and test. This level of layout extraction and verification can be very valuable to design organizations to ensure first silicon success. RFC Design and erification 11

12 Figure 1. Critical CO circuit layout geometry as simulated in HFSS. (a) (b) Figure 11. Plots of CO negative resistance generator S 11 magnitude (blue) and phase (red). S 11 must be above the green dashed line in order for the device to oscillate. (a) Before full-block layout extraction shows oscillation at 4.4 GHz. (b) After full-block layout shows that device no longer oscillates. The next critical step is to extract package parasitics and add those effects to the circuit simulations. At RF frequencies even the smallest amount of lead inductance can have a significant effect on circuit performance. Figure 12 contains images of an HFSS model for a quad flat no-lead (QFN) integrated circuit package. Simulations were performed to extract a full S-parameter matrix for all leads. From these simulations we can compute lead inductance for all conductors. Figure 13 depicts the schematic for the UWB radio receiver including the T/R switch, variable gain LNA, balun, /Q demodulator, and baseband filtering/agc. This circuit was used to examine the effects of package parasitics on circuit performance. Figure 14 is a plot of the small signal performance of the circuit shown in Figure 13 with and without ground and supply lead inductance. The blue trace is the baseline with no ground or supply inductance included. As can be seen from this plot, the S 11 response looking into the LNA is less than db across the frequency range and hence the circuit is stable. The red trace is a plot of S 11 for the LNA including ground and supply package lead inductance for the T/R switch. Again, the circuit remains stable. The green trace is a plot of S 11 looking into the LNA when ground and supply package lead inductance is included for RFC Design and erification 12

13 ADD1 AGND1 AGND2 AGND3 ADD2 RxTx RFin PD ADD RFout RFoutn AGND PD bias_mxi RF RFN LOi LOib bias_mxq LOq LOqb ADD AGND Fi Fin Fq Fqn LPF_tun ADD ctrl_1p ctrl_1n ctrl_2p ctrl_2n PD the T/R switch and LNA. These results show that the ground inductance, common to the first and second stages of the LNA, cause the circuit to oscillate. n the same simulation it was observed that the small signal gain of the LNA decreased by ~15dB. Adjustments to the design of the various blocks were performed to stabilize the circuit. Port2 Die Port4 Port1 Exposed Die Paddle Port3 Gold Wire Cu Leadframe ias Ports (a) (b) Figure 12. Quad flat no-lead (QFN) C package model. (a) Model in HFSS. (b) Finite element mesh. E1648 E1657 bias_mxi bias_mxq RxMx_DD LNA_bias LNA_DD TRsw_DD1 TRsw_DD2 LPF_Tun BB_ADD BB_bias ANT U37 TRswitch Rx ANT Tx LNA_PD LNA_GND U2 LNA bias ADD RFout RFin LNA PD AGND GC AGND1 Balun_DD U53 ActBal Balun_GND RxMx_PD U166 RxMx BBp BBn BBqp BBqn AGND GNDdum p U85 BB Outp Outn QOutp Qoutn out outn outq outqn LNA_GND1 LOi TRsw_GND1 LNA_GC Balun_PD ctrl_1p ctrl_1n ctrl_2p ctrl_2n RxTx Tx LOib RxMx_GND TRsw_GND2 LOq BB_AGND TRsw_GND3 LOqb E1664 Figure 13. UWB receiver schematic including T/R switch, variable gain LNA, balun, /Q demodulator, and baseband filtering/agc. RFC Design and erification 13

14 Q R R CDMUX MXE R3P MXE R3P CMUX CMUX CM UX R CMUX CMUX CD MUX CDMUX CD MUX R CDM U X CDM U X R Q r Q e f re f CDMUX CMUX R Q Figure 14. nput return loss looking into the LNA of the circuit shown in Figure 13 with and without ground and supply lead inductance. Blue trace is the baseline with no ground or supply inductance included. Red trace includes ground and supply package lead inductance for the T/R switch. Green trace includes ground and supply package lead inductance for the T/R switch and LNA causing the circuit to become unstable. The final step prior to tape-out or additional chip integration is to perform full-chip verification in a system (behavioral) test bench. The verification can include transistor-level circuits for multiple circuit blocks with incorporation of all extracted parasitics. The system should allow designers to select the particular level of abstraction for individual circuit blocks in order to make reasonable trades between accuracy and simulation run time. Figure 15 depicts a circuit schematic for full-chip verification of radio transceiver transistor-level circuits within a system test bench. MBOA bit and frame accurate time-domain waveforms are automatically linked to the input of the receiver circuit. Nexxim circuit simulation is performed on the full receive chain with all extracted parasitics included. Figure 16 contains plots of some representative results from the full-chip analysis. Figure 16 (a) is a spectral plot of the signal at the input to the receiver and Figure 16 (b) is a constellation plot showing the detected QPSK symbols at the receiver. mod _ou t N LO OUT S x ( f) x final_tx FFTL=8192*2 TYPE=1 W N DOW_TYPE=1 NTSAMP = rx_rfi n U2 UWB_ Rx SNK DAC U1 DAC2 CTOR AMP MS21= 15 4 MNCH rx_in rx_ out_ r x_ou t_q RTOC pa pr =9 exp and =4 fc utoff=256mhz flength=124 fbeta=.2 N OUT LO Hata su ppl y= 1. 2 LNA_PD= Balun_PD= RxMx_PD= LN A _L G= flo=4g rxlo _a mp= 8 m NS 1 =t ime _s ync _dr op NS2 =2^2 timing_recov_rx txrx= RxBB_PD= ctr l1 = ctr l2 =-. 11 cmout=.68 bias _lna= bias _mx= bb tx bb r x SRDC CSCALE BSRC RANDOM NB =1 12*2 *symb ol s/ 2. 5 BR=data_rate*2 SEED= 1 tx_bits BMEN 1 1/ 6 NB=2 M=4 RTOC CSCALE GAN=1/sqrt(2) REAL_ CONST= MA G_CONST= NSAMP=symbols SAMPLE_RATE=data_rate CCONST CCONST TYPE= NS1=1 NS2=5 6 TYPE= NS1=56 REAL_CONST= TYPE= NS2=56 MAG_ CONST= NS 1= 15 NSAMP =1 5*s ymbo ls NS 2= 56 SAMPL E_RATE=data_rate tx_fre q TYPE= NS1=5 7 NS2=7 1 REAL_CONST= MAG_CONST= NSAMP=32*symbols SAMP LE _R A T E=data_rate CCONST FFT FF TL =1 28 tx_time TYPE= TY P E = NS1=3 2 NS1=16 NS2=1 28 NS2=5 CCONST REAL_CONST= MA G_CONST= NSAMP=5*symbols SAMPLE_RATE=data_ rate TYPE= NS1=3 2 NS2=1 33 SN K TYPE= NS1=128 NS2=5 SNK rx _ti me FF T FFTL=128 rx_ fre q TYPE= NS1=57 NS2=71 DF= 4 TYPE= NS1= 1 N S 2= 56 TYPE= N S 1= 15 N S 2= 56 SNK SNK TYPE= NS1 =56 NS2 =56 CSCALE GAN=sqrt(2) CT OR M=4 MBEN 6/ 11 NB=2 rx_ bits BERP CTOR CT OR EMP EM Figure 15. Full-chip verification for radio transceiver transistor-level circuit in system test bench. RFC Design and erification 14

15 (a) (b) Figure 16. Full-chip verification simulation results. (a) Spectrum at input to receiver. (b) Constellation plot of QPSK symbols detected at the receiver. Applications The RFC design solution is applicable to many diverse applications from sophisticated analog-digital SoCs containing wireless front-ends to simpler RFC devices that only contain RF circuit blocks. The method provides for higher fidelity in the simulation of the sensitive and critical analog sections by combining rigorous EM extraction with more powerful circuit simulators in an integrated design flow. Wireless and high-speed devices for networking and communications provide the greatest opportunity for this flow. A selection of likely applications is: Cellular CDMA power amplifier 1Gb/s Backplane Transceiver GHz-frequency PLL Gb/s Data Converter UWB Radio Transceiver. UMC Ansoft Collaboration UMC and Ansoft have a shared vision regarding partnerships and the need for advanced technology in the SoC design flow. Partnerships are developed to address significant needs in the C design industry that align with the mission of both partners. The best partnerships are those that have the additional benefit of scaling the business of the members of the partnership and the business of their joint customers. The collaboration between UMC and Ansoft aims to build the most reliable solution for SoCs that contain high-performance analog front-ends by leveraging UMC s advanced RFCMOS processes and Ansoft s new technology for circuit and electromagnetic simulation. UMC.13um RFCMOS Solution UMC provides a logic-based technology platform with Mixed Signal/RF devices--a high performance, low cost solution for SOC designs. Besides providing a common technology platform, UMC also provides a design environment to support Mixed Signal/RF designs, meeting our customers' time to market needs. The design environment includes Mixed Signal/RF foundry design kits, accurate models and P-cells, automatic schematic driven layout environments with links to electromagnetic extraction, simulation, and verification flow. The UMC RFC Design and erification 15

16 .13um CMOS process offers low 1.2 core voltage, F t of 15 GHz, F max = 9 GHz, and very low noise figure and high Q inductors. Ansoft EDA Technology Ansoft provides electronic design automation (EDA) products that deliver high-performance and high-accuracy to support modern electronic and RF integrated circuit design. Ansoft s best-in-class technology for circuit and electromagnetic simulation complements established monolithic C design flows allowing designers to simulate sensitive analog circuits while including layout and packaging electromagnetic effects. Electromagnetic simulation using such tools as the High Frequency Structure Simulator (HFSS) provides accurate modeling of on-chip passives, layout, package parasitics, and substrate coupling. Ansoft s Nexxim circuit simulator links directly into the mainstream Cadence design environment and adds high-performance transient and harmonic balance simulation. Harmonic balance, including the capacity to handle today s larger designs, allows the engineer to predict non-linear performance of circuits including gain compression, P3, inter-modulation, mixer spurious, phase noise, and sensitivity. Transient simulation plus Harmonic Balance in a singular simulator allows circuit validation in time- and frequency-domain under real-world communications waveforms. Benefits The RFC design flow significantly benefits fabless semiconductor design organizations now and in the future. Organizations large and small are highly concerned with achieving silicon success in order to avoid expensive respins and to hit a particular market window. The lifespan of wireless products is typically months. Avoiding a program slip for re-spin can make the difference between successful design-in and missed opportunity. The RFC flow provides a methodical approach to the design, simulation, and integration of complex SoCs. By allowing continuous monitoring of project development using system-level verification and co-design with transistor-level circuits, fabless design organizations can establish true metrics for design feasibility and efficacy. The examples shown here are for the UMC.13um RFCMOS process. The need for this flow increases as technologies scale to smaller technology nodes where parasitic and interconnect effects are more significant. As technologies continue to scale to smaller technology nodes and include greater analog complexity and RF functionality, parasitic effects and the need to solve ever larger circuits faster, with more accuracy, becomes increasingly more significant. The adoption of newer methods is no longer a question of if, but when. Conclusion UMC s advanced RFCMOS process combined with electronic design automation (EDA) tools from Ansoft and other established vendors provide the platform for developing advanced RFCs. This joint effort leverages UMC s production-proven.13um RFCMOS process for RFCs with advanced circuit simulation and electromagnetic extraction tools from Ansoft. This document described RFC design and verification in the RFC design flow and demonstrated key benefits by real examples from an ongoing UWB radio project. t was shown that additional fidelity in modeling, simulation, and verification coverage can be gained by following this method. RFC Design and erification 16

17 About the Companies UMC UMC (NYSE: UMC, TSE: 233) is a leading global semiconductor foundry that manufactures advanced process Cs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume-production, industry-leading 65nm, and mixed signal/rfcmos. UMC s 1 wafer manufacturing facilities include two advanced 3mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. UMC employs approximately 12, people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at Ansoft Ansoft is a leading developer of high-performance electronic design automation (EDA) software. Engineers use Ansoft s software to design state-of-the-art electronic products, such as cellular phones, nternet-access devices, broadband networking components and systems, integrated circuits (Cs), printed circuit boards (PCBs), automotive electronic systems and power electronics. Ansoft markets its products worldwide through its own direct sales force and has comprehensive customer-support and training offices throughout North America, Asia and Europe. For more information, please visit UMC USA 488 De Guigne Drive, Sunnyvale, CA 9485, USA Tel: Fax: Ansoft Corporation 225 West Station Square, Suite 2 Pittsburgh, PA Tel: Fax: RFC Design and erification 17

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