1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

Transcription

1 1-Kb, 2-Kb and 4-Kb SPI Srial CMOS EEPROM FEATURES 10 MHz SPI compatibl 1.8V to 5.5V supply voltag rang SPI mods (0,0) & (1,1) 16-byt pag writ buffr Slf-timd writ cycl Hardwar and softwar protction Block writ protction Protct 1/4, 1/2 or ntir EEPROM array Low powr CMOS tchnology 1,000,000 program/ras cycls 100 yar data rtntion Industrial and Extndd tmpratur rang RoHS-compliant 8-lad PDIP, IC, TSP and 8-pad TDFN packags PIN CONFIGURATION PDIP (L) IC (V) TSP (Y) TDFN (VP2) DESCRIPTION Th CAT25010/20/40 ar 1-Kb/2-Kb/4-Kb Srial CMOS EEPROM dvics intrnally organizd as 128x8/256x8/512x8 bits. Thy fatur a 16-byt pag writ buffr and support th Srial Priphral Intrfac (SPI) protocol. Th dvic is nabld through a Chip Slct ( ) input. In addition, th rquird bus signals ar a clock input (), data input () and data output () lins. Th HOLD input may b usd to paus any srial communication with th CAT25010/20/40 dvic. Ths dvics fatur softwar and hardwar writ protction, including partial as wll as full array protction. FUNCTIONAL SYMBOL V CC 1 8 V CC 2 7 HOLD WP 3 6 V SS 4 5 WP HOLD CAT25010 CAT25020 CAT25040 PIN FUNCTION Pin Nam WP V SS HOLD V CC Function Chip Slct Srial Data Output Writ Protct Ground Srial Data Input Srial Clock Hold Transmission Input Powr Supply V SS For Ordring Information dtails, s pag SCILLC. All rights rsrvd 1 Doc. No. MD-1006 Rv. U

2 ABLUTE MAXIMUM RATINGS (1) Paramtrs Ratings Units Storag Tmpratur -65 to +150 ºC Voltag on any Pin with Rspct to Ground (2) -0.5 to V CC V RELIABILITY CHARACTERISTI (3) Symbol Paramtr Min Units (4) N END Enduranc 1,000,000 Program/ Eras Cycls T DR Data Rtntion 100 Yars D.C. OPERATING CHARACTERISTI V CC = +1.8V to +5.5V, T A =-40 C to +125 C unlss othrwis spcifid. Symbol Paramtr Tst Conditions Min Max Units Rad, Writ, V 10MHz / -40 C to 85 C 2 ma I CC Supply Currnt CC = 5.0V, opn 5MHz / -40 C to 125 C 2 ma I SB1 I SB2 Standby Currnt Standby Currnt V IN = GND or V CC, = V CC, WP = V CC, V CC = 5.0V 2 µa V IN = GND or V CC, = V CC, T A = -40 C to +85 C 4 µa WP = GND, V CC = 5.0V T A = -40 C to +125 C 5 µa I L Input Lakag Currnt V IN = GND or V CC -2 2 µa Output Lakag = V T A = -40 C to +85 C -1 1 µa I CC, LO Currnt V OUT = GND or V CC T A = -40 C to +125 C -1 2 µa V IL Input Low Voltag V CC V V IH Input High Voltag 0.7V CC V CC V V OL1 Output Low Voltag V CC > 2.5V, I OL = 3.0mA 0.4 V V OH1 Output High Voltag V CC > 2.5V, I OH = -1.6mA V CC - 0.8V V V OL2 Output Low Voltag V CC > 1.8V, I OL = 150µA 0.2 V V OH2 Output High Voltag V CC > 1.8V, I OH = -100µA V CC - 0.2V V PIN CAPACITANCE (3) T A = 25 C, f = 1.0MHz, V CC = +5.0V Symbol Tst Conditions Min Typ Max Units C OUT Output Capacitanc () V OUT = 0V 8 pf Input Capacitanc (,,,, WP HOLD ) V IN = 0V 8 pf C IN (1) Strsss abov thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions outsid of thos listd in th oprational sctions of this spcification is not implid. Exposur to any absolut maximum rating for xtndd priods may affct dvic prformanc and rliability. (2) Th DC input voltag on any pin should not b lowr than -0.5V or highr than V CC + 0.5V. During transitions, th voltag on any pin may undrshoot to no lss than -1.5V or ovrshoot to no mor than V CC + 1.5V, for priods of lss than 20ns. (3) Ths paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat AEC-Q100 and JEDEC tst mthods. (4) Pag Mod, V CC = 5V, 25 C Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

3 A.C. CHARACTERISTI T A = -40 C to +125 C, unlss othrwis spcifid. (1) V CC = 1.8V-5.5V V CC = 2.5V-5.5V T A = -40 C to +85 C Symbol Paramtr Min. Max. Min. Max. Units f Clock Frquncy DC 5 DC 10 MHz t SU Data Stup Tim ns t H Data Hold Tim ns t WH High Tim ns t WL Low Tim ns HOLD to Output Low Z ns t LZ (2) t RI t FI (2) t HD t CD Input Ris Tim 2 2 µs Input Fall Tim 2 2 µs HOLD Stup Tim 0 0 ns HOLD Hold Tim ns t V Output Valid from Clock Low ns t HO Output Hold Tim 0 0 ns t DIS Output Disabl Tim ns t HZ t t S t H t WPS t WPH (4) t WC Powr-Up Timing (2)(3) HOLD to Output High Z ns High Tim ns Stup Tim ns Hold Tim ns WP Stup Tim ns WP Hold Tim ns Writ Cycl Tim 5 5 ms Symbol Paramtr Max. Units t PUR Powr-up to Rad Opration 1 ms t PUW Powr-up to Writ Opration 1 ms (1) AC Tst Conditions: Input Puls Voltags: 0.3V CC to 0.7V CC Input ris and fall tims: 10ns Input and output rfrnc voltags: 0.5V CC Output load: currnt sourc I OL max /I OH max ; C L = 50pF (2) This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr. (3) t PUR and t PUW ar th dlays rquird from th tim V CC is stabl until th spcifid opration can b initiatd. (4) t WC is th tim from th rising dg of aftr a valid writ squnc to th nd of th intrnal writ cycl SCILLC. All rights rsrvd 3 Doc. No. MD-1006 Rv. U

4 PIN DESCRIPTION : Th srial data input pin accpts op-cods, addrsss and data. In SPI mods (0,0) and (1,1) input data is latchd on th rising dg of th clock input. : Th srial data output pin is usd to transfr data out of th dvic. In SPI mods (0,0) and (1,1) data is shiftd out on th falling dg of th clock. : Th srial clock input pin accpts th clock providd by th host and usd for synchronizing communication btwn host and CAT25010/20/40. : Th chip slct input pin is usd to nabl/disabl th CAT25010/20/40. Whn is high, th output is tri-statd (high impdanc) and th dvic is in Standby Mod (unlss an intrnal writ opration is in progrss). Evry communication sssion btwn host and CAT25010/20/40 must b prcdd by a high to low transition and concludd with a low to high transition of th input. : WP Th writ protct input pin will allow all writ oprations to th dvic whn hld high. Whn WP pin is tid low all writ oprations ar inhibitd. HOLD : Th HOLD input pin is usd to paus trans mission btwn host and CAT25010/20/40, without having to rtransmit th ntir squnc at a latr tim. To paus, HOLD must b takn low and to rsum it must b takn back high, with th input low during both transitions. Whn not usd for pausing, th HOLD input should b tid to V CC, ithr dirctly or through a rsistor. FUNCTIONAL DESCRIPTION Th CAT25010/20/40 dvics support th Srial Priphral Intrfac (SPI) bus protocol, mods (0,0) and (1,1). Th dvic contains an 8-bit instruction rgistr. Th instruction st and associatd op-cods ar listd in Tabl 1. Rading data stord in th CAT25010/20/40 is accom plishd by simply providing th READ command and an addrss. Writing to th CAT25010/20/40, in addition to a WRITE command, addrss and data, also rquirs nabling th dvic for writing by first stting crtain bits in a Status Rgistr, as will b xplaind latr. Aftr a high to low transition on th input pin, th CAT25010/20/40 will accpt any on of th six instruction op-cods listd in Tabl 1 and will ignor all othr possibl 8-bit combinations. Th communication protocol follows th timing from Figur 1. Tabl 1: Instruction St (1) Instruction Opcod Opration WREN Enabl Writ Oprations WRDI Disabl Writ Oprations RDSR Rad Status Rgistr WRSR Writ Status Rgistr READ 0000 X011 Rad Data from Mmory WRITE 0000 X010 Writ Data to Mmory Not: (1) X = 0 for CAT25010, CAT X = A8 for CAT25040 Figur 1. Synchronous Data Timing V IH t V IL t S t H V IH V IL t SU t WH t H t WL V IH VIL VALID IN t RI t FI t V t HO t DIS V OH HI-Z HI-Z V OL Not: Dashd Lin = mod (1, 1) Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

5 STATUS REGISTER Th Status Rgistr, as shown in Tabl 2, contains a numbr of status and control bits. Th RDY (Rady) bit indicats whthr th dvic is busy with a writ opration. This bit is automatically st to 1 during an intrnal writ cycl, and rst to 0 whn th dvic is rady to accpt commands. For th host, this bit is rad only. Th WEL (Writ Enabl Latch) bit is st/rst by th WREN/WRDI commands. Whn st to 1, th dvic is in a Writ Enabl stat and whn st to 0, th dvic is in a Writ Disabl stat. Th BP0 and BP1 (Block Protct) bits dtrmin which blocks ar currntly writ protctd. Thy ar st by th usr with th WRSR command and ar non-volatil. Th usr is allowd to protct a quartr, on half or th ntir mmory, by stting ths bits according to Tabl 3. Th protctd blocks thn bcom rad-only. Tabl 2. Status Rgistr BP1 BP0 WEL RDY Tabl 3. Block Protction Bits Status Rgistr Bits BP1 BP0 Array Addrss Protctd Protction 0 0 Non No Protction 0 1 CAT25010: F CAT25020: 0C0-0FF Quartr Array Protction CAT25040: 180-1FF 1 0 CAT25010: F CAT25020: 080-0FF CAT25040: 100-1FF Half Array Protction 1 1 CAT25010: F CAT25020: 000-0FF CAT25040: 000-1FF Full Array Protction 2008 SCILLC. All rights rsrvd 5 Doc. No. MD-1006 Rv. U

6 WRITE OPERATIONS Th CAT25010/20/40 dvic powrs up into a writ disabl stat. Th dvic contains a Writ Enabl Latch (WEL) which must b st bfor attmpting to writ to th mmory array or to th status rgistr. In addition, th addrss of th mmory location(s) to b writtn must b outsid th protctd ara, as dfind by BP0 and BP1 bits from th status rgistr. Writ Enabl and Writ Disabl Th intrnal Writ Enabl Latch and th corrsponding Status Rgistr WEL bit ar st by snding th WREN instruction to th CAT25010/20/40. Car must b takn to tak th input high aftr th WREN instruction, as othrwis th Writ Enabl Latch will not b proprly st. WREN timing is illustratd in Figur 2. Th WREN instruction must b snt prior any WRITE or WRSR instruction. Th intrnal writ nabl latch is rst by snding th WRDI instruction as shown in Figur 3. Disabling writ oprations by rstting th WEL bit, will protct th dvic against inadvrtnt writs. Figur 2. WREN Timing HIGH IMPEDANCE Not: Dashd Lin = mod (1, 1) Figur 3. WRDI Timing HIGH IMPEDANCE Not: Dashd Lin = mod (1, 1) Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

7 Byt Writ Onc th WEL bit is st, th usr may xcut a writ squnc, by snding a WRITE instruction, a 8-bit addrss and data as shown in Figur 4. For th CAT25040, bit 3 of th writ instruction opcod contains A8 addrss bit. Intrnal programming will start aftr th low to high transition. During an intrnal writ cycl, all commands, xcpt for RDSR (Rad Status Rgistr) will b ignord. Th RDY bit will indicat if th intrnal writ cycl is in progrss (RDY high), or th th dvic is rady to accpt commands (RDY low). Pag Writ Aftr snding th first data byt to th CAT25010/20/40, th host may continu snding data, up to a total of 16 byts, according to timing shown in Figur 5. Aftr ach data byt, th lowr ordr addrss bits ar automatically incrmntd, whil th highr ordr addrss bits (pag addrss) rmain unchangd. If during this procss th nd of pag is xcdd, thn loading will roll ovr to th first byt in th pag, thus possibly ovrwriting prvioualy loadd data. Following compltion of th writ cycl, th CAT25010/20/40 is automatically rturnd to th writ disabl stat. Figur 4. Byt WRITE Timing OPCODE BYTE ADDRESS DATA IN X* A7 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE Dashd Lin = mod (1, 1) * X = 0 for CAT25010, CAT x = A8 for CAT25040 Figur 5. Pag WRITE Timing (N-1)x (N-1)x8 16+Nx8-1 OPCODE X* BYTE ADDRESS A 7 A 0 Data Byt 1 Data Byt 2 DATA IN Data Byt 3 Data Byt N HIGH IMPEDANCE Dashd Lin = mod (1, 1) * X = 0 for CAT25010, CAT x = A8 for CAT SCILLC. All rights rsrvd 7 Doc. No. MD-1006 Rv. U

8 Writ Status Rgistr Th Status Rgistr is writtn by snding a WRSR instruction according to timing shown in Figur 6. Only bits 2 and 3 can b writtn using th WRSR command. Writ Protction Whn WP input is low all writ oprations to th mmory array and Status Rgistr ar inhibitd. WP going low whil is still low will intrrupt a writ to th status rgistr. If th intrnal writ cycl has alrady bn initiatd, WP going low will hav no ffct on any writ opration to th Status Rgistr. Th WP input timing is shown in Figur 7. Figur 6. WRSR Timing OPCODE HIGH IMPEDANCE MSB DATA IN Not: Dashd Lin = mod (1, 1) Figur 7. WP Timing twps twph WP WP Not: Dashd Lin = mod (1, 1) Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

9 READ OPERATIONS Rad from Mmory Array To rad from mmory, th host snds a READ instruction followd by a 8-bit addrss (for th CAT25040, bit 3 of th rad instruction opcod contains A8 addrss bit). Aftr rciving th last addrss bit, th CAT25010/20/40 will rspond by shifting out data on th pin (as shown in Figur 8). Squntially stord data can b rad out by simply continuing to run th clock. Th intrnal addrss pointr is automatically incrmntd to th nxt highr addrss as data is shiftd out. Aftr raching th highst mmory addrss, th addrss countr rolls ovr to th lowst mmory addrss, and th rad cycl can b continud indfinitly. Th rad opration is trminatd by taking high. Rad Status Rgistr To rad th status rgistr, th host simply snds a RDSR command. Aftr rciving th last bit of th command, th CAT25010/20/40 will shift out th contnts of th status rgistr on th pin (Figur 9). Th status rgistr may b rad at any tim, including during an intrnal writ cycl. Figur 8. READ Timing OPCODE X* A7 BYTE ADDRESS A0 HIGH IMPEDANCE D7 D6 D5 D4 D3 D2 D1 D0 MSB DATA OUT Dashd Lin = mod (1, 1) * X = 0 for CAT25010, CAT X = A8 for CAT25040 Figur 9. RDSR Timing OPCODE DATA OUT HIGH IMPEDANCE MSB Not: Dashd Lin = mod (1, 1) SCILLC. All rights rsrvd 9 Doc. No. MD-1006 Rv. U

10 Hold Opration Th HOLD input can b usd to paus communication btwn host and CAT25010/20/40. To paus, HOLD must b takn low whil is low (Figur 10). During th hold condition th dvic must rmain slctd ( low). During th paus, th data output pin () is tri-statd (high impdanc) and transitions ar ignord. To rsum communication, HOLD must b takn high whil is low. DEGN CONDERATIONS Th CAT25010/20/40 dvics incorporat Powr-On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. Th dvic will powr up into Standby mod aftr V CC xcds th POR triggr lvl and will powr down into Rst mod whn V CC drops blow th POR triggr lvl. This bi-dirctional POR bhavior protcts th dvic against brown-out failur following a tmporary loss of powr. Th CAT25010/20/40 dvic powrs up in a writ disabl stat and in a low powr standby mod. A WREN instruction must b issud prior any writs to th dvic. Aftr powr up, th pin must b brought low to ntr a rady stat and rciv an instruction. Aftr a succssful byt/pag writ or status rgistr writ, th dvic gos into a writ disabl mod. Th input must b st high aftr th propr numbr of clock cycls to start th intrnal writ cycl. Accss to th mmory array during an intrnal writ cycl is ignord and programming is continud. Any invalid op-cod will b ignord and th srial output pin () will rmain in th high impdanc stat. Figur 10. HOLD Timing tcd tcd thd HOLD thd Not: Dashd Lin = mod (1, 1) thz HIGH IMPEDANCE t LZ Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

11 PACKAGE OUTLINES DRAWINGS PDIP 8-Lad 300mils (L) (1)(2) PIN # 1 IDENTIFICATION D E1 SYMBOL MIN NOM MAX A 5.33 A A b b c D E BSC E B L TOP VIEW E A A2 A1 L b2 c b B DE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: (1) All dimnsions ar in millimtrs. (2) Complis with JEDEC spcification MS SCILLC. All rights rsrvd 11 Doc. No. MD-1006 Rv. U

12 IC 8-Lad 150mils (V) (1)(2) SYMBOL MIN NOM MAX A A b PIN # 1 IDENTIFICATION E1 E c D E E BSC h L θ 0º 8º TOP VIEW D h A1 A θ c b L DE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: (1) All dimnsions ar in millimtrs. (2) Complis with JEDEC spcification MS-012. Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

13 TSP 8-Lad (Y) (1)(2) b E1 E SYMBOL MIN NOM MAX A 1.20 A A b c D E E BSC L 1.00 REF L θ1 0 8 TOP VIEW D A2 A θ1 c A1 L1 L DE VIEW END VIEW For currnt Tap and Rl information, download th PDF fil from: (1) All dimnsions ar in millimtrs. (2) Complis with JEDEC spcification MO SCILLC. All rights rsrvd 13 Doc. No. MD-1006 Rv. U

14 TDFN 8-Pad 2 x 3mm (VP2) (1)(2) D A b E E2 PIN#1 IDENTIFICATION PIN#1 INDEX AREA A1 D2 L TOP VIEW DE VIEW BOTTOM VIEW SYMBOL MIN NOM MAX A A A A REF b D D E E TYP L A2 FRONT VIEW A3 For currnt Tap and Rl information, download th PDF fil from: (1) All dimnsions ar in millimtrs. (2) Complis with JEDEC spcification MO-229. Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

15 MP 8-Lad 3 x 3mm (Z) (1)(2) E E1 SYMBOL MIN NOM MAX A 1.10 A A b c D E E BSC L L REF L BSC θ 0º 6º TOP VIEW D A A2 DETAIL A A1 b c DE VIEW END VIEW θ L2 L1 L DETAIL A For currnt Tap and Rl information, download th PDF fil from: (1) All dimnsions ar in millimtrs. (2) Complis with JEDEC spcification MO SCILLC. All rights rsrvd 15 Doc. No. MD-1006 Rv. U

16 EXAMPLE OF ORDERING INFORMATION (1)(2) Prfix Dvic # Suffix CAT V I -G T3 Company ID Product Numbr 25010: 1-Kb 25020: 2-Kb 25040: 4-Kb Packag L: PDIP V: IC, JEDEC Y: TSP VP2: TDFN (2 x 3mm) Z: MP (4) Tmpratur Rang I = Industrial (-40ºC to +85ºC) E = Extndd (-40ºC to +125ºC) Lad Finish G: NiPdAu Blank: Matt-Tin Tap & Rl T: Tap & Rl 3: 3000 units/rl (1) All packags ar RoHS-compliant (Lad-fr, Halogn-fr). (2) Th standard lad finish is NiPdAu. (3) Th dvic usd in th abov xampl is a CAT25040VI-GT3 (IC, Industrial Tmpratur, NiPdAu, Tap & Rl). (4) For availabitily, plas contact your narst ON Smiconductor Sals offic. Doc. No. MD-1006 Rv. U SCILLC. All rights rsrvd

17 REVION HISTORY Dat Rv. Dscription 13-Oct-05 N Updat D.C. Oprating Charactristics Updat Ordring Information 9-Dc-05 O Updat Pin Configuration Updat D.C. Oprating Charactristics Updat Pin Impdanc Charactristics Updat Figur 2, 3, 4, 6, 8 Add Tap and Rl Updat Ordring Information 21-Mar-06 P Updat D.C. Oprating Charactristics Updat A.C. Charactristics Updat Pin Dscription 30-Jun-06 Q Updat Faturs Updat Dscription Updat A.C. Charactristics Updat Packag Marking Rmov Tap and Rl Updat Exampl of Ordring Information 31-Jul-06 R Add TDFN and MP packags Updat Packag Marking Updat Ordring Information 13-Oct-06 S Updat Exampl of Ordring Information 14-Spt-07 T Add Extndd Tmpratur rang Updatd txt format Updat D.C. Oprating Charactristics tabl for Extndd Tmpratur rang Updat A.C. Charactristics tabl for Extndd Tmpratur rang Add MD- to documnt numbr 29-Oct-08 U Chang logo and fin print to ON Smiconductor ON Smiconductor and ar rgistrd tradmarks of Smiconductor Componnts Industris, LLC (SCILLC). SCILLC rsrvs th right to mak changs without furthr notic to any products hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos SCILLC assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Typical paramtrs which may b providd in SCILLC data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. All oprating paramtrs, including Typicals must b validatd for ach customr application by customr's tchnical xprts. SCILLC dos not convy any licns undr its patnt rights nor th rights of othrs. SCILLC products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th SCILLC product could crat a situation whr prsonal injury or dath may occur. Should Buyr purchas or us SCILLC products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold SCILLC and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that SCILLC was nglignt rgarding th dsign or manufactur of th part. SCILLC is an Equal Opportunity/Affirmativ Action Employr. This litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Litratur Distribution Cntr for ON Smiconductor P.O. Box 5163, Dnvr, Colorado USA Phon: or Toll Fr USA/Canada Fax: or Toll Fr USA/Canada ordrlit@onsmi.com N. Amrican Tchnical Support: Toll Fr USA/Canada Europ, Middl East and Africa Tchnical Support: Phon: Japan Customr Focus Cntr: Phon: ON Smiconductor Wbsit: Ordr Litratur: For additional information, plas contact your local Sals Rprsntativ 2008 SCILLC. All rights rsrvd 17 Doc. No. MD-1006 Rv. U