Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2 ICS9DBL411A. Features/Benefits: Recommended Application: General Description:

Transcription

1 ATASHEET Four Output iffrntial Fanout Buffr for PCI Exprss Gn 1 & ICS9BL411A Rcommndd Application: Faturs/Bnfits: PCI-Exprss fanout buffr Low powr diffrntial fanout buffr for PCI- Exprss and CPU clocks 0-pin MLF or TSSOP packaging Output Faturs: 4 - low powr diffrntial output pairs Individual OE# control of ach output pair Ky Spcifications: Output cycl-cycl jittr < 5ps additiv Output to output skw: < 50ps Powr Groups Pin Numbr (TSSOP) V GN scription 9,18 10,17 V_IO for IF(3:0) V Analog V & GN Pin Numbr (MLF) V GN scription 6,15 7,14 V_IO for IF(3:0) 1 3.3V Analog V & GN Gnral scription: Th ICS9BL411 is a 4 output lowr powr diffrntial buffr. Each output has its own OE# pin. It has a maximum input frquncy of 400 MHz. Funtional Block iagram OE#(3:0) 4 IF_INT IF_INC STOP LOGIC 4 IF_LPR(3:0) 1

2 Pin Configuration OE0# 1 IF_INC IF_INT 3 VA 4 GNA 5 OE3# 6 IF3C_LPR 7 IF3T_LPR 8 V_IO 9 GN 10 ICS9BL411 0 IF0T_LPR 19 IF0C_LPR 18 V_IO 17 GN 16 OE1# 15 IF1T_LPR 14 IF1C_LPR 13 OE# 1 IFT_LPR 11 IFC_LPR IF_INT IF_INC OE0# IF0T_LPR IF0C_LPR VA 1 GNA OE3# 3 9BL411 IF3C_LPR 4 IF3T_LPR V_IO 14 GN 13 OE1# 1 IF1T_LPR 11 IF1C_LPR V_IO GN IFC_LPR IFT_LPR OE# 0-pin TSSOP 0-pin MLF

3 TSSOP Pin scription PIN # (TSSOP) 1 OE0# IN PIN NAME PIN TYPE ESCRIPTION Output Enabl for IF0 output. Control is as follows: IF_INC IN Complmnt sid of diffrntial input clock 3 IF_INT IN Tru sid of diffrntial input clock 4 VA PWR 3.3V Powr for th Analog Cor 5 GNA GN Ground for th Analog Cor 6 OE3# IN Output Enabl for IF3 output. Control is as follows: 7 IF3C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 8 IF3T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 9 V_IO PWR Powr supply for low powr diffrntial outputs, nominal 1.05V to 3.3V 10 GN GN Ground pin 11 IFC_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 1 IFT_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 13 OE# IN Output Enabl for IF output. Control is as follows: 14 IF1C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 15 IF1T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 16 OE1# IN Output Enabl for IF1 output. Control is as follows: 17 GN GN Ground pin 18 V_IO PWR Powr supply for low powr diffrntial outputs, nominal 1.05V to 3.3V 19 IF0C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 0 IF0T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 3

4 MLF Pin scription PIN # (MLF) PIN NAME PIN TYPE ESCRIPTION 1 VA PWR 3.3V Powr for th Analog Cor GNA GN Ground for th Analog Cor 3 OE3# IN Output Enabl for IF3 output. Control is as follows: 4 IF3C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 5 IF3T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 6 V_IO PWR Powr supply for low powr diffrntial outputs, nominal 1.05V to 3.3V 7 GN GN Ground pin 8 IFC_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 9 IFT_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 10 OE# IN Output Enabl for IF output. Control is as follows: 11 IF1C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 1 IF1T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 13 OE1# IN Output Enabl for IF1 output. Control is as follows: 14 GN GN Ground pin 15 V_IO PWR Powr supply for low powr diffrntial outputs, nominal 1.05V to 3.3V 16 IF0C_LPR OUT Complmnt clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 17 IF0T_LPR OUT Tru clock of low powr diffrntial clock pair. (no 50ohm shunt rsistor to GN ndd) 18 OE0# IN Output Enabl for IF0 output. Control is as follows: 19 IF_INC IN Complmnt sid of diffrntial input clock 0 IF_INT IN Tru sid of diffrntial input clock 4

5 Absolut Maximum Ratings PARAMETER SYMBOL CONITIONS MIN MAX UNITS Nots Maximum Supply Voltag VA Cor Supply Voltag 4.6 V 1,7 Maximum Supply Voltag V_IO Low-Voltag iffrntial I/O Supply V 1,7 Maximum Input Voltag V IH 3.3V LVCMOS Inputs 4.6 V 1,7,8 Minimum Input Voltag V IL Any Input Vss V 1,7 Storag Tmpratur Ts C 1,7 Input ES protction ES prot Human Body Modl 000 V 1,7 Elctrical Charactristics - Input/Supply/Common Output Paramtrs PARAMETER SYMBOL CONITIONS MIN MAX UNITS Nots Ambint Oprating Tmp Tambint C 1 Supply Voltag Vxxx Supply Voltag V 1 Supply Voltag Vxxx_IO Low-Voltag iffrntial I/O Supply V 1 OE# latncy T Input High Voltag V IHSE Singl-ndd inputs V V 1 Input Low Voltag V ILSE Singl-ndd inputs V SS V 1 iffrntial inputs iffrntial Input High Voltag V IHIF (singl-ndd masurmnt) V 1 iffrntial inputs iffrntial Input Low Voltag V ILIF (singl-ndd masurmnt) V SS mv 1 Input Slw Rat - IF_IN dv/dt Masurd diffrntially V/ns Input Lakag Currnt I IN V IN = V, V IN = GN -5 5 ua 1 I _3.3V 3.3V supply 5 ma 1 Oprating Supply Currnt I _IO+100M V_IO fop = 100MHz 15 ma 1 I _IO_400M V_IO fop = 400MHz 54 ma 1 3.3V supply, Input stoppd, OE# I Standby Currnt _SB33 pins all high 1 ma 1 I _SBIO V_IO supply, Input stoppd 0.1 ma 1 Input Frquncy F i V = 3.3 V MHz Pin Inductanc L pin 7 nh 1 Input Capacitanc C IN Logic Inputs pf 1 C OUT Output pin capacitanc 6 pf 1 disabl output from 1 3 priods 1 Numbr of clocks to nabl or OE#LAT assrtion/dassrtion of OE# Output nabl aftr Tdriv_OE# T ROE# OE# d-assrtion 10 ns 1 Tfall_OE# T FALL 5 ns 1 Fall/ris tim of OE# inputs Tris_OE# T RISE 5 ns 1 5

6 AC Elctrical Charactristics - IF Low Powr iffrntial Outputs PARAMETER SYMBOL CONITIONS MIN MAX UNITS NOTES Rising Edg Slw Rat t SLR iffrntial Masurmnt 1.5 V/ns 1, Falling Edg Slw Rat t FLR iffrntial Masurmnt 1.5 V/ns 1, Slw Rat Variation t SLVAR Singl-ndd Masurmnt 0 % 1 Maximum Output Voltag V HIGH Includs ovrshoot 1150 mv 1 Minimum Output Voltag V LOW Includs undrshoot -300 mv 1 iffrntial Voltag Swing V SWING iffrntial Masurmnt 100 mv 1 Crossing Point Voltag V XABS Singl-ndd Masurmnt mv 1,3,4 Crossing Point Variation V XABSVAR Singl-ndd Masurmnt 140 mv 1,3,5 CYCIS0 iffrntial Masurmnt, fin<=100mhz 0.5 % 1,6 uty Cycl istortion CYCIS1 iffrntial Masurmnt 100MHz < fin<=67mhz +5 % 1,6 CYCIS iffrntial Masurmnt, fin>67mhz +7 % 1,6 iffrntial Masurmnt, IF Jittr - Cycl to Cycl IFJ CC Additiv 5 ps 1 IF[3:0] Skw IF SKEW iffrntial Masurmnt 50 ps 1 Propagation lay t P Input to output lay ns 1 PCI Gn Phas Jittr - Addtiv t phas_addhi 1.5MHz < fin < Nyquist (50MHz) 0.8 ps rms 1 PCI Gn Phas Jittr - Addtiv t phas_addlo 10KHz < fin < 1.5MHz 0.1 ps rms 1 Nots on Elctrical Charactristics: 1 Guarantd by dsign and charactrization, not 100% tstd in production. Slw rat masurd through Vswing cntrd around diffrntial zro 3 Vxabs is dfind as th voltag whr CLK = CLK# 4 Only applis to th diffrntial rising dg (CLK rising and CLK# falling) 5 find as th total variation of all crossing voltags of CLK rising and CLK# falling. Matching applis to rising dg rat of CLK and falling dg of CLK#. It is masurd using a +/-75mV window cntrd on th avrag cross point whr CLK mts CLK#. 6 Tthis is th figur rfrs to th maximum distortion of th input wav form. 7 Opration undr ths conditions is nithr implid, nor guarantd. 8 Maximum input voltag is not to xcd maximum V 6

7 0-pin TSSOP Packag rawing and imnsions INEX AREA A N 1 E1 A E c α L 0-Lad, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (5.6 mil) In Millimtrs In Inchs SYMBOL COMMON IMENSIONS COMMON IMENSIONS MIN MAX MIN MAX A A A b c E SEE VARIATIONS 6.40 BASIC SEE VARIATIONS 0.5 BASIC E BASIC BASIC L N SEE VARIATIONS SEE VARIATIONS a aaa Cb A1 SEATING PLANE VARIATIONS mm. (inch) N MIN MAX MIN MAX aaa C Rfrnc oc.: JEEC Publication 95, MO

8 0-pin MLF Packag rawing and imnsions Indx Ara N Top V iw Sating Plan A1 Anvil Singulation OR Sawn Singulation A3 L E E (N -1)x (Rf.) N (Rf.) N & N Evn 1 (T yp.) If N & N ar Evn (N -1)x (Rf.) b Chamfr 4x 0.6 x 0.6 max OPTIONAL C A C (R f.) N & N Odd Thrmal Bas THERMALLY ENHANCE, VERY THIN, FINE PITCH QUA FLAT / NO LEA PLASTIC PACKAGE IMENSIONS IMENSIONS SYMBOL MIN. MAX. ICS 0L A SYMBOL TOLERANCE A N 0 A3 0.0 Rfrnc N 5 b N E BASIC x E BASIC 4.00 x 4.00 MIN. / MAX..00 /.5 E MIN. / MAX..00 /.5 L MIN. / MAX / 0.65 Ordring Information Part / Ordr Numbr Shipping Packaging Packag Tmpratur 9BL411AKLF Tubs 0-pin MLF 0 to +70 C 9BL411AKLFT Tap and Rl 0-pin MLF 0 to +70 C 9BL411AGLF Tubs 0-pin TSSOP 0 to +70 C 9BL411AGLFT Tap and Rl 0-pin TSSOP 0 to +70 C "LF" suffix to th part numbr ar th Pb-Fr configuration and ar RoHS compliant. "A" is th dvic rvision dsignator (will not corrlat to th datasht rvision). 8

9 Rvision History Rv. Issu at scription Pag # 0.1 8/1/006 Initial Rlas //006 Updatd MLF Packag imnsions. 8 A 7/31/ Updatd lctrical charactristics - additiv jittr, cycl-to-cycl, tpd, skws, slw rats, Idd, tc.. Corrctd powr grouping tabl for TSSOP pkg 3. Final Rlas 1,5,6 B /1/ Highlightd that V IHIF and V ILIF ar singl ndd masurmnts.. Corrctd VSWING paramatr from 300mV to 100mV. 3. Updatd duty cycl distortion tabl with a 3rd figur for spds <=100MHz. 5 C 6/8/01 Typo for "iffrntial Input Low Voltag" units; changd "V" to "mv" This product is protctd by Unitd Stats Patnt NO. 7, 34, 40 and othr patnts. Innovat with IT and acclrat your futur ntworks. Contact: For Sals Fax: For Tch Support pcclockhlp@idt.com Corporat Hadquartrs Intgratd vic Tchnology, Inc. 604 Silvr Crk Vally Road San Jos, CA Unitd Stats (outsid U.S.) Asia Pacific and Japan Intgratd vic Tchnology Singapor (1997) Pt. Ltd. Rg. No G 435 Orchard Road #0-03 Wisma Atria Singapor Europ IT Europ, Limitd Prim Hous Barntt Wood Lan Lathrhad, Surry Unitd Kingdom KT 7E TM 006 Intgratd vic Tchnology, Inc. All rights rsrvd. Product spcifications subjct to chang without notic. IT, ICS, and th IT logo ar tradmarks of Intgratd vic Tchnology, Inc. Acclratd Thinking is a srvic mark of Intgratd vic Tchnology, Inc. All othr brands, product nams and marks ar or may b tradmarks or rgistrd tradmarks usd to idntify products or srvics of thir rspctiv ownrs. Printd in USA 9