Logic Design 2013/9/26. Outline. Implementation Technology. Transistor as a Switch. Transistor as a Switch. Transistor as a Switch

Transcription

1 3/9/6 Logic Dsign Implmntation Tchnology Outlin Implmntation o logic gats using transistors Programmabl logic dvics Compl Programmabl Logic Dvics (CPLD) Fild Programmabl Gat Arrays () Dynamic opration o logic gats Transmission gats Logic circuits ar implmntd using transistors Logic variabls ( and ) ar rprsntd ithr as lvls o currnt or voltag. W will us voltag. A thrshold is din and any voltag blow thrshold is on logic valu and any voltag abov thrshold is th othr logic valu Positiv logic systm: logic zro is rprsntd by low voltag and logic is rprsntd by highr voltag Ngativ logic systm: logic zro is rprsntd by high voltag and logic is rprsntd by low voltag Voltag Logic valu V,min Undind V,ma Logic valu V SS (Gnd) Transistors in logic circuits oprats as switchs Most popular typ o transistors: mtal oid smiconductor ild ct transistor (MOSFET) Two typs o MOSFET: n-channl (NMOS) and p-channl (PMOS) Trminals: sourc, drain, gat and substrat A MOSFET is controlld by th gat voltag NMOS: V G high -> transistor on V G low -> transistor o = "low" = "high" (a) A simpl switch controlld by th input Gat Sourc Drain Substrat (Body) (b) NMOS transistor V G V S (c) Simpliid symbol or an NMOS transistor Figur 3.. NMOS transistor as a switch.

2 3/9/6 = "high" = "low" = V (a) A switch with th opposit bhavior o Figur 3. a V G V S = V Gat Closd switch whn V G = Opn switch whn V G = V Drain Sourc (a) NMOS transistor Substrat (Body) V S = (b) PMOS transistor V G V G = V S Opn switch whn V G = Closd switch whn V G = V (c) Simpliid symbol or a PMOS transistor Figur 3.3. PMOS transistor as a switch. (b) PMOS transistor Figur 3.4. NMOS and PMOS transistors in logic circuits. Considr V as a unction o V NMOS Logic Gats NMOS Logic Gats + 5 V - R V R V V V V V V diagram (b) Simpliid circuit diagram (b) Truth tabl (c) Graphical symbols Figur 3.5. A NOT gat built using NMOS tchnology. (c) Graphical symbols Figur 3.6. NMOS ralization o a NAND gat. NMOS Logic Gats NMOS Logic Gats V V V V (b) Truth tabl V V A (b) Truth tabl (c) Graphical symbols (c) Graphical symbols Figur 3.7. NMOS ralization o a NOR gat. Figur 3.8. NMOS ralization o an AND gat.

3 3/9/6 NMOS Logic Gats V CMOS Gats In NMOS th logic unctions ar ralizd by arrangmnts o NMOS transistors combind with a pull-up dvic that acts as a rsistor. V V (b) Truth tabl V V V n Pull-down ntwork (PDN) (c) Graphical symbols CMOS Gats CMOS Gats In CMOS circuits th pull-up dvic is rplacd by a pull-up ntwork (PUN) build using PMOS transistors For any valuation o inputs, ithr PDN pulls V down to Gnd or PUN pulls V up to PDN and PUN hav qual numbr o transistors, which ar arrangd so that th ntworks ar dual V T V T T T on o o on Pull-up ntwork (PUN) (b) Truth tabl and transistor stats V V V n Pull-down ntwork (PDN) Figur 3.. CMOS ralization o a NOT gat. T T V CMOS Gats CMOS Gats ow to dsign th transistor circuit or a logic unction? = givs th PUN = givs th PDN V V T 3 T 4 T T T 3 T 4 on on o o on o o on o on on o o o on on (b) Truth tabl and transistor stats 3

4 3/9/6 CMOS Gats NOR Gat T T V V T 3 T T T 3 T 4 V T 4 on on o o on o o on o on on o o o on on (b) Truth tabl and transistor stats V T V T V V T T T 3 T 4 V T 3 T 4 on on o o on o o on o on on o o o on on V (b) Truth tabl and transistor stats 3 ( 3) 3 Ngativ Logic Systm Ngativ logic systm: lowr voltag rprsnts V V V V V V V V V L L L L L V 3 (b) Voltag lvls 4

5 3/9/6 Ngativ Logic Systm Standard Chips An approach usd widly until mid-98s was to connct chips ach containing only a w logic gats 74 sris: chips with dirnt logic gats (a) Positiv logic truth tabl and gat symbol (b) Ngativ logic truth tabl and gat symbol Standard Chips For ach spciic 74 sris chip svral variants ar build with dirnt tchnologis 74LS: build with transistor-transistor logic (TTL) 74C: build using CMOS tchnology Standard Chips Standard Chips Bcaus o thir low capacity, standard chips ar sldom usd today cpt or burs Pin Pin 4 Pin 6 Pin 8 Pin Pin Pin 4 Pin 6 Pin 8 Pin 9 Pin Pin 3 Pin 5 Pin 7 Programmabl Logic Dvics Th unction providd by ach o th 74 sris parts is id Each chip contains only a w logic gats Ths chips ar inicint or building larg circuits Solution: manuactur chips that contain rlativly larg amount o logic with a structur that is not id Ths chips ar calld programmabl logic dvics (PLDs) Svral typs o PLDs ar availabl: PLA, PAL, CPLD, and Pin 3 Pin 5 Pin 7 Pin 9 5

6 3/9/6 Programmabl Logic Tchnology n Simpl programmabl logic dvics (PLDs) such as programmabl logic array (PLA) and programmabl array logic (PAL) hav bn in us or ovr yars. PLA: th ida is that logic unctions can b ralizd in sum-o products orm Input burs and invrtrs n n P AND plan P k OR plan Gnral structur o a PLA m 3 3 Programmabl Logic Tchnology Programmabl connctions (switchs) ar diicult to abricat and rduc th spd o circuit In PALs th AND plan is programmabl but th OR plan is id. To compnsat or rducd libility, PALs ar manuacturd in a rang 35 6

7 3/9/6 Programmabl Logic Tchnology On many PLAs and PALs th output o th OR gat is connctd to a lip lop whos output can thn b dback as an input into th AND gat array. This way simpl stat machins ar implmntd 37 Programming PLAs and PALs In PLA or PAL switchs ist btwn th inputs and AND gat Ths switchs should b programmd to implmnt a circuit Thr ar svral thousands programmabl switchs in commrcial chips Manual programming is not an option CAD systms ar mployd or this purpos CAD is running on a computr that is connctd to a programming unit CAD gnrats a il that stats how ach switch should b to raliz th dsignd circuit Programming PLAs and PALs PLD is placd in th programming unit and th programming il is transrrd rom th computr systm Usually PLAs and PALs ar part o circuit and ar on a printd circuit board Usually th chip should b rmovd rom th board or programming In systm programming is usually not providd or PLAs and PALs but is availabl or mor sophisticatd chips CPLD PLAs andpals ar nough or implmnting modrat siz circuits For mor sophisticatd circuits CPLDs ar usd CPLD: multipl blocks and intrnal wiring that conncts th blocks Each block is similar to a PAL or PLA so it is calld PAL lik block CPLD 7

8 3/9/6 CPLD CPLD Intrconnction wiring contains programmabl switchs that ar usd to connct PAL-lik blocks Commrcial CPLDs hav to PAL-lik blocks CPLD dvics usually support in systm programming A small connctor is plac on th board and or programming it is connctd to th computr Th circuit on CPLD that allows this typ o programming is calld JTAG (Joint Tst Action Group). CPLD Fild Programmabl Gat Arrays () On way to quantiy a circuit s siz is to assum that th circuits is to b built using only simpl gats (.g., NAND gats) and stimat how many o ths gats ar ndd This mthod is calld quivalnt gats PLA/PAL: 6 gats CPLD:, gats Not larg by modrn standards To implmnt largr circuits w us s Fild Programmabl Gat Arrays () s: do not contain AND or OR plans contains thr main typs o rsourcs: logic blocks I/O blocks or conncting to th pins intrconnction wirs and switchs Each logic block in an has a small numbr o input and outputs Th most commonly usd logic block is a look-up tabl (LUT) LUT: contains storag clls that ar usd to implmnt a small logic unction 8

9 3/9/6 s ar conigurd by using th in-systm programming mthod s ar volatil: thy will los stord contnts whnvr th powr is turnd o Otn a small PROM is includd on th board that houss th and th storag clls ar loadd automatically rom th PROM whn th powr is applid Dynamic opration o logic gats N N A (a) A NOT gat driving anothr NOT gat V A V V C (b) Th capacitiv load at nod A 9

10 3/9/6 Dynamic opration o logic gats Bur V 5% 5% Gnd Propagation dlay Propagation dlay V V 9% 9% V A 5% 5% Gnd % % (a) Implmntation o a bur t r t (b) Graphical symbol Tri-stat Bur = Tri-stat Bur = (a) (b) (a) A tri-stat bur (b) Equivalnt circuit Z Z (c) (d) (c) Truth tabl (d) Implmntation s Tri-stat Bur Transmission Gat It is possibl to combin an NMOS and a PMOS transistor into a singl switch It is calld a transmission gat Vs=5 and Vs = turns th switch on. Whn V =, NMOS is on and V will b Whn V=5, PMOS transistor will b on and V will b 5 Figur An application o tri-stat burs.

11 3/9/6 XOR Implmnting XOR using AND and OR and NOT rquirs transistors. This can b rducd using transmission gats Multiplr