CS SK DI DO NC TEST GND. Figure 1. Table 1

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1 Rev.. CMOS SERIAL E 2 PROM The series are low power 4K/8K-bit E 2 PROM with a low operating voltage range. They are organized as 256-word 6-bit and 52-word 6bit, respectively. Each is capable of sequential read, at which time addresses are automatically incremented in 6- bit blocks. The instruction code is compatible with the NM93XX series. Features ølow power consumption Standby : 2. µa Max. (VCC=3.6 V) Operating :.6 ma Max. (VCC=3.6 V) :.4 ma Max. (VCC=2.7 V) øwide operating voltage range Write :.9 to 3.6 V Read :.9 to 3.6 V øsequential read capable ø Endurance : 5 cycles/word ø Data retention : years ø S-29Z33A : 4K bits NM9366 instruction code compatible ø S-29Z43A : 8K bits NM93XX series compatible Pin Assignment 8-pin SOP2 Top view 8 V CC 2 7 NC 3 6 TEST 4 5 GND pin SSOP Top view V CC NC TEST GND S-29Z33ADFJA S-29Z43ADFJA S-29Z33AFS * See Dimensions Figure Pin Functions Table Name Pin Number Function SOP2 SSOP Chip select input 2 2 Serial clock input 3 3 Serial data input 4 4 Serial data output GND 5 5 Ground TEST 6 6 Test pin (normally kept open) (can be connected to GND or Vcc) NC 7 7 No Connection V CC 8 8 Power supply

2 Block Diagram Memory array Address decoder V CC GND Data register Output buffer Mode decode logic Clock generator Figure 2 Instruction Set Table 2 Instruction Start Bit Opo Code Address Data S-29Z33A S-29Z43A READ (Read data) A 7 to A xa 8 to A D 5 to D Output* WRITE (Write data) A 7 to A xa 8 to A D 5 to D Input ERASE (Erase data) A 7 to A xa 8 to A EWEN (Program enable) xxxxxx xxxxxxxx EWDS (Program disable) xxxxxx xxxxxxxx x : Doesn t matter. * : Addresses are continuously incremented. Absolute Maximum Ratings Table 3 Parameter Symbol Ratings Unit Power supply voltage V CC -.3 to +7. V Input voltage V IN -.3 to V CC +.3 V Output voltage V OUT -.3 to V CC V Storage temperature under bias T bias -5 to +95 C Storage temperature T stg -65 to +5 C 2

3 Recommended Operating Conditions Table 4 Parameter Symbol Conditions Min. Typ. Max. Unit Power supply voltage V CC READ/WRITE/ERASE EWEN/EWDS V High level input voltage V IH VCC=.8 to 3.6 V.8 Vcc -- Vcc V V CC =.9 to.8 V.9 Vcc -- Vcc V Low level input voltage V IL VCC=.8 to 3.6 V Vcc V V CC =.9 to.8 V. --. Vcc V Operating temperature T op C Pin Capacitance Table 5 (Ta=25 C, f=. MHz, V CC =5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input Capacitance C IN V IN = V 8 pf Output Capacitance C OUT V OUT = V pf Endurance Table 6 Parameter Symbol Min. Typ. Max. Unit Endurance N W 5 cycles/word 3

4 DC Electrical Characteristics Table 7 Parameter Smbl Conditions V CC =2.7 V to 3.6 V V CC =.8 V to 2.7 V VCC=.9 to.8 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Current consumption I CC unloaded ma (READ) Current consumption (PROGRAM) I CC2 unloaded ma Table 8 Parameter Smbl Conditions V CC =2.7 V to 3.6 V V CC =.8 to 2.7 V V CC =.9 to.8 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Standby current consumption I SB =GND =Open Connected to V CC or GND... µa Topr=- +7 C =GND =Open Connected to V CC or GND Topr= C µa Input leakage current I LI V IN =GND to V CC µa Output leakage current I LO V OUT =GND to V CC µa Low level output voltage High level output voltage Write enable latch data hold voltage I OL = µa.. V V OL I OL = 3µA.. V I OL = µa...2 V I OH = -µa V CC -.7 V V OH I OH = -µa V CC -.7 V CC -.3 V I OH = -5µA V CC -.7 V CC -.3 V CC -.2 V V DH Only when write disable V mode 4

5 AC Electrical Characteristics Input pulse voltage Output reference voltage Output load Table 9. V CC to.9 V CC.5 V CC pf Table Parameter Symble Conditions V CC =2.7 to 3.6V V CC =.8 to 2.7 V V CC =.9 to.8v Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. setup time t S.4. µs hold time t H.4. µs deselect time t CDS µs Data setup time t DS µs Data hold time t DH µs Output delay Clock frequency Clock pulse width t PD f t H, t L Topr=- to +7 C µs Topr=-4 to +85 C. 2. µs Topr=- to +7 C 5 25 KHz Topr=-4 to +85 C KHz Topr=- to +7 C µs Topr=-4 to +85 C. 2. µs Output disable time t HZ, t HZ µs Output enable time t SV.5. 5 µs Programming time t PR ms t S t CDS t H t L t H t DS t DH t DS t DH Valid data Valid data t PD t PD (READ) t SV t HZ2 t HZ (VERIFY) Figure 3 Read Timing 5

6 Operation Instructions (in the order of start-bit, instruction, address, and data) are latched to in synchronization with the rising edge of after goes high. A start-bit can only be recognized when the high of is latched to the rising edge of when goes from low to high, it is impossible for it to be recognized as long as is low, even if there are pulses after goes high. Any pulses input while is low are called "dummy clocks." Dummy clocks can be used to adjust the number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when goes low, where it must be between commands during t CDS. All input, including and signals, is ignored while is low, which is stand-by mode.. Read The READ instruction reads data from a specified address. After A is latched at the rising edge of, output changes from a high-impedance state () to low level output. Data is continuously output in synchronization with the rise of. When all of the data (D5 to D) in the specified address has been read, the data in the next address can be read with the input of another clock. Thus, it is possible for all of the data addresses to be read through the continuous input of clocks as long as is high. The last address (An A A = ) rolls over to the top address (An A A = ) A 7 A 6 A 5 A 4 A 3 A 2 A A D 5 D 4 D 3 D 2 D D D 5 D 4 D 3 D 2 D D D 5 D 4 D 3 A 7A 6A 5A 4A 3A 2A A + A 7A 6A 5A 4A 3A 2A A +2 Figure 4 Read Timing (S-29Z33A) X A 8 A 7 A 6 A 5 A 4 A 3 A 2 A A D 5 D 4 D 3 D 2 D D D 5 D 4 D 3 D 2 D D D 5 D 4 D 3 A 8A 7A 6A 5A 4A 3A 2A A + A 8A 7A 6A 5A 4A 3A 2A A +2 Figure 5 Read Timing (S-29Z43A) 6

7 2. Write (WRITE, ERASE) There are two write instructions, WRITE and ERASE. Each automatically begins writing to the non-volatile memory when goes low at the completion of the specified clock input. The write operation is completed in ms (t PR Max.), and the typical write period is less than 4 ms. In the S- 29ZX3A series, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting to high and checking the pin, which is low during the write operation and high after its completion. This VERIFY procedure can be executed over and over again. There are two methods to detect a change in the output. One is to detect a change from low to high setting to high, and the other is to detect a change from low to high as a result of repetitious operations of returning the to low after setting to high and checking the output. Because all and inputs are ignored during the write operation, any input of instruction will also be disregarded. When outputs high after completion of the write operation or if it is in the high-impedence state (), the input of instructions is available. Even if the pin remains high, it will enter the high-impedence state upon the recognition of a high of (start-bit) attached to the rising edge of an pulse. (see Figure 3). input should be low during the VERIFY procedure. 2. WRITE This instruction writes 6-bit data to a specified address. After changing to high, input a start-bit, op-code (WRITE), address, and 6-bit data. If there is a data overflow of more than 6 bits, only the last 6-bits of the data is considered valid. Changing to low will start the WRITE operation. It is not necessary to make the data "" before initiating the WRITE operation. t CDS VERIFY Standby A7 A6 A5 A4 A3 A2 A A D5 D t SV t PR busy ready t HZ Figure 6 WRITE Timing (S-29Z33A) t CDS VERIFY Standby X A8 A7 A6 A5 A4 A3 A2 A A D5 D t SV t PR busy ready t HZ Figure 7 WRITE Timing (S-29Z43A) 7

8 2.2 ERASE This command erases 6-bit data in a specified address. After changing to high, input a start-bit, op-code (ERASE), and address. It is not necessary to input data. Changing to low will start the ERASE operation, which changes every bit of the 6 bit data to "." t CDS VERIFY Standby A7 A6 A5 A4 A3 A2 A A t SV t PR busy ready t HZ Figure 8 ERASE Timing (S-29Z33A) t CDS VERIFY Standby X A8 A7 A6 A5 A4 A3 A2 A A t SV t PR busy ready t HZ Figure 9 ERASE Timing (S-29Z43A) 3. Write enable (EWEN) and Write disable (EWDS) The EWEN instruction puts the series into write enable mode, which accepts WRITE and ERASE instructions. The EWDS instruction puts the series into write disable mode, which refuses WRITE and ERASE instructions. The series powers on in write disable mode, which protects data against unexpected, erroneous write operations caused by noise and/or CPU malfunctions. It should be kept in write disable mode except when performing write operations. 8

9 Standby =EWEN =EWDS 6Xs Figure EWEN/EWDS Timing (S-29Z33A) Standby =EWEN =EWDS 8Xs Figure EWEN/EWDS Timing (S-29Z43A) Receiving a Start-Bit A start bit can be recognized by latching the high level of at the rising edge of after changing to high (Start-bit Recognition). The write operation begins by inputting the write instruction and setting to low. The pin then outputs low during the write operation and high at its completion by setting to high (Verify Operation). Therefore, only after a write operation, in order to accept the next command by having go high, will the pin switch from a state of highimpedence to a state of data output; but if it recognizes a start-bit, the pin returns to a state of high-impedence (see Figure 3). Three-wire Interface (- direct connection) Although the normal configuration of a serial interface is a 4-wire interface to,,, and, a 3-wire interface is also a possibility by connecting and. However, since there is a possibility that the output from the serial memory IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between and in order to give preference to data output from the CPU to (See Figure 2). CPU SIO R : to kω Figure 2 9

10 Ordering Information XXX Package DFJA : SOP2 FS : SSOP (S-29Z33A) Product S-29Z33A : 4Kbit S-29Z43A : 8Kbit

11 Characteristics. DC Characteristics. Current consumption (READ) I CC --.2 Current consumption (READ) I CC -- ICC (ma).4 V CC =3.6 V fsk=5 KHz DATA= ICC (ma).4 V CC =.8 V fsk= KHz DATA= Current consumption (READ) I CC -- Power supply voltage V CC ICC (ma).4.2 Ta=25 C fscl=5 KHz DATA=.4 Current consumption (READ) I CC -- Power supply voltage V CC ICC (ma).4.2 Ta=25 C fscl= KHz DATA=.5 Current consumption (READ) I CC -- Power supply voltage V CC ICC (ma) V CC (V) Ta=25 C fscl= KHz DATA= V CC (V).6 Current consumption (WRITE) I CC2 -- ICC2 (ma) 2.. Vcc=3.6 V V CC (V).7 Current consumption (WRITE) I CC Standby current consumption I SB -- Power supply voltage V CC Ta=25 C -6 Vcc=3.6 V ICC2 (ma) 2.. ISB (A) V CC (V)

12 .9 Input leakage current I LI -- Vcc=3.6 V,,= V. Input leakage current I LI -- Vcc=3.6 V,,=3.6 V ILI (µa). ILI (µa) Output leakage current I LO -- Vcc=3.6 V = V.2 Output leakage current I LO -- Vcc=3.6 V =3.6 V ILO (µa). ILI (µa) High level output voltage V OH --.4 High level output voltage V OH -- VOH (V) Vcc=2.7 V IOH= ua VOH (V)..9 Vcc=.9 V IOH=5 ua Low level output voltage V OL --.6 Low level output voltage V OL -- VOL (V).3.2 Vcc=.8 V IOL= ua VOL (V).3.2 Vcc=.9 V IOL= ua.. 2

13 2. AC Characteristics 2. Maximum operating frequency f max -- Power supply voltage V CC 2.2 Program time t PR -- Power supply voltage V CC Ta=25 C Ta=25 C M fmax (Hz) K twr (ms) 6 4 K V CC (V) V CC (V) 2.3 Program time t PR Program time t PR -- V CC =3.6 V V CC =.9 V twr (ms) 6 4 twr (ms) Data output delay time t PD Data output delay time t PD -- tpd (µs).6.4 V CC =2.7 V tpd (µs).6.4 V CC =.8 V Data output delay time t PD -- tpd (µs) 3 2 V CC =.9 V 3

17 The information herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or other diagrams described herein whose industrial properties, patents or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee any mass-production design. When the products described herein include Strategic Products (or Service) subject to regulations, they should not be exported without authorization from the appropriate governmental authorities. The products described herein cannot be used as part of any device or equipment which influences the human body, such as physical exercise equipment, medical equipment, security system, gas equipment, vehicle or airplane, without prior written permission of Seiko Instruments Inc.

y Endurance : 10 6 cycles/word y Data retention : 10 years 8-pin SOP2 Top view 8-pin DIP Top view CS VC C NC TEST VCC NC CS SK DI DO TEST GND

y Endurance : 10 6 cycles/word y Data retention : 10 years 8-pin SOP2 Top view 8-pin DIP Top view CS VC C NC TEST VCC NC CS SK DI DO TEST GND Rev.. CMOS SERIAL E 2 PROM The S-2953A / 63A series are low power 6K / 32K-bit E 2 PROM with a low operating voltage range. They are organized as 24-word 6-bit and 248-word 6bit, respectively. Each is