y Endurance : 10 6 cycles/word y Data retention : 10 years 8-pin SOP2 Top view 8-pin DIP Top view CS VC C NC TEST VCC NC CS SK DI DO TEST GND

Transcription

1 Rev.. CMOS SERIAL E 2 PROM The S-2953A / 63A series are low power 6K / 32K-bit E 2 PROM with a low operating voltage range. They are organized as 24-word 6-bit and 248-word 6bit, respectively. Each is capable of sequential read, at which time addresses are automatically incremented in 6-bit blocks. Features y Low power consumption Standby :.µa Max. Operating :.2 ma Max. (VCC=5.5 V) :.4 ma Max. (VCC=2.5 V) y Wide operating voltage range Write :.8 to 5.5 V Read :.8 to 5.5 V y Sequential read capable y Endurance : 6 cycles/word y Data retention : years Pin Assignment y 8-pin DIP (PKG drawing code : DP8-A) y 8-pin SOP PKG drawing code : FJ8-D) Pin Assignment 8-pin DIP Top view 8-pin SOP2 Top view SK 2 DI VC C NC TEST SK DI VCC NC TEST GND 4 5 GND * See Dimensions Figure Pin Functions Table Name Pin Number Function DIP SOP2 Chip select input SK 2 2 Serial clock input DI 3 3 Serial data input 4 4 Serial data output GND 5 5 Ground TEST 6 6 Test pin (normally kept open) (can be connected to GND or Vcc) NC 7 7 No Connection VCC 8 8 Power supply

2 Block Diagram Memory array Address decoder V CC GND Data register Output buffer DI Mode decode logic SK Clock generator Figure 2 Instruction Set Table 2 Instruction Start Opo Address Data Bit Code S-2953A S-2963A x : Doesn t matter. READ (Read data) A 9 to A xa to A D 5 to D Output* WRITE(Write data) A 9 to A xa to A D 5 to D Input ERASE (Erase data) A 9 to A xa to A EWEN (Program enable) xxxxxxxx xxxxxxxxxx EWDS (Program disable) xxxxxxxx xxxxxxxxxx * : Addresses are continuously incremented. Absolute Maximum Ratings Table 3 Parameter Symbol Ratings Unit Power supply voltage V CC -.3 to +7. V Input voltage V IN -.3 to V CC +.3 V Output voltage V OUT -.3 to V CC V Storage temperature under bias T bias -5 to +95 C Storage temperature T stg -65 to +5 C 2

3 Recommended Operating Conditions Table 4 Parameter Symbol Conditions Min. Typ. Max. Unit Power supply voltage VCC READ/WRITE/ERASE EWEN/EWDS V V CC = 2.5 to 5.5 V.8 Vcc Vcc V High level input voltage V IH V CC =.8 to 2.5 V.8 Vcc Vcc V Low level input voltage V IL V CC = 2.5 to 5.5 V.2 Vcc V V CC =.8 to 2.5 V.5 Vcc V Operating temperature T opr C Pin Capacitance Table 5 (Ta=25 C, f=. MHz, V CC =5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input Capacitance C IN V IN = V 8 pf Output Capacitance C OUT V OUT = V pf Endurance Table 6 Parameter Symbol Min. Typ. Max. Unit Endurance N W 6 cycles/word 3

4 DC Electrical Characteristics Table 7 Parameter Smbl Conditions V CC =4.5 V to 5.5 V V CC =2.5 V to 4.5 V VCC=.8 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Current consumption I CC unloaded ma (READ) Current consumption (PROGRAM) I CC2 unloaded ma Table 8 Parameter Smbl Conditions V CC =4.5 V to 5.5 V V CC =2.5 to 4.5 V V CC =.8 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Standby current consumption Input leakage current Output leakage current Low level output voltage High level output voltage Write enable latch data hold voltage I SB =GND =Open... µa Connected to V CC or GND I LI V IN =GND to V CC µa I LO V OUT =GND to V CC µa V OL CMOS I OL = µa.. V CMOS V OH V DH Vcc=2.5 to 5.5V:I OH = -µa V CC -.7 V CC -.7 V CC -.3 V Vcc=.8 to 2.5V:I OH = -µa Only when write V disable mode 4

5 AC Electrical Characteristics Table 9 Input pulse voltage Output reference voltage Output load. V CC to.9 V CC.5 V CC pf Table Parameter Symble V CC =4.5 to 5.5 V V CC =2.5 to 4.5 V V CC =.8 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. setup time t S.2.4. µs hold time t H.2.4. µs deselect time t CDS µs Data setup time t DS µs Data hold time t DH µs Output delay t PD µs Clock frequency f SK MHz Clock pulse width t SKH, t SKL µs Output disable time t HZ, t HZ µs Output enable time t SV.5.5. µs Programming time t PR ms t S t CDS t SKH t SKL t H SK t DS t DH t DS t DH DI Valid data Valid data t PD t PD (READ) t SV t HZ2 t HZ (VERIFY) Figure 3 Timing Chart 5

6 Operation Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising edge of SK after goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK when goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses after goes high. Any SK pulses input while DI is low are called "dummy clocks." Dummy clocks can be used to adjust the number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when goes low, where it must be low between commands during t CDS. All input, including DI and SK signals, is ignored while is low, which is stand-by mode.. Read The READ instruction reads data from a specified address. After A is latched at the rising edge of SK, output changes from a high-impedance state () to low level output. Data is continuously output in synchronization with the rise of SK. When all of the data (D5 to D) in the specified address has been read, the data in the next address can be read with the input of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous input of SK clocks as long as is high. The last address (An A A = ) rolls over to the top address (An A A = ). SK DI A9 A8 A7 A6 A5 A4 A3 A2 A A D5 D4 D3 D2 D D D5 D4 D3 D2 D D D5 D4 D3 A9A8A7A6A5A4A3A2AA+ A9A8A7A6A5A4A3A2AA+2 Figure 4 Read Timing (S-2953A) SK DI X A A9 A8 A7 A6 A5 A4 A3 A2 A A D5 D4 D3 D2 D D5 D4 D3 D2 D D D5 D4 D3 AA9A8A7A6A5A4A3A2AA+ Figure 5 Read Timing (S-2963A) AA9A8A7A6A5A4A3A2AA+2 6

7 2. Write (WRITE, ERASE) There are two write instructions, WRITE and ERASE. Each automatically begins writing to the non-volatile memory when goes low at the completion of the specified clock input. The write operation is completed in ms (t PR Max.), and the typical write period is less than 4 ms. In the S-2953A / 63A series, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting to high and checking the pin, which is low during the write operation and high after its completion. This VERIFY procedure can be executed over and over again. There are two methods to detect a change in the output. One is to detect a change from low to high setting to high, and the other is to detect a change from low to high as a result of repetitious operations of returning the to low after setting to high and checking the output. Because all SK and DI inputs are ignored during the write operation, any input of instruction will also be disregarded. When outputs high after completion of the write operation or if it is in the high-impedence state (), the input of instructions is available. Even if the pin remains high, it will enter the high-impedence state upon the recognition of a high of DI (start-bit) attached to the rising edge of an SK pulse. (see Figure 3). DI input should be low during the VERIFY procedure. 2. WRITE This instruction writes 6-bit data to a specified address. After changing to high, input a start-bit, op-code (WRITE), address, and 6-bit data. If there is a data overflow of more than 6 bits, only the last 6-bits of the data is considered valid. Changing to low will start the WRITE operation. It is not necessary to make the data "" before initiating the WRITE operation. t CDS VERIFY SK DI A9 A8 A7 A6 A5 A4 A3 A2 A A D5 D t SV t PR busy ready t HZ Figure 6 Write Timing (S-2953A) t CDS VERIFY SK DI X A A9 A8 A7 A6 A5 A4 A3 A2 A A D5 D t SV t PR busy ready t HZ Figure 7 Write Timing (S-2963A) 7

8 2.2 ERASE This command erases 6-bit data in a specified address. After changing to high, input a start-bit, op-code (ERASE), and address. It is not necessary to input data. Changing to low will start the ERASE operation, which changes every bit of the 6 bit data to "." t CDS VERIFY SK DI A9 A8 A7 A6 A5 A4 A3 A2 A A t SV t PR busy ready t HZ Figure 8 ERASE Timing (S-2953A) t CDS VERIFY SK DI X A A9 A6 A7 A6 A5 A4 A3 A2 A A t SV t PR busy ready t HZ Figure 9 ERASE Timing (S-2963A) 8

9 3. Write enable (EWEN) and Write disable (EWDS) The EWEN instruction puts the S-2953A / 63A series into write enable mode, which accepts WRITE and ERASE instructions. The EWDS instruction puts the S-2953A / 63A series into write disable mode, which refuses WRITE and ERASE instructions. The S-2953A / 63A series powers on in write disable mode, which protects data against unexpected, erroneous write operations caused by noise and/or CPU malfunctions. It should be kept in write disable mode except when performing write operations. SK DI EWEN= EWDS= X X8 X Figure EWEN/EWDS Timing (S-2953A) SK DI DI EWEN= EWDS= X X Figure EWEN/EWDS Timing (S-2963A) X 9

10 Receiving a Start-Bit A start bit can be recognized by latching the high level of DI at the rising edge of SK after changing to high (Start-bit Recognition). The write operation begins by inputting the write instruction and setting to low. The pin then outputs low during the write operation and high at its completion by setting to high (Verify Operation). Therefore, only after a write operation, in order to accept the next command by having go high, the pin switch from a state of highimpedence to a state of data output; but if it recognizes a start-bit, the pin returns to a state of high-impedence (see Figure 3). Three-wire Interface (DI- direct connection) Although the normal configuration of a serial interface is a 4-wire interface to, SK, DI, and, a 3-wire interface is also a possibility by connecting DI and. However, since there is a possibility that the output from the serial memory IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between DI and in order to give preference to data output from the CPU to DI(See Figure 2). CPU SIO DI R : to kω Figure 2 Please refer Application Note S-29 & S-93C series EEPROMs Tips, Tricks & Traps for equivalent circuit of each pin.

11 Ordering Information S-29X3A XXXX Package DPA : DIP DFJA : SOP Product S-2953A : 6Kbit S-2963A : 32Kbit

12 Characteristics.DC Characteristics. Current consumption (READ) I CC.2 Current consumption (READ) I CC ICC.4.2 Vcc=5.5V fsk=mhz DATA= I CC.4.2 Vcc=3.3V fsk=5kh DATA=.3 Current consumption (READ) I CC.4 Current consumption (READ) I CC Power supply voltage V CC I CC.4.2 Vcc=.8V fsk=khz DATA= I CC.4.2 Ta=25 C fsk=m,5khz DATA= MHz.5 Current consumption (READ) I CC Power supply voltage V CC 5KHz Vcc[V].6 Current consumption (READ) I CC Clock frequency f SK I CC.4.2 Ta=25 C fsk=k,kh DATA= KHz ICC.4.2 Vcc=5.5V Ta=25 C DATA= KHz Vcc[V].7 Current consumpion (PROGRAM) I CC2 Ambient temprature Ta fsk[hz].8 Current consumption (PROGRAM) I CC2.5.5 Vcc=5.5V Vcc=3.3V I CC2..5 I CC2..5 2

13 .9 Current consumption (PROGRAM)I CC2 I CC Vcc=.8V. Current consumption (PROGRAM) I CC2 Power supply voltage V CC I CC Ta=25 C. Stand by current consumption I SB I SB [A] E-5 E-6 E-7 E-8 E-9 E- E- Vcc=5.5V E-2.3 Input leakege current I LI Ambient temprature Ta I LI [µa].5..5 Vcc=5.5V,SK,DI, TEST=5.5V Vcc[V].2 Input leakege current I LI Ambient temprature Ta I LI [µa].5..5 Vcc=5.5V,SK,DI, TEST=V.4 Output leakege current I LO I LO [µa].5..5 Vcc=5.5V =V.5 Output leakege current I LO Ambient temprature Ta.5. Vcc=5.5V =5.5V.6 High level output voltege V OH Vcc=4.5V I OH=-µA I LO [µa].5 V OH [V]

14 .7 High level output voltage V OH VOH [V] Vcc=2.7V IOH=-µA.8 High level output voltage V OH VOH [V] Vcc=2.5V IOH=-µA High level output voltage V OH 2..9 Vcc=.8V I OH=-µA Low level output voltage V OL.4.3 Vcc=4.5V I OL =µa VOH [V].8 VOL [V] Low level output voltage V OL VOL [V] Vcc=.8V I OL =µa.22 High level output current I OH Ambient temprature Ta -3 IOH -2 - Vcc=4.5V VOH=2.4V.23 High level output current I OH -6 IOH -4-2 Vcc=2.7V VOH=2.V.24 High level output current I OH -6 IOH -4-2 Vcc=2.5V V OH =.8V 4 5 5

15 .25 High level output current I OH IOH Vcc=.8V VOH=.6V.26 Low level output current I OL Ambient temerature Ta IOL 3 2 Vcc=4.5V VOL=.4V.27 Low level output current I OL IOL.5..5 Vcc=.8V VOL=.V.28 Input inversion voltage V INV Power supply voltage V CC VINV [V] Ta=25 C,SK,DI.29 Input inversion voltage V INV Vcc[V] 4 3 Vcc=5.5V,SK,DI VINV [V] 2 5

16 2.AC Characteristics 2. Maximum operation frequency f Max Power supply voltage V CC 2.2 Program time T PR Power supply voltage V CC 7 Ta=25 C 6. Ta=25 C 6 fmax [Hz] 5 4 TPR [ms] Vcc[V] 2.3 Program time T PR Vcc[V] 2.4 Program time T PR 6 Vcc=5.V 6 Vcc=3.V TPR [ms] 4 TPR [ms] Program time T PR 2.6 Data output delay time T PD 6 Vcc=.8V.4 Vcc=4.5V TPR [ms] 4 2 TPD [µs] Data output delay time T PD 2.8 Data output delay time T PD.8.6 Vcc=2.7V 2..5 Vcc=.8V TPD [µs].4 TPD [µs]

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