S-19100xxxA Series FOR AUTOMOTIVE 125 C OPERATION VOLTAGE DETECTOR BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) Features.

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1 S-9xxxA Series FOR AUTOMOTIVE 25 C OPERATION VOLTAGE DETECTOR BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) ABLIC Inc., Rev..2_2 The S-9xxxA Series, developed by using CMOS technology, is a voltage detector IC for automotive 25 C operation. The detection voltage is fixed internally with an accuracy of 3.% ( V DET = 2.4 V). It operates with current consumption of 27 na typ. The release signal can be delayed by setting a capacitor externally, and the delay time accuracy at Ta = 25 C is 5%. The operation temperature range is Ta = 4 C to 25 C. Two output forms Nch open-drain and CMOS output are available. Compared with conventional CMOS voltage detectors, the S-9xxxA Series has super-low current consumption and small packages. Caution This product can be used in vehicle equipment and in-vehicle equipment. Before using the product in the purpose, contact to ABLIC Inc. is indispensable. Features Detection voltage:.2 V to 4.6 V ( V step) Detection voltage accuracy: 3.% (2.4 V V DET 4.6 V, Ta = 4 C to 25 C) (2.5% 2 mv) (.2 V V DET 2.4 V, Ta = 4 C to 25 C) Current consumption: 27 na typ. (.2 V V DET 2.3 V) Operation voltage range:.6 V to. V (CMOS output product) Hysteresis width * : 5% 2% (Ta = 4 C to 25 C) Delay time accuracy: 5% (C D = 4.7 nf, Ta = 25 C) Output form: Nch open-drain output (active "L") CMOS output (active "L") Operation temperature range: Ta = 4 C to 25 C Lead-free (Sn %), halogen-free AEC-Q qualified *2 *. The product without hysteresis width is also available. *2. Contact our sales office for details. Applications For automotive use (engine, transmission, suspension, ABS, related-devices for EV / HEV / PHEV, etc.) Packages SOT-23-5 SC-82AB

2 S-9xxxA Series Rev..2_2 Block Diagrams. Nch open-drain output product VDD * Delay circuit * V REF * VSS *. Parasitic diode CD Figure 2. CMOS output product VDD * Delay circuit * V REF * * VSS *. Parasitic diode CD Figure 2 2

3 Rev..2_2 S-9xxxA Series AEC-Q Qualified This IC supports AEC-Q for operation temperature grade. Contact our sales office for details of AEC-Q reliability specification. Product Name Structure Users can select the output form, the detection voltage value and the package type for the S-9xxxA Series. Refer to ". Product name" regarding the contents of product name, "2. Packages" regarding the package drawings and "3. Product name list" regarding details of product name.. Product name S-9 x xx A - xxxx U *. Refer to the tape drawing. 2. Packages Environmental code U: Lead-free (Sn %), halogen-free Package abbreviation and IC packing specifications * M5T2: SOT-23-5, Tape N4T2: SC-82AB, Tape Operation temperature A: Ta = 4 C to 25 C Detection voltage value 2 to 46 (e.g., when the detection voltage is.2 V, it is expressed as 2.) Output form N: Nch open-drain output (active "L") C: CMOS output (active "L") Table Package Drawing Codes Package Name Dimension Tape Reel SOT-23-5 MP5-A-P-SD MP5-A-C-SD MP5-A-R-SD SC-82AB NP4-A-P-SD NP4-A-C-SD NP4-A-C-S NP4-A-R-SD 3

4 S-9xxxA Series Rev..2_2 3. Product name list 3. Nch open-drain output product Table 2 Detection Voltage SOT-23-5 SC-82AB.2 V (2.5% 2 mv) S-9N2A-M5T2U S-9N2A-N4T2U.3 V (2.5% 2 mv) S-9N3A-M5T2U S-9N3A-N4T2U.4 V (2.5% 2 mv) S-9N4A-M5T2U S-9N4A-N4T2U.5 V (2.5% 2 mv) S-9N5A-M5T2U S-9N5A-N4T2U.6 V (2.5% 2 mv) S-9N6A-M5T2U S-9N6A-N4T2U.7 V (2.5% 2 mv) S-9N7A-M5T2U S-9N7A-N4T2U.8 V (2.5% 2 mv) S-9N8A-M5T2U S-9N8A-N4T2U.9 V (2.5% 2 mv) S-9N9A-M5T2U S-9N9A-N4T2U 2. V (2.5% 2 mv) S-9N2A-M5T2U S-9N2A-N4T2U 2. V (2.5% 2 mv) S-9N2A-M5T2U S-9N2A-N4T2U 2.2 V (2.5% 2 mv) S-9N22A-M5T2U S-9N22A-N4T2U 2.3 V (2.5% 2 mv) S-9N23A-M5T2U S-9N23A-N4T2U 2.4 V 3.% S-9N24A-M5T2U S-9N24A-N4T2U 2.5 V 3.% S-9N25A-M5T2U S-9N25A-N4T2U 2.6 V 3.% S-9N26A-M5T2U S-9N26A-N4T2U 2.7 V 3.% S-9N27A-M5T2U S-9N27A-N4T2U 2.8 V 3.% S-9N28A-M5T2U S-9N28A-N4T2U 2.9 V 3.% S-9N29A-M5T2U S-9N29A-N4T2U 3. V 3.% S-9N3A-M5T2U S-9N3A-N4T2U 3. V 3.% S-9N3A-M5T2U S-9N3A-N4T2U 3.2 V 3.% S-9N32A-M5T2U S-9N32A-N4T2U 3.3 V 3.% S-9N33A-M5T2U S-9N33A-N4T2U 3.4 V 3.% S-9N34A-M5T2U S-9N34A-N4T2U 3.5 V 3.% S-9N35A-M5T2U S-9N35A-N4T2U 3.6 V 3.% S-9N36A-M5T2U S-9N36A-N4T2U 3.7 V 3.% S-9N37A-M5T2U S-9N37A-N4T2U 3.8 V 3.% S-9N38A-M5T2U S-9N38A-N4T2U 3.9 V 3.% S-9N39A-M5T2U S-9N39A-N4T2U 4. V 3.% S-9N4A-M5T2U S-9N4A-N4T2U 4. V 3.% S-9N4A-M5T2U S-9N4A-N4T2U 4.2 V 3.% S-9N42A-M5T2U S-9N42A-N4T2U 4.3 V 3.% S-9N43A-M5T2U S-9N43A-N4T2U 4.4 V 3.% S-9N44A-M5T2U S-9N44A-N4T2U 4.5 V 3.% S-9N45A-M5T2U S-9N45A-N4T2U 4.6 V 3.% S-9N46A-M5T2U S-9N46A-N4T2U 4

5 Rev..2_2 S-9xxxA Series 3. 2 CMOS output product Table 3 Detection Voltage SOT-23-5 SC-82AB.2 V (2.5% 2 mv) S-9C2A-M5T2U S-9C2A-N4T2U.3 V (2.5% 2 mv) S-9C3A-M5T2U S-9C3A-N4T2U.4 V (2.5% 2 mv) S-9C4A-M5T2U S-9C4A-N4T2U.5 V (2.5% 2 mv) S-9C5A-M5T2U S-9C5A-N4T2U.6 V (2.5% 2 mv) S-9C6A-M5T2U S-9C6A-N4T2U.7 V (2.5% 2 mv) S-9C7A-M5T2U S-9C7A-N4T2U.8 V (2.5% 2 mv) S-9C8A-M5T2U S-9C8A-N4T2U.9 V (2.5% 2 mv) S-9C9A-M5T2U S-9C9A-N4T2U 2. V (2.5% 2 mv) S-9C2A-M5T2U S-9C2A-N4T2U 2. V (2.5% 2 mv) S-9C2A-M5T2U S-9C2A-N4T2U 2.2 V (2.5% 2 mv) S-9C22A-M5T2U S-9C22A-N4T2U 2.3 V (2.5% 2 mv) S-9C23A-M5T2U S-9C23A-N4T2U 2.4 V 3.% S-9C24A-M5T2U S-9C24A-N4T2U 2.5 V 3.% S-9C25A-M5T2U S-9C25A-N4T2U 2.6 V 3.% S-9C26A-M5T2U S-9C26A-N4T2U 2.7 V 3.% S-9C27A-M5T2U S-9C27A-N4T2U 2.8 V 3.% S-9C28A-M5T2U S-9C28A-N4T2U 2.9 V 3.% S-9C29A-M5T2U S-9C29A-N4T2U 3. V 3.% S-9C3A-M5T2U S-9C3A-N4T2U 3. V 3.% S-9C3A-M5T2U S-9C3A-N4T2U 3.2 V 3.% S-9C32A-M5T2U S-9C32A-N4T2U 3.3 V 3.% S-9C33A-M5T2U S-9C33A-N4T2U 3.4 V 3.% S-9C34A-M5T2U S-9C34A-N4T2U 3.5 V 3.% S-9C35A-M5T2U S-9C35A-N4T2U 3.6 V 3.% S-9C36A-M5T2U S-9C36A-N4T2U 3.7 V 3.% S-9C37A-M5T2U S-9C37A-N4T2U 3.8 V 3.% S-9C38A-M5T2U S-9C38A-N4T2U 3.9 V 3.% S-9C39A-M5T2U S-9C39A-N4T2U 4. V 3.% S-9C4A-M5T2U S-9C4A-N4T2U 4. V 3.% S-9C4A-M5T2U S-9C4A-N4T2U 4.2 V 3.% S-9C42A-M5T2U S-9C42A-N4T2U 4.3 V 3.% S-9C43A-M5T2U S-9C43A-N4T2U 4.4 V 3.% S-9C44A-M5T2U S-9C44A-N4T2U 4.5 V 3.% S-9C45A-M5T2U S-9C45A-N4T2U 4.6 V 3.% S-9C46A-M5T2U S-9C46A-N4T2U 5

6 S-9xxxA Series Rev..2_2 Pin Configurations. SOT-23-5 Top view Table 4 Pin No. Symbol Description Voltage detection output pin 2 VDD Input voltage pin 3 VSS GND pin 4 NC * No connection 5 CD Connection pin for delay capacitor *. The NC pin is electrically open. The NC pin can be connected to the VDD pin or the VSS pin. Figure 3 2. SC-82AB Top view 4 3 Table 5 Pin No. Symbol Description VSS GND pin 2 VDD Input voltage pin 3 CD Connection pin for delay capacitor 4 Voltage detection output pin 2 Figure 4 6

7 Rev..2_2 S-9xxxA Series Absolute Maximum Ratings Table 6 (Ta = 4 C to 25 C unless otherwise specified) Item Symbol Absolute Maximum Rating Unit Power supply voltage V DD V SS 2 V CD pin input voltage V CD V SS.3 to V DD.3 V Output voltage Nch open-drain output product V SS.3 to 2. V V CMOS output product V SS.3 to V DD.3 V Output current I 5 ma Operation ambient temperature T opr 4 to 25 C Storage temperature T stg 4 to 5 C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Thermal Resistance Value Table 7 Item Symbol Condition Min. Typ. Max. Unit Junction-to-ambient thermal resistance * ja SOT-23-5 SC-82AB *. Test environment: compliance with JEDEC STANDARD JESD5-2A Board 92 C/W Board 2 6 C/W Board 236 C/W Board 2 24 C/W Remark Refer to " Thermal Characteristics" for details of power dissipation and test board. 7

8 S-9xxxA Series Rev..2_2 Electrical Characteristics. Nch open-drain output product Table 8 (Ta = 4 C to 25 C unless otherwise specified) Test Item Symbol Condition Min. Typ. Max. Unit Circuit Detection voltage * V DET.2 V V DET 2.4 V V DET(S) V DET(S) V DET(S).25.2 V 2.4 V V DET 4.6 V V DET(S).97 V DET(S) V DET(S).3 V Hysteresis width V HYS V DET.3 V DET.5 V DET.7 V.2 V V DET 2.3 V.27.8 A 2 Current consumption I SS V DD = V DET.6 V 2.3 V V DET 3.6 V A V V DET 4.6 V A 2 Operation voltage V DD.8. V Output current I Output transistor Nch V DS *2 =.5 V V DD =.7 V S-9N2 to 4 V DD =.2 V S-9N5 to 46 V DD = 2.4 V S-9N27 to ma ma ma 3 Leakage current I LEAK Output transistor Nch 2.4 A 3 V DD =. V, V =. V Delay time t D C D = 4.7 nf ms 4 *. V DET : Actual detection voltage value, V DET(S) : Set detection voltage value (The center value of the detection voltage range in Table 2.) *2. V DS : Drain-to-source voltage of the output transistor 8

9 Rev..2_2 S-9xxxA Series 2. CMOS output product Table 9 (Ta = 4 C to 25 C unless otherwise specified) Test Item Symbol Condition Min. Typ. Max. Unit Circuit Detection voltage * V DET.2 V V DET 2.4 V 2.4 V V DET 4.6 V Hysteresis width V HYS V DET(S) V DET(S).97 V DET.3 V DET(S) V DET(S).25.2 V DET(S) V DET(S).3 V DET.5 V DET.7 V V V.2 V V DET 2.3 V.27.8 A 2 Current consumption I SS V DD = V DET.6 V 2.3 V V DET 3.6 V A V V DET 4.6 V A 2 Operation voltage V DD.6. V Output current I Output transistor Nch V DS *2 =.5 V Output transistor Pch V DS *2 =.5 V V DD =.7 V S-9C2 to 4 V DD =.2 V S-9C5 to 46 V DD = 2.4 V S-9C27 to 46 V DD = 4.8 V S-9C2 to 39 V DD = 6. V S-9C4 to ma ma ma ma ma 5 Delay time t D C D = 4.7 nf ms 4 *. V DET : Actual detection voltage value, V DET(S) : Set detection voltage value (The center value of the detection voltage range in Table 3.) *2. V DS : Drain-to-source voltage of the output transistor 9

10 S-9xxxA Series Rev..2_2 Test Circuits A V DD V VDD VSS CD V R * k V DD VDD VSS CD *. R is unnecessary for CMOS output product. Figure 5 Test Circuit Figure 6 Test Circuit 2 V DD V VDD VSS CD V A V DS P.G. VDD VSS CD R * k Oscilloscope *. R is unnecessary for CMOS output product. Figure 7 Test Circuit 3 Figure 8 Test Circuit 4 V DD V VDD V A V DS VSS CD Figure 9 Test Circuit 5

11 Rev..2_2 S-9xxxA Series Timing Charts. Nch open-drain output product Hysteresis width (V HYS ) V DD Release voltage ( V DET ) Detection voltage ( V DET ) Minimum operation voltage V SS VDD R k V DD Output from the pin CD VSS V V SS t D Figure 2. CMOS output product Hysteresis width (V HYS ) V DD Release voltage ( V DET ) Detection voltage ( V DET ) Minimum operation voltage VDD V SS CD VSS V V DD Output from the pin V SS t D Remark When V DD is the minimum operation voltage or less, the output voltage from the pin is indefinite in the shaded area. Figure

12 S-9xxxA Series Rev..2_2 Operation. Basic operation: CMOS output (active "L") product () When the power supply voltage (V DD ) is the release voltage ( V DET ) or higher, the Nch transistor is turned off and the Pch transistor is turned on to output V DD ("H"). Since the Nch transistor N in Figure 2 is turned off, (R B R C ) V DD the input voltage to the comparator is. R A R B R C (2) Even if V DD decreases to V DET or lower, V DD is output when V DD is higher than the detection voltage ( V DET ). When V DD decreases to V DET (point A in Figure 3) or lower, the Nch transistor is turned on and the Pch transistor is turned off, and then V SS ("L") is output. At this time, the Nch transistor N in Figure 2 is turned R B V DD on, and the input voltage to the comparator is. R A R B (3) The output is unstable if V DD further decreases to the IC's minimum operation voltage or lower, and the output is V DD when the output is pulled up. (4) V SS is output when V DD increases to the minimum operation voltage or higher. Even if V DD exceeds V DET, the output is V SS when V DD is lower than V DET. (5) When V DD increases to V DET (point B in Figure 3) or higher, the Nch transistor is turned off and the Pch transistor is turned on, and then V DD is output. At this time, V DD is output from the pin after the elapse of the delay time (t D ). VDD * R A Delay circuit Pch * V REF R B * Nch * VSS R C N CD C D *. Parasitic diode Figure 2 Operation () (2) (3) (4) (5) Hysteresis width (V HYS ) A B V DD Release voltage ( V DET ) Detection voltage ( V DET ) Minimum operation voltage V SS V DD Output from pin V SS t D Figure 3 Operation 2 2

13 Rev..2_2 S-9xxxA Series 2. Delay circuit The delay circuit delays the output signal to the pin from the time at which the power supply voltage (V DD ) exceeds the release voltage ( V DET ) when the power supply voltage (V DD ) is turned on. The output signal is not delayed when V DD decreases to the detection voltage ( V DET ) or less (refer to "Figure 3 Operation 2"). The delay time (t D ) is determined by the time constant of the built-in constant current (approx. na) and the attached delay capacitor (C D ), or the delay time when the CD pin is open (t D ), and calculated from the following equation. When the C D value is sufficiently large, the t D value can be ignored. t D [ms] = Delay coefficient C D [nf] t D [ms] Operation Temperature Table Delay Coefficient Delay Coefficient Min. Typ. Max. Ta = 25 C Ta = 5 C Ta = 25 C Ta = 4 C Operation Temperature Table Delay Time Delay Time when CD pin is Open (t D ) Min. Typ. Max. Ta = 4 C to 25 C. ms ms.8 ms Caution. When the CD pin is open, a double pulse shown in Figure 4 may appear at release. To avoid the double pulse, attach pf or more capacitor to the CD pin. Do not apply voltage to the CD pin from the exterior. V Time Figure 4 2. Mounted board layout should be made in such a way that no current flows into or flows from the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be provided. 3. There is no limit for the capacitance of C D as long as the leakage current of the capacitor can be ignored against the built-in constant current value. Leakage current causes deviation in delay time. When the leakage current is larger than the built-in constant current, no release takes place. 3

14 S-9xxxA Series Rev..2_2 Standard Circuit VDD R * k CD C D *2 VSS *. R is unnecessary for CMOS output products. *2. The delay capacitor (C D ) should be connected directly to the CD pin and the VSS pin. Figure 5 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 4

15 Rev..2_2 S-9xxxA Series Explanation of Terms. Detection voltage ( V DET ) The detection voltage is a voltage at which the output in Figure 8 turns to "L". The detection voltage varies slightly among products of the same specification. The variation of detection voltage between the specified minimum ( V DET min.) and the maximum ( V DET max.) is called the detection voltage range (refer to Figure 6). Example: In the S-9C2A, the detection voltage is either one in the range of.938 V V DET 2.62 V. This means, at the operation temperature 4 C to 25 C, some S-9C2A have V DET =.938 V and some have V DET = 2.62 V. 2. Release voltage ( V DET ) The release voltage is a voltage at which the output in Figure 8 turns to "H". The release voltage varies slightly among products of the same specification. The variation of release voltages between the specified minimum ( V DET min.) and the maximum ( V DET max.) is called the release voltage range (refer to Figure 7). The value is calculated from the actual detection voltage ( V DET ) of a product and is in the range of V DET.3 V DET V DET.7. Example: In the S-9C2A, the release voltage is either one in the range of.997 V V DET 2.26 V. This means, at the operation temperature 4 C to 25 C, some S-9C2A have V DET =.997 V and some have V DET = 2.26 V. V DD V DET max. V DET min. Detection voltage Detection voltage range Release voltage V DET max. V DET min. V DD Release voltage range Delay time Figure 6 Detection Voltage Figure 7 Release Voltage R * V DD V VDD VSS CD C D k V *. R is unnecessary for CMOS output product. Figure 8 Test Circuit of Detection Voltage and Release Voltage 5

16 S-9xxxA Series Rev..2_2 3. Hysteresis width (V HYS ) The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at point B the voltage at point A = V HYS in "Figure 3 Operation 2"). Setting the hysteresis width between the detection voltage and the release voltage to prevent malfunction caused by noise on the input voltage. 4. Delay time (t D ) The delay time in the S-9xxxA Series is a period from the input voltage to the VDD pin exceeding the release voltage ( V DET ) until the output from the pin inverts. The delay time changes according to the delay capacitor (C D ). V DD V DET 5. Feed-through current t D Figure 9 Delay Time Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product. 6. Oscillation In applications where a resistor is connected to the voltage detector input (Figure 2), taking a CMOS output (active "L") product for example, the feed-through current which is generated when the output goes from "L" to "H" (release) causes a voltage drop equal to [feed-through current] [input resistance] across the resistor. When the input voltage drops below the detection voltage ( V DET ) as a result, the output voltage goes to low level. In this state, the feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces oscillation. VDD R A V IN S-9C R B VSS Figure 2 Example for Bad Implementation Due to Detection Voltage Change 6

17 Rev..2_2 S-9xxxA Series Precautions Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. In CMOS output product, the feed-through current flows at the detection and the release. If the input impedance is high, oscillation may occur due to the voltage drop by the feed-through current during releasing. In CMOS output product, oscillation may occur when a pull-down resistor is used, and falling speed of the power supply voltage (V DD ) is slow near the detection voltage. When designing for mass production using an application circuit described herein, the product deviation and temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any responsibility for patent infringements related to products using the circuits described herein. ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 7

18 S-9xxxA Series Rev..2_2 Characteristics (Typical Data). Detection voltage (V DET ) vs. Temperature (Ta) S-9N2.4 VDET [V] VDET VDET Ta [ C] S-9N VDET VDET Ta [ C] VDET [V] 2. Hysteresis width (V HYS ) vs. Temperature (Ta) S-9N2 8 VHYS [%] Ta [ C] S-9N46 8 VHYS [%] Ta [ C] 3. Current consumption (I SS ) vs. Input voltage (V DD ) S-9C Ta = +25 C.5 Ta = +5 C.25 Ta = +25 C Ta = 4 C ISS [μa] VDD [V] S-9C ISS [μa] 2. Ta = +25 C Ta = +5 C Ta = +25 C Ta = 4 C 4. VDD [V] Current consumption (I SS ) vs. Temperature (Ta) S-9N2/9C2. V DD = V DET.6 V S-9N46/9C46. V DD = V DET.6 V ISS [μa] S-9C2 S-9N Ta [ C] ISS [μa] S-9C46 S-9N Ta [ C] 8

19 Rev..2_2 S-9xxxA Series 5. Nch transistor output current (I ) vs. V DS S-9N I [ma].5. VDD =.2 V VDD =. V.5 VDD = 3.6 V 2. VDS [V] 2.5 Ta = 4 C VDD = 2.4 V S-9N I [ma].5. VDD =.2 V VDD =. V.5 VDD = 3.6 V 2. VDS [V] 2.5 Ta = 25 C VDD = 2.4 V S-9N46 Ta = 5 C VDD = 3.6 V 8 6 VDD =. V VDD = 2.4 V 4 2 VDD =.2 V I [ma] VDS [V] S-9N46 Ta = 25 C VDD = 3.6 V 8 6 VDD =. V VDD = 2.4 V 4 2 VDD =.2 V I [ma] VDS [V] 6. Pch transistor output current (I ) vs. V DS S-9C I [ma] Ta = 4 C VDD = 8.4 V VDD = 7.2 V VDD = 6. V VDD = 4.8 V VDD = 3.6 V VDD = 2.4 V VDS [V] S-9C I [ma]. 2. VDD = 8.4 V VDD = 7.2 V VDS [V] 6. Ta = 25 C VDD = 6. V VDD = 4.8 V VDD = 3.6 V VDD = 2.4 V S-9C I [ma]. Ta = 5 C VDD = 8.4 V VDD = 7.2 V VDD = 6. V VDD = 4.8 V VDD = 3.6 V VDD = 2.4 V VDS [V] S-9C I [ma]. Ta = 25 C VDD = 8.4 V VDD = 7.2 V VDD = 6. V VDD = 4.8 V VDD = 3.6 V VDD = 2.4 V VDS [V] Remark V DS : Drain-to-source voltage of the output transistor 9

20 S-9xxxA Series Rev..2_2 7. Nch transistor output current (I ) vs. Input voltage (V DD ) S-9N I [ma] Ta = 4 C Ta = +25 C. Ta = +5 C Ta = +25 C VDD [V] 4. V DS =.5 V 8. Pch transistor output current (I ) vs. Input voltage (V DD ) S-9C Ta = 4 C 3. Ta = +25 C I [ma] VDD [V] V DS =.5 V Ta = +5 C Ta = +25 C Minimum operation voltage (V ) vs. Input voltage (V DD ) S-9N2.6 Pull-up to V DD Pull-up resistance: k S-9N46 6 Pull-up to V DD Pull-up resistance: k V [V] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C.6.8 VDD [V]..2.4 V [V] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C. 2. VDD [V] S-9N2 2 Pull-up to V Pull-up resistance: k S-9N46 2 Pull-up to V Pull-up resistance: k V [V] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C V [V] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C VDD [V] VDD [V] Remark V DS : Drain-to-source voltage of the output transistor 2

21 Rev..2_2 S-9xxxA Series. Dynamic response characteristics vs. Output pin capacitance (C ) (CD pin; open). V DET =.2 V S-9C2 Ta = 4 C S-9N2 Ta = 4 C Response time [ms]... tplh tphl... C [μf] Response time [ms]... tplh tphl... C [μf] S-9C2 Ta = 25 C S-9N2 Ta = 25 C Response time [ms]... tplh tphl... C [μf] Response time [ms]... tplh tphl... C [μf] S-9C2 Ta = 5 C S-9N2 Ta = 5 C Response time [ms]... tplh tphl... C [μf] Response time [ms]... tplh tphl... C [μf] S-9C2 Ta = 25 C S-9N2 Ta = 25 C Response time [ms]... tplh tphl... C [μf] Response time [ms]... tplh tphl.. C [μf]. 2

22 S-9xxxA Series Rev..2_2. 2 V DET = 4.6 V S-9C46 Ta = 4 C S-9N46 Ta = 4 C Response time [ms]... tplh tphl... C [μf] Response time [ms]. tplh tphl.... C [μf]. S-9C46 Ta = 25 C S-9N46 Ta = 25 C Response time [ms]... tplh tphl... C [μf] Response time [ms]. tplh tphl.... C [μf]. S-9C46 Ta = 5 C S-9N46 Ta = 5 C Response time [ms]... tplh tphl... C [μf] Response time [ms]. tplh tphl.... C [μf]. S-9C46 Ta = 25 C S-9N46 Ta = 25 C Response time [ms]... tplh tphl... C [μf] Response time [ms]. tplh tphl.... C [μf]. 22

23 Rev..2_2 S-9xxxA Series s s V IH * Input voltage *2 V IL *3 V DD Output voltage t PHL t PLH V DD *3 9% V DD V R * VDD k * VSS CD V DD C V V DD *3 % *. V IH = V *2. V IL =.8 V *3. CMOS output product: V DD Nch open-drain product: V DD Figure 2 Test Condition of Response Time *. R and V DD are unnecessary for CMOS output product. Figure 22 Test Circuit of Response Time Caution. The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 2. When the CD pin is open, a double pulse may appear at release. To avoid the double pulse, attach pf or more capacitor to the CD pin. Response time when detecting (t PHL ) is not affected by CD pin capacitance. Besides, response time when releasing (t PLH ) can be set the delay time by attaching CD pin. Refer to ". Delay time (t D ) vs. CD pin capacitance (C D ) (without output pin capacitance) for details.. Delay time (t D ) vs. CD pin capacitance (C D ) (without output pin capacitance) S-9C2 td [ms] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C S-9C46 td [ms] Ta = 4 C Ta = +25 C Ta = +5 C Ta = +25 C CD [nf] CD [nf] 23

24 S-9xxxA Series Rev..2_2 2. Delay time (t D ) vs. Temperature (Ta) S-9N2 5 td [ms] C D = 4.7 nf Ta [ C] S-9N46 5 td [ms] C D = 4.7 nf Ta [ C] s V IH * Input voltage V IL *2 Output voltage t D V DD 9% V DD V VDD VSS CD C D R * k V V SS *. V IH = V *2. V IL =.8 V Figure 23 Test Condition of Delay Time *. R is unnecessary for CMOS output product. Figure 24 Test Circuit of Delay Time Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 24

25 Rev..2_2 S-9xxxA Series Application Circuit Examples. Microcomputer reset circuits In microcomputers, when the power supply voltage is lower than the minimum operation voltage, an unspecified operation may be performed or the contents of the memory register may be lost. When power supply voltage returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched off or lowered. Using the S-9xxxA Series which has the low minimum operation voltage, a high-accuracy detection voltage and hysteresis, reset circuits can be easily constructed as seen in Figure 25 and Figure 26. VDD VDD VDD2 S-9C Microcomputer S-9N Microcomputer VSS VSS Figure 25 Example of Reset Circuit (CMOS Output Product) Figure 26 Example of Reset Circuit (Nch Open-drain Output Product) Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 25

26 S-9xxxA Series Rev..2_2 2. Power-on reset circuit (Nch open-drain output product only) A power-on reset circuit can be constructed using the S-9NxxA Series. VDD R A * (R A k ) VIN Di *2 S-9N R k C (Nch open-drain output product) VSS *. R A should be k or less to prevent oscillation. *2. Diode (Di) instantaneously discharges the charge stored in the capacitor (C) at the power falling. Di can be removed when the delay of the falling time is not important. Figure 27 V DD [V] [V] t [s] t [s] Figure 28 Remark When the power rises sharply, the output may instantaneously be set to the "H" level due to the IC s indefinite area (the output voltage is indefinite when it is the IC s minimum operation voltage or less), as seen in Figure 29. V DD [V] [V] t [s] t [s] Figure 29 Caution. The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 2. Note that the hysteresis width may be larger as the following equation shows when using the above connection. Perform thorough evaluation using the actual application to set the constant. Maximum hysteresis width = V HYS R A 2 A 26

27 Rev..2_2 S-9xxxA Series 3. Change of detection voltage (Nch open-drain output product only) If there is not a product with a specified detection voltage value in the S-9NxxA Series, the detection voltage can be changed by using a resistance divider or a diode, as seen in Figure 3 and Figure 3. In Figure 3, the hysteresis width also changes. VDD VDD R A * (R A k ) VIN S-9N R k V f VIN S-9N R k R B (Nch open-drain ouput product) (Nch open-drain output product) VSS VSS Detection voltage = R A R B R B Hysteresis width = R A R B R B V DET V HYS *. R A should be k or less to prevent oscillation. Detection voltage = V f ( V DET ) Caution If R A and R B are large, the hysteresis width may also be larger than the value given by the above equation due to the feed-through current. Figure 3 Figure 3 Caution. The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 2. Note that the hysteresis width may be larger as the following equation shows when using the above connections. Perform thorough evaluation using the actual application to set the constant. Maximum hysteresis width = R A R B R B V HYS R A 2 A 27

28 S-9xxxA Series Rev..2_2 Marking Specifications. SOT-23-5 Top view 5 4 () to (3): Product code (Refer to Product name vs. Product code) (4): Lot number () (2) (3) (4) 2 3 Product name vs. Product code. Nch open-drain output product. 2 CMOS output product Product Name Product Code Product Code Product Name () (2) (3) () (2) (3) S-9N2A-M5T2U 3 N A S-9C2A-M5T2U 3 M A S-9N3A-M5T2U 3 N B S-9C3A-M5T2U 3 M B S-9N4A-M5T2U 3 N C S-9C4A-M5T2U 3 M C S-9N5A-M5T2U 3 N D S-9C5A-M5T2U 3 M D S-9N6A-M5T2U 3 N E S-9C6A-M5T2U 3 M E S-9N7A-M5T2U 3 N F S-9C7A-M5T2U 3 M F S-9N8A-M5T2U 3 N G S-9C8A-M5T2U 3 M G S-9N9A-M5T2U 3 N H S-9C9A-M5T2U 3 M H S-9N2A-M5T2U 3 N I S-9C2A-M5T2U 3 M I S-9N2A-M5T2U 3 N J S-9C2A-M5T2U 3 M J S-9N22A-M5T2U 3 N K S-9C22A-M5T2U 3 M K S-9N23A-M5T2U 3 N L S-9C23A-M5T2U 3 M L S-9N24A-M5T2U 3 N M S-9C24A-M5T2U 3 M M S-9N25A-M5T2U 3 N N S-9C25A-M5T2U 3 M N S-9N26A-M5T2U 3 N O S-9C26A-M5T2U 3 M O S-9N27A-M5T2U 3 N P S-9C27A-M5T2U 3 M P S-9N28A-M5T2U 3 N Q S-9C28A-M5T2U 3 M Q S-9N29A-M5T2U 3 N R S-9C29A-M5T2U 3 M R S-9N3A-M5T2U 3 N S S-9C3A-M5T2U 3 M S S-9N3A-M5T2U 3 N T S-9C3A-M5T2U 3 M T S-9N32A-M5T2U 3 N U S-9C32A-M5T2U 3 M U S-9N33A-M5T2U 3 N V S-9C33A-M5T2U 3 M V S-9N34A-M5T2U 3 N W S-9C34A-M5T2U 3 M W S-9N35A-M5T2U 3 N X S-9C35A-M5T2U 3 M X S-9N36A-M5T2U 3 N Y S-9C36A-M5T2U 3 M Y S-9N37A-M5T2U 3 N Z S-9C37A-M5T2U 3 M Z S-9N38A-M5T2U 3 N S-9C38A-M5T2U 3 M S-9N39A-M5T2U 3 N 2 S-9C39A-M5T2U 3 M 2 S-9N4A-M5T2U 3 N 3 S-9C4A-M5T2U 3 M 3 S-9N4A-M5T2U 3 N 4 S-9C4A-M5T2U 3 M 4 S-9N42A-M5T2U 3 N 5 S-9C42A-M5T2U 3 M 5 S-9N43A-M5T2U 3 N 6 S-9C43A-M5T2U 3 M 6 S-9N44A-M5T2U 3 N 7 S-9C44A-M5T2U 3 M 7 S-9N45A-M5T2U 3 N 8 S-9C45A-M5T2U 3 M 8 S-9N46A-M5T2U 3 N 9 S-9C46A-M5T2U 3 M 9 28

29 Rev..2_2 S-9xxxA Series 2. SC-82AB 4 Top view 3 () to (3): Product code (Refer to Product name vs. Product code) () (2) (3) 2 Product name vs. Product code 2. Nch open-drain output product 2. 2 CMOS output product Product Name Product Code Product Code Product Name () (2) (3) () (2) (3) S-9N2A-N4T2U 3 N A S-9C2A-N4T2U 3 M A S-9N3A-N4T2U 3 N B S-9C3A-N4T2U 3 M B S-9N4A-N4T2U 3 N C S-9C4A-N4T2U 3 M C S-9N5A-N4T2U 3 N D S-9C5A-N4T2U 3 M D S-9N6A-N4T2U 3 N E S-9C6A-N4T2U 3 M E S-9N7A-N4T2U 3 N F S-9C7A-N4T2U 3 M F S-9N8A-N4T2U 3 N G S-9C8A-N4T2U 3 M G S-9N9A-N4T2U 3 N H S-9C9A-N4T2U 3 M H S-9N2A-N4T2U 3 N I S-9C2A-N4T2U 3 M I S-9N2A-N4T2U 3 N J S-9C2A-N4T2U 3 M J S-9N22A-N4T2U 3 N K S-9C22A-N4T2U 3 M K S-9N23A-N4T2U 3 N L S-9C23A-N4T2U 3 M L S-9N24A-N4T2U 3 N M S-9C24A-N4T2U 3 M M S-9N25A-N4T2U 3 N N S-9C25A-N4T2U 3 M N S-9N26A-N4T2U 3 N O S-9C26A-N4T2U 3 M O S-9N27A-N4T2U 3 N P S-9C27A-N4T2U 3 M P S-9N28A-N4T2U 3 N Q S-9C28A-N4T2U 3 M Q S-9N29A-N4T2U 3 N R S-9C29A-N4T2U 3 M R S-9N3A-N4T2U 3 N S S-9C3A-N4T2U 3 M S S-9N3A-N4T2U 3 N T S-9C3A-N4T2U 3 M T S-9N32A-N4T2U 3 N U S-9C32A-N4T2U 3 M U S-9N33A-N4T2U 3 N V S-9C33A-N4T2U 3 M V S-9N34A-N4T2U 3 N W S-9C34A-N4T2U 3 M W S-9N35A-N4T2U 3 N X S-9C35A-N4T2U 3 M X S-9N36A-N4T2U 3 N Y S-9C36A-N4T2U 3 M Y S-9N37A-N4T2U 3 N Z S-93C7A-N4T2U 3 M Z S-9N38A-N4T2U 3 N S-9C38A-N4T2U 3 M S-9N39A-N4T2U 3 N 2 S-9C39A-N4T2U 3 M 2 S-9N4A-N4T2U 3 N 3 S-9C4A-N4T2U 3 M 3 S-9N4A-N4T2U 3 N 4 S-9C4A-N4T2U 3 M 4 S-9N42A-N4T2U 3 N 5 S-9C42A-N4T2U 3 M 5 S-9N43A-N4T2U 3 N 6 S-9C43A-N4T2U 3 M 6 S-9N44A-N4T2U 3 N 7 S-9C44A-N4T2U 3 M 7 S-9N45A-N4T2U 3 N 8 S-9C45A-N4T2U 3 M 8 S-9N46A-N4T2U 3 N 9 S-9C46A-N4T2U 3 M 9 29

30 S-9xxxA Series Rev..2_2 Thermal Characteristics. SOT Tj = 25 C max. Power dissipation (PD) [W] Board 2.63 W Board.52 W 5 5 Ambient temperature (Ta) [ C] Figure 32 Power Dissipation of Package (When Mounted on Board). Board * 76.2 mm Table 2 Figure mm Item Thermal resistance value ( ja ) 92 C/W Specification Size 4.3 mm 76.2 mm t.6 mm Material FR-4 Number of copper foil layer 2 Land pattern and wiring for testing: t.7 mm 2 Copper foil layer mm 74.2 mm t.7 mm Thermal via. 2 Board 2 * 76.2 mm Table 3 Figure mm Item Thermal resistance value ( ja ) 6 C/W Specification Size 4.3 mm 76.2 mm t.6 mm Material FR-4 Number of copper foil layer 4 Land pattern and wiring for testing: t.7 mm mm 74.2 mm t.35 mm Copper foil layer mm 74.2 mm t.35 mm mm 74.2 mm t.7 mm Thermal via *. The board is same in SOT-23-3, SOT-23-5 and SOT

31 Rev..2_2 S-9xxxA Series 2. SC-82AB. Tj = 25 C max. Power dissipation (PD) [W] Board 2.49 W Board.42 W 5 5 Ambient temperature (Ta) [ C] Figure 35 Power Dissipation of Package (When Mounted on Board) 2. Board 76.2 mm Table 4 Figure mm Item Thermal resistance value ( ja ) 236 C/W Specification Size 4.3 mm 76.2 mm t.6 mm Material FR-4 Number of copper foil layer 2 Land pattern and wiring for testing: t.7 mm 2 Copper foil layer mm 74.2 mm t.7 mm Thermal via 2. 2 Board mm Table 5 Figure mm Item Thermal resistance value ( ja ) 24 C/W Specification Size 4.3 mm 76.2 mm t.6 mm Material FR-4 Number of copper foil layer 4 Land pattern and wiring for testing: t.7 mm mm 74.2 mm t.35 mm Copper foil layer mm 74.2 mm t.35 mm mm 74.2 mm t.7 mm Thermal via 3

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39 Disclaimers (Handling Precautions). All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein. 4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the products outside their specified ranges. 5. When using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc. Especially, the products cannot be used for life support devices, devices implanted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility.. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use.. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 2. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 3. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party without the express permission of ABLIC Inc. is strictly prohibited. 4. For more details on the information described herein, contact our sales office