THE CHARACTERIZATION OF CHROMELESS PHASE SHIFT MASK TECHNIQUE FOR SUB-45NM LITHOGRAPHY TAN SOON YOENG

Transcription

1 THE CHARACTERIZATION OF CHROMELESS PHASE SHIFT MASK TECHNIQUE FOR SUB-45NM LITHOGRAPHY TAN SOON YOENG NATIONAL UNIVERSITY OF SINGAPORE 2008

2 THE CHARACTERIZATION OF CHROMELESS PHASE SHIFT MASK TECHNIQUE FOR SUB-45NM LITHOGRAPHY TAN SOON YOENG (B.Eng.(Hons.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF MECHANICAL ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008

3 Acknowledgements I would like to express my deepest gratitude to my kindness research advisors, Professor Tay Cho Jui and Professor Quan Chenggen for the invaluable advice and consistent supervision in this thesis. Without their support, this work would not have progressed as smoothly as it had. I would also like to express heartfelt gratitude to my mentor at Chartered Semiconductor Manufacturing Ltd, Dr Lin Qunying for all resources, encouragement and invaluable discussions. I would like to thank J. Fung Chen, Michael Hsu, Stephen D. Hsu and Alex Chew of ASML for their helpful discussions. Also thanks to DNP for the Chromeless Phase Lithography (CPL) mask making support and fruitful discussion. I wish to express my appreciation to my fellow friends in Chartered Semiconductor Manufacturing Ltd, Gek Soon, Serene and Sia Kim for their advice and discussion in this thesis. Last but not least, I would like to thank those who may be concerned in giving me both technical and spiritual support to make this thesis success. Thank you. i

4 Summary The advancement of semiconductor device fabrication has depended heavily on the evolution of optical lithography technologies. However, conventional optical lithography has reached the resolution limit. To overcome the barrier, many approaches have come under intense investigation. One way to achieve improvements in resolution is to simply migrate to a shorter wavelength optical lithography system. Unfortunately, a change of wavelength typically requires large capital expense and significant process development efforts. Another alternative is to take advantages of RET (Resolution Enhancement Techniques) that uses existing techniques which is available on the existing optical lithography tool. Several RET such as OPC (Optical Proximity Correction), PSM (Phase Shift Mask), OAI (Off Axis Illumination) and polarization has been introduced to extend the life time of optical lithography. Chromeless Phase Lithography (CPL) has been considered as one of the most practical RET solutions providing low MEEF (Mask Error Enhancement Factor) and high resolution to support aggressive industry roadmap. There are several papers that show the advantages of the CPL compared to other types of RET. In this study, theoretical background of CPL is investigated. Several primary RET are adopted to enhance the lithographic performance. Simulation and experimental results are compared and discussed. The study covers CPL data generation, mask fabrication, wafer printing and ii

5 data collection on physical wafer. Limitations of mask fabrication are explored and taken into consideration during data generation. CPL data tapeout procedure and mask fabrication flow are discussed and proposed. Four major areas of process window optimization are investigated systematically. CPL data handling, which include three-zone layout decomposition, OPC and SRAF (Subresolution Assist Feature) placement rule are studied. The original design data is split into pure phase, zebra and pure chrome type based on feature size. To enhance resolution, pure phase type is used as MEEF is low. Zebra type and pure chrome type are used for feature size bigger than 75 nm and 180 nm respectively. The results of optimizing illumination are presented and discussed. The 2D overlap region of diffraction order within the entrance pupil is analyzed. The investigation shows that process window can be improved through background noise reduction and illumination optimization. From mask making point of view, 3D mask effect and quartz depth optimization are also verified. The investigation shows that a 180 phase for CPL mask in 193 nm lithography is not optimized. The effective phase is 205 instead. High NA vector effects with considerable polarization and immersion lithography are introduced. Simulation results show DoF can be improved through polarization. By migrating from dry to wet lithography system, a 60% improvement in DoF is observed. iii

6 Table of Contents Acknowledgments Summary Table of Contents List of Tables List of Figures Nomenclature i ii iv vii viii xiii 1. Introduction Background Research Contributions Outline 7 2. Literature Review The evolution of integrated circuit The evolution of lithography tool Contact printing and proximity printing: Projection Printing: High NA and immersion photolithography: 2003 present Extending optical lithography with Resolution Enhancement Techniques (RET) Optical Proximity Correction (OPC) 20 iv

7 2.3.2 Phase Shift Mask (PSM) Off Axis Illumination (OAI) Polarization effects in optical lithography Theoretical Analysis Rayleigh Criterion and the extension Chromeless Phase Lithography (CPL) mask transmittance and diffraction orders Simulation Work Simulation models Lithocruiser CPL Builder Maskweaver Empirical Model Optical Proximity Correction SOLID E Experimental Work Chromeless Phase Lithography (CPL) mask tapeout Chromeless Phase Lithography (CPL) mask fabrication process Chromeless Phase Lithography (CPL) mask wafer printing Lithography tool FEM (Focus Exposure Matrix) wafers Process window DOE (Design of experimental) 74 v

8 6. Results and Discussion Data handling optimization Three zone layout splitting Implementation of OPC (Optical Proximity Correction) and SRAF (Sub-resolution Assist Feature) Illumination optimization Effects of 3D mask Quartz etch optimization Effects of phase variation Effects of high NA vector Polarization effects Immersion lithography Conclusions and Recommendations for Future Work Conclusions Recommendations for future work 119 List of Publications 120 References 121 Appendix A 129 Appendix B 136 vi

9 List of Tables 5.1 Design of experiment I Design of experiment II Optical Proximity Correction (OPC) bias and SRAF (Sub-resolution Assist Feature) placement rules Calculated optimum illumination setting (NA/Sigma) with Lithocruiser of ASML 106 vii

10 List of Figures 1.1 Chromeless Phase Lithography (CPL) and layout decomposition Schematics of (a) contact printing and (b) proximity printing Schematics of various types of projection system GCA 4800 DSW 10:1 Reduction Stepper Schematic diagram of wafer-immersion lithography tool Illustration of serifs, hammerhead and SRAF with main feature Schematic diagram for a conventional binary mask Schematic diagram for an attenuated phase shift mask (Att-PSM) Schematic diagram for an alternating phase shift mask (Alt-PSM) Schematic diagram for a chromeless phase lithography (CPL) mask Three point sources: 0th order, 1st order and -1st order Schematic of (a) on axis illumination and (b) off axis illumination on a small diffraction angle / big slit Schematic of (a) on axis illumination and (b) off axis illumination on a big diffraction angle / small slit Common off axis illumination configuration (a) quadrupole, (b) dipole (c) annular Polarization effects on low NA and high NA lens Source Polarization (a) homogeneous (b) inhomogeneous Imaging in Optical Lithography Effect of varying NA on Depth of Focus (DoF) Schematic dry and immersion systems 40 viii

11 4.1 Graphic User Interface (GUI) of Lithocruiser of ASML Graphic User Interface (GUI) of CPL Builder of ASML Illustration of original data, mesa, chrome and simulated contour layers Sample of Scanning Electron Microscope (SEM) images Maskweaver empirical model OPC calibrations steps Graphic User Interface (GUI) of Solid E simulator Solid E parameters setting on illuminators and exposure conditions D and 3D view of CPL mask: Isolated pure phase feature D and 3D view of CPL mask: Isolated pure phase feature with SRAF D and 3D view of CPL mask: Isolated zebra feature D and 3D view of CPL mask: Isolated zebra feature with SRAF D and 3D view of CPL mask: Dense pure phase feature D and 3D view of CPL mask: Dense zebra feature Chromeless Phase Lithography (CPL) mask tapeout flow Layout decomposition of original data to different mask types with SRAF Chromeless Phase Lithography (CPL) 1st and 2nd mask write data Chromeless Phase Lithography (CPL) physical mask data Chromeless Phase Lithography (CPL) mask fabrication process flow FEM (Focus Exposure Matrix) wafer setting Experimental results for CPL wafer CD against designed CD Experimental results for MEEF against designed CD for CPL pure phase type 78 ix

12 6.3 Diffraction order ratio against designed CD at 160 nm pitch Comparison of depth of focus from experimental results by comparing different mask types and off axis illumination (OAI) at designed pitch of 160 nm Top-down SEM view of 40 nm pure phase mask features at a pitch of 160 nm Top-down SEM view of 40 nm pure phase mask features at a pitch of 140 nm Through pitch structure at a pitch of 160 nm with OPC and SRAF Through pitch structure at a pitch of 250 nm with OPC and SRAF Comparison of experimental results for isolated main features (CD: 30 nm - 90 nm) with and without SRAF Comparison of experimental results for isolated main features (CD: 120 nm nm) with and without SRAF DoF against designed CD for pure phase type (with and without SRAF for both annular and quasar illumination) DoF against designed CD for zebra type (with and without SRAF for both annular and quasar illumination) SRAF placement in a variety of pitches of main features Top-down SEM view of zebra type (without OPC, through pitch test pattern) with annular illumination and 0.85 NA Top-down SEM view of zebra type (without OPC, through pitch test pattern) with quasar illumination and 0.85 NA Top-down SEM view of pure phase type (without OPC, through pitch test pattern) with annular illumination and 0.85 NA Top-down SEM view of pure phase type (without OPC, through pitch test pattern) with quasar illumination and 0.85 NA Top-down SEM view of OPC through pitch test pattern (with SRAF) with annular illumination and 0.85 NA 99 x

13 6.19 Top-down SEM view of OPC through pitch test pattern (with SRAF) with quasar illumination and 0.85 NA Through pitch performance for zebra and pure phase feature (without OPC and SRAF) Through pitch performance for feature with OPC and SRAF Comparison of experimental results for semi-dense main features (Pitch: 250 nm and 360 nm) with and without SRAF On-axis illumination: Conventional Off-axis illumination: Quasar Off-axis illumination: Annular Off-axis illumination: High Sigma Off-axis illumination: Multipole Off-axis illumination: Multipole Depth of focus (DoF) improvement by changing illumination type (a) Pure Phase Type CPL (b) Zebra Type CPL Simulated Bossung curves at a pitch of 180 nm against different quartz depths Simulated Bossung curves at a pitch of 350 nm against different quartz depths Simulated Bossung curves at a pitch of 840 nm against different quartz depths D mask simulation results at a pitch of 180 nm D mask simulation results at a pitch of 350 nm D mask simulation results at a pitch of 840 nm Simulated results of phase variation effects against effective phase angle Simulated results of polarization effects against polarization types 114 xi

14 6.38 Simulated results of quartz etch impact on both dry and immersion lithography 115 xii

15 Nomenclature d f x g i k k 1 k 2 n p s w z A E F F I P T(x) λ θ Resist thickness Pupil frequency coordinate Distance between the photomask and the resist surface A complex number Extinction coefficient Measure of lithography aggressiveness Measure of process aggressiveness Reflective index Pitch Line space Line width Photoresist thickness Wave amplitude Electric field Fourier transform operator Inverse transform operator Intensity at the image plane Pupil function Transmittance function Exposure wavelength Highest diffracted angle that can be captured by the lens xiii

16 φ (x) Phase change Alt-PSM Att-PSM ARC CD CMOS CoG CPL DFM DICD DOE DoF DPL DUV EL EUV FEM FIB IC ISO ITRS LER MEEF MOSFET Alternating Phase Shift Mask Attenuated Phase Shift Mask Anti-reflecting coating Critical Dimension Complementary Metal Oxide Semiconductor Chrome on Glass Chromeless Phase Lithography Design for Manufacturability Develop Inspection Critical Dimension Design of Experimental Depth of Focus Double Patterning Lithography Deep Ultraviolet Exposure latitude Extreme Ultraviolet Focus Exposure Matrix Focus Ion Beam Integrated Circuit Isolated feature International Technology Roadmap for Semiconductors Line Edge Roughness Mask Error Enhancement Factor Metal Oxide Semiconductor Field Effect Transistor xiv

17 NA OAI OPC PSM RET SEM SRAF TE TM UV VUV Numerical Aperture Off Axis illumination Optical Proximity Correction Phase Shift Mask Reticle Enhancement Techniques Scanning Electron Microscope Sub Resolution Assist Feature Transverse-electric waves Transverse-magnetic waves Ultraviolet Vacuum Ultraviolet xv

18 Chapter 1 Introduction Device line width is getting narrower with an increase in complexity of integrated circuits. Conventional light sources and Chrome on Glass (CoG) patterning are no longer able to support today s aggressive technology roadmap. Advanced technological improvements become a must in the semiconductor industry. RET are necessary to extend optical lithography. One of the potential candidates which are able to extend optical resolution and process limits (k 1 factor) is CPL. This chapter provides the background and motivation for the study of CPL in optical lithography technology. 1.1 Background Photolithography or optical lithography is a process, which uses light to transfer a designed pattern from a photomask to a photoresist (light-sensitive chemical) on a substrate. This process is used in micro and nano-scale fabrication to selectively remove parts of a thin film or the bulk of a silicon substrate. A series of processes, which include developing, etching, ashing (photoresist removal) and cleaning will then engraves the exposure pattern into the material underneath the photoresist. Photography is also helpful in determine area for implantation. Developed photoresist will allow implantation while 1

19 undeveloped photoresist will be used as hard mask to stop implantation onto the substrate. In modern 45 nm CMOS (complementary metal oxide semiconductor) technology, a wafer will have to go through photolithographic cycle up to 60 times. A photomask or mask is typically transparent fused quartz blanks covered with a pattern defined with an opaque pattern like chrome metal or semi-transparent pattern like MoSi absorbing film. The opaque pattern or semi-transparent pattern will block the light from shinning through the photomask while the holes or opening space will allow light to pass through in a defined pattern and exposure onto a photoresist coating. Electron beam or laser beam is used to define pattern on the photomask. Electron beam is a high-end while laser beam is a low-end photomask writing tool. Photomask can be used in wavelength of 365 nm (UV), 248 nm and 193 nm (DUV). Special photomask has been developed to support wavelength of 157 nm (VUV) and 13.5 nm (EUV). In integrated circuit fabrication, a set of photomasks are needed, each define a specific design level and serve for different purposes. Photolithography stepper or scanner tool is selected for exposure process. Optical lithography has been a dominant patterning process for semiconductor fabrication since 1960, for about 50 years. As of today, optical lithography system has become the highest resolution and most accurate optical imaging systems ever produced. As the complexity of integrated circuits increased, the patterning process evolved from the initial 2

20 methods used in the printing industry to the sophisticated new imaging methods. One way to achieve improvements in resolution is to simply migrate to a shorter wavelength optical lithography system. Unfortunately, a change of wavelength typically requires large capital expense and significant process development efforts. Lithographers are continuously attempting to improve resolution and process window for manufacturing technology and develop new options for the next technology node. One alternative is to take advantages of RET. RET uses existing techniques which is available on the existing optical lithography tool. Several RET has been introduced such as OPC, PSM, OAI and polarization to extend the life time of optical lithography. CPL becomes an important candidate to extend the optical resolution and process limits (k 1 factor) in 45 nm and beyond technologies. CPL offers many added benefits to the lithographer and mask maker in terms of performance, simplicity and cycle time. The designs and verifications are simplified. There is no requirement for alternating phase assignments. Hence, there are no phase conflicts that require resolution as seen with Alternating Phase Shift Mask. Besides, the technology is less sensitive to phase errors. CPL mask is a single mask solution. There is no need for a secondary exposure with an additional mask, thereby improving stepper or scanner throughput relative to Alternating Phase Shift Mask. Compared to Attenuated Phase Shift Mask, CPL has flexibility to optimize the process window through mask data type decomposition into pure phase, zebra and pure chrome type as shown in Fig1. CPL 3

21 can be used in existing lithography system without putting in significant developments effort. Fig. 1.1: Chromeless Phase Lithography (CPL) and layout decomposition. 4

22 1.2 Research Contributions This thesis describes issues associated with the characterization of Chromeless Phase Shift Mask technique for sub-45nm lithography. Several RET are studied. Process window optimization solutions for CPL are introduced and presented. In this course of the research, I have studied theoretical background of CPL. I have learnt and performed several simulations studies on CPL with commercial lithography software (Lithocruiser, CPLBuilder and Maskweaver of ASML, Calibre Workbench of Mentor Graphic and SOLID-E of Synopsis). The simulation is based on a resist model, which is highly dependent on the properties of the wafer resist and bottom anti-reflective coating. I have developed a tapeout flow for CPL mask which is useful for mass production. Several types of test pattern are designed by myself with commercial software (IC Graph software from Mentor Graphic), which include linearity, through pitch, SRAM and logic test cells. I also setup and optimize the rule of OPC, the placement rule of SRAF and the algorithm of layout decomposition in order to enhance the printing resolution and process window. A 193 nm CPL mask is fabricated to carry out the experimental work. I have done collaboration work with DNP maskhouse to optimize and freeze the CPL mask fabrication process. I have examined CPL lithographic performance through 5

23 experimental works. The experimental works include wafer printing with optical lithography system, feature measurement with SEM (scanning electron microscope) tool and optical inspection. Experimental and simulations results are compared and presented. Several process window optimization methods are introduced and discussed. I have studied the 3D mask effect of CPL mask. I have investigated the impact of mask topography on the lithographic performance. 3D mask simulations which include mask intensity and near field effects are performed. I have proposed optimum quartz etch for CPL mask, which are 205 instead of 180. I have proposed phase change specification should be controlled at +/- 1.5 in order to obtain optimum process window. I have investigated the influence of high NA vector on the image formation. I have studied polarization effects in optical lithography and have proved that Azimuthal polarized light source results in better process window compared to unpolarized and radially polarized waves. Besides, I have also investigated impact of immersion lithography on the lithographic performance. The results show that immersion lithography system achieves at least a 60% improvement in DoF compared to dry lithography system. Apart from the work accomplished, I have also published several papers. 6

24 1.3 Outline The dissertation is organized as follows: In Chapter 2, the evolution of integrated circuit and lithography tool are reviewed. Several Resolution Enhancement Techniques (RET) to extend optical lithography are introduced. In Chapter 3, the theory of optical lithography (Rayleigh criterion) is introduced. CPL mask transmittance and diffraction orders are discussed. In Chapter 4, several commercial lithography softwares: Lithocruiser, CPLBuilder and Maskweaver of ASML and SOLID-E of Synopsys are introduced. Procedures of lithography simulation approaches are presented. Layout decomposition into pure phase, chrome and zebra type, Optical Proximity Correction (OPC) and 3D mask simulation setup are discussed. In Chapter 5, experimental works are presented. Several flows on CPL mask tapeout, mask fabrication process and wafer printing are introduced. Design of experiments (DOE) that have been carried out to study CPL mask lithographic performance: resolution limit and process window are presented. 7

25 In Chapter 6, several areas of CPL process window optimization are presented. Data handling optimization, illumination optimization, 3D mask effect and high NA vector effect are studied. Simulation and experimental results are presented. In Chapter 7, the thesis concludes with a summary of the most important results, recommendation and provide outlook or ideas for future research which is worthy for world of lithography. 8

26 Chapter 2 Literature Review This chapter reviews the evolution of integrated circuit and lithography tools. Several RET to extend optical lithography are introduced. RET that derived from four basic properties of a wave: wavelength, amplitude, phase and direction can be categorized into OPC, PSM, OAI and polarization illumination. The theory of optical lithography (Rayleigh criterion) and CPL are then discussed. 2.1 Development of integrated circuit The first PN junction was introduced by Russel Ohl at Bell Labs in The PN junction can produce 0.5 volts when exposed to light. With the invention of PN junction, it creates a stage for integrated circuit. In 1950s, more inventions of integrated circuit are published and discussed [1-6]. The first MOSFET (metal oxide semiconductor fieldeffect transistor) was fabricated by Kahng at Bell Labs in 1960 [5] [7]. At the same time, the first silicon wafer with inch was introduced [8]. The first commercial IC (integrated circuit) was introduced by both Fairchild and Texas Instrucments. In 1963, Frank Wanlass from Fairchild Semiconductor published an idea of Complementary-MOS (CMOS) [9]. On 5th Dec 1967, Wanlass was issued U.S. Patent # 3,356,858 for "Low 9

27 Stand-By Power Complementary Field Effect Circuitry". CMOS forms the basis of the vast majority of all high density ICs manufactured today. In 1965, Gordon Moore, director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled "Cramming more components onto integrated circuits" [10]. In the paper, Moore observed that "The complexity for minimum component cost has increased at a rate of roughly a factor of two per year". With this publication, the observation became a well known Moore s law (the number of components per IC doubles every 18 months) and the law still holds till today. The first microprocessor was invented and in production in The microprocessor was named 4004 by Intel [11-13]. It was a 10 um technology device. In 1974 Intel introduced the 8080 chip, the first commercially successful microprocessor which was used in Altair Computer [14] chip used 1 polysilicon layer and 1 metal layer. It has 6,000 transistors and is a 6 um technology device. From 1970s till 2000s, microprocessor technology evolves rapidly from 10 um technology to 45 nm technology. Historically, silicon wafer sizes have changed every 10 to 12 years. Silicon wafer size range from the first inch in 1960 to the last being 300 mm in The ITRS (International Technology Roadmap for Semiconductors) projects the next silicon wafer size change in Increasing in silicon wafer size will be able to support the global 10

28 demand and it is proven to be cost effective with taking into consideration on technology node. Researchers are still looking into advantages to have 450 mm silicon wafer in future. With the increasing in silicon wafer size and global demand, evolution of lithography tool becomes critical. 2.2 The evolution of lithography tool Optical lithography has been used in patterning process for semiconductor fabrication since Optical lithography comprises four basic elements: an illumination system, a photomask, an exposure system and a wafer. Patterns on the photomask are replicated by the exposure system onto the photoresist-coated wafer. As the complexity of integrated circuits increased and the device line width decreased, patterning process has to evolve from the initial simple printing process to the sophisticated imaging methods. The evolution of lithography tool has a few trends: separation between the photomask and wafer is increasing, the area of exposure is generally decreasing, the bandwidth of illumination light is narrower and the dimension control requirements become more stringent Contact printing and proximity printing: In mid 1960 s, when the device dimensions were about 5um, process for transferring patterns onto the wafer was dominated by contact printing. Contact printing, as illustrated 11

29 in Fig. 2.1 (a) is a form of photolithography whereby the image to be printed is obtained by illumination of a photomask in direct contact with a substrate coated with an imaging photoresist layer. The photomask has to be the same size as wafer or substrate. Light with a wavelength of about 400 nm is used in contact printing. In this technique, photomask must be thin and flexible to allow better contact over the whole wafer and to achieve uniformity of attainable resolution across the wafer. Contact printing was constrained by practical difficulties of the continuous shrink in circuit dimension. Besides, contact printing also results in defects in both the photomasks and wafers used. Mask defects such as pinholes, scratches, intrusions and star fractures will be reproduced in subsequent exposures. Regular disposal of photomasks is needed after a certain level of use. Technical difficulties in contact printing on the inevitable transfer of defects from the photomask to wafer or wafer to mask have led to the introduction of proximity printing, in which the photomask was placed with a gap of 10 um top 25 um from the wafer surface, as shown in Fig. 2.1 (b). With this technique, photomask have longer useful lives compared to those used in contact printing. The tradeoff encountered with the gap between the photomask and wafer surface is the reduction of resolution. When light passes through slits on a photomask, diffraction of light occurs and reduces printing resolution. This type of diffraction is known as Fresnel diffraction, or near-field diffraction as it results from a small gap between the photomask and the wafer. 12

30 Fig. 2.1: Schematics of (a) contact printing and (b) proximity printing [15] Projection Printing: The limitation of resolution on proximity printing led to the introduction of projection printing in the mid-1970s. Projection printing also involves no contact between the photomask and the wafer. Projection printing requires objective lens between the photomask and the wafer. The objective lens will collects diffracted light from the photomask and project it onto the wafer. This technique employs much larger gap between the photomask and the wafer compared to proximity printing. Fresnel diffraction or near-field effect is no longer involved. Instead, Fraunhofer diffraction or far-field effect is applied under this technique. The early projection printing systems were designed for full-wafer exposure without demagnification (1:1), as shown in Fig. 2.2 (a). With increasing wafer size from 2.25 inch 13

31 (1970), 3 inch (1973), 4 inch (1975), 5 inch (1979) and 6 inch (1981) [16] projection printing without demagnification has reached its limitations. It is because photomasks need to grow in size to match the larger wafers. This trend continues until wafers reached 6 inch in diameter and the photomasks size is 6 inch x 6 inch. Lithographers find difficulties to image all features onto a wafer simultaneously. The image field has to be partitioned and to have more than a single mask exposure onto the wafer. Scanning projection printing, as shown in Fig. 2.2 (b) becomes one of the first partitioning approaches. The photomask is projected onto the wafer by scanning a ringshaped image field. This technique improves the imaging capability to print all features onto a wafer simultaneously. However, this technique does not solve the difficulties dealing with the continuous increase in wafer size and reduction on feature dimension. Reduction projection printing is needed. This technique, as illustrated in Fig. 2.2 (c), step and repeat (stepper) and Fig. 2.2 (d), step and scan (scanner) require addition wafer alignment step but eliminate making of 1:1 masks. Scanner imaging system has better printing accuracy and resolution compared to stepper imaging system. 14

32 Fig. 2.2: Schematics of various types of projection system In 1978, photolithography step and repeat system (stepper), the GCA 4800 DSW, as shown in Fig. 2.3 was invented by GCA (Geophysical Corporation of America) to increase the printing resolution and enabling line width shrinks. The reduction lens made 15

33 by Carl Zeiss, has a 10:1 reduction ratio with a numerical aperture of 0.28 and field size of 10 mm x 10 mm. Exposure wavelength that was used is g-line (436 nm) from a highpressure mercury lamp. Fig. 2.3: GCA 4800 DSW 10:1 Reduction Stepper In 1980, the first commercial photography step and repeat system (stepper), NSR-1010G was introduced in Japan by Nikon. The stepper technology was copied from GCA [17]. The exposure wavelength of the tool was still g-line (486 nm). In 1982, first stepper was shipped to USA. Nikon surpasses GCA in total units of stepper shipped and sales revenue in The first Nikon s i-line (365 nm) stepper, NSR-1010i3 and first KrF (248 nm) stepper, NSR-1505EX were shipped on 1984 and 1988 respectively. ASML, a European 16

34 photolithography system manufacturer commercializes the first stepper PAS 2000/10 g- line (486 nm) in The technology was spinning out from Philips. ASML s stepper has better alignment performance compared to Nikon s stepper. The first ASML s i-line (365 nm), PAS 2500/40 and KrF (248 nm), PAS 5000/70 stepper were shipped in 1987 and 1991 respectively. Photolithography productivity increases when the stepper image size increases due to fewer exposures per wafer. Higher resolution means more circuits per wafer. Reduction ratios are reduced as the chip size requirements grow in order to accommodate larger chips and more chips on the same photomask to be imaged onto the wafer. Reduction ratios have been reduced from the very beginning 10:1 from GCA s tool to 5:1 and then 4:1 on Nikon and ASML photolithography tool. Stepper technology hit its limitation with the continuous increase in chip size and more stringent dimension control requirements. New technology was then introduced which is step and scan projection lithography system. The photomask is scanned rather than exposed all at once. Repeated stepping and scanning exposes an entire wafer. Scanner tool is able to increase image field coverage without increasing the natural field size of the lens. In 1995, Nikon shipped the first step and scan (scanner) KrF (248 nm) tool, NSR-S201A. Scanner performance is much better compared to stepper as it can reduce the iso-dense bias. Other than that, uniformity is improved. ASML and Nikon shipped their first ArF (193 nm) scanner PAS 5500/500 and NSR-S302A in 1997 and

35 respectively. In 2000, ASML introduced the TWINSCAN product platform, using two wafer stages to increase throughput. ASML surpassed NIKON and become the world number one photolithography tool supplier in High NA and immersion photolithography: 2003 present Lithographers face an even greater challenge keeping up with Moore s Law in early Both 157 nm and 193 nm wavelength were being developed along with other optical and non-optical approaches and it seems no obvious solution to meet the long term need [18]. In 2003, 157 nm has been announced as impractical road map for optical lithography after 193 nm due to the stringent control on scanner environment and photomask or pellicle requirements. Researchers continue to put enormous effort or investment to support advanced optical lithography due to its tremendous staying power. Besides improvements with shorter wavelength and bigger numerical aperture, further resolution solution have been explored with the introducing of DFM (Design for Manufacturability), material improvements and RET, which include PSM, OPC, and customized illumination that allow systems to operate at smaller values of k 1. In 2003, wafer-immersion lithography, as shown in Fig. 2.4 at 193 nm was commercialized after solving the design problem with the lens. Wafer-immersion lithography in principle will allow the NA to rise to nearly 1.4 [19-22]. ASML and Nikon shipped their first ArF (193 nm) wafer-immersion lithography scanner AT:1250i and NSR-S609B in 2003 and 2006 respectively. 18

36 Fig. 2.4: Schematic diagram of wafer-immersion lithography tool 2.3 Extending optical lithography with Resolution Enhancement Technique (RET) Lithographers did predict optical lithography will be dead when the feature size of integrated circuit reaches about 1 um. However, the prediction is not true since optical lithography is still being used for 32 nm technology. In 2006, IBM scientist claimed that they are able to print 32 nm design rule features with 193 nm optical lithography together with RET and high index liquid immersion system. The resolution of optical lithography is basically limited by the wavelength of exposure system. However, by employing RET, the minimum feature size that can be printed on wafer can be further reduced to about 20% smaller than the wavelength of exposure system. RET play an important role in 19

37 extending optical lithography, which include OPC, PSM, OAI and polarization illumination. RET are derived from four basic properties of a wave: wavelength, amplitude, phase and direction. In optical lithography, wavelength is set by the exposure system. OPC is to control amplitude by changing the mask transmissions and polygon shapes, PSM is to control phase of the wave while OAI and polarization illumination will be able to control the propagating of the wave by changing the direction of how light is directed on a photomask [23-27] Optical Proximity Correction (OPC) OPC is used to optimize the aerial image formed by a projection lens and to compensate image error due to diffraction or process effects. In this technique, an OPC simulation program is used to simulate a 2D aerial image from a photomask pattern considering the illumination condition and recipe model. Based on a simulated aerial image, the photomask pattern will be manipulated so as to improve pattern fidelity on wafer printing. Three common OPC applications are to resolve line width difference due to pattern density variation, line end shortening and corner rounding. Line width difference due to pattern density variation can be resolved by employing linewidth adjustment based on the proximity effect or with the placement of SRAF or scattering bar adjacent to main features [28]. SRAF can be used to reduce iso-dense bias. SRAF are narrow lines or spaces placed adjacent to a main feature to make a relatively isolated main feature behave lithographically closer to a dense main feature. Line end shortening and corner rounding can be resolved by employing serif or hammerhead features to the line end or cornering 20

38 in the design as these sub-resolution features are able to enhance the light transmitted through line end and corners. OPC application will increase the cost of photomask. Data volume of the photomask layout will increase dramatically with the application of OPC. This increases mask writes cycle time. Photomask supplier will have to use better photomask writing tool to resolve the sub-resolution features on the photomask. Furthermore, photomask supplier will encounter inspection problem as the sub-resolutions features are much smaller than the minimum main features. Figure 2.5 shows an illustration of serifs, hammerhead and SRAF with main feature. Main Feature Hammerhead SRAF Serif Fig. 2.5: Illustration of serifs, hammerhead and SRAF with main feature 21

39 2.3.2 Phase Shift Mask (PSM) PSM utilizes the interference generated by phase differences on the photomask to improve the image resolution in wafer printing. Material and structure optimization are critical to control the phase of the exposure light accurately. Compared to the conventional binary photomask, binary photomask does not utilize phase shift concept. All types of PSM employ the same principle, in which the destructive interference of light of opposite phases is used to improve image contrast [29]. A binary mask, as shown in Fig. 2.6 consists of quartz and chrome features. When light hits the photomask, light will pass through the clear quartz region while block by opaque chrome region. Exposed region on the photoresist (positive resist) will be removed in the developing process and leaving the unexposed region as features on the wafer. As feature sizes and pitches shrink, the resolution of the projection optics begins to limit the quality of the resist image. There is significant energy (and intensity, which is proportional to the square of the energy) even below the opaque chrome areas, due to the very close proximity of the neighboring clear quartz areas. This "unwanted" energy affects the quality of the resist profiles, which are ideally vertical. Therefore phase-shift techniques are designed to "sharpen" the intensity profile, and thus the resist profile, which allows smaller features to be printed. There are several types of phase shift mask that has been used in recent years to extend the limits of optical lithography, which include Att-PSM (Attenuated Phase Shift Mask), Alt-PSM (Alternating Phase Shift Mask) and the latest CPL photomask. 22

40 Att-PSM, as shown in Fig. 2.7 form their patterns through adjacent areas of quartz and, for example, molybdenum silicide (MoSi). Unlike chrome, MoSi allows a small percentage of the light to pass through (typically 6%, 8%, 12% or 18%). However, the thickness of the MoSi is chosen so that the light that does pass through is 180 out of phase with the light that passes through the neighboring clear quartz areas. The light that passes through the MoSi areas is too weak to expose the resist, however the phase delta serves to "push" the intensity down to be "darker" than similar features in chrome. The result is a sharper intensity profile which allows smaller features to be printed on the wafer. The faint aerial image formed by the attenuated features is 180 out of phase and thus "darker' than similar chrome features (as in binary masks). Alt-PSM, as shown in Fig. 2.8 employs alternating areas of chrome and 180 shifted quartz to form features on the wafer. Alt-PSM is a powerful but complex technology. The process of manufacturing the mask is considerably more demanding and expensive than that for binary masks. Furthermore, the Alt-PSM must be accompanied by a second "Trim" mask, resulting in extra cost and decreased stepper throughput. Chrome lines on the reticle are bordered on one side by quartz of phase 0, and on the other side by quartz of phase 180. As the phase goes from positive to negative, it passes through zero phase value. The intensity (proportional to the square of the phase) also goes through zero value, making a very dark and sharp line on the wafer. 23

41 Fig. 2.6: Schematic diagram for a conventional binary mask [29] Fig. 2.7: Schematic diagram for an attenuated phase shift mask (Att-PSM) [29] Fig. 2.8: Schematic diagram for an alternating phase shift mask (Alt-PSM) [29] 24

42 CPL mask, as shown in Fig. 2.9 is a strong phase-shift mask containing chrome, phase, and variable transmission (chrome & phase) features, typically including the use of scattering bars and model-based OPC. CPL imaging techniques include the use of high NA, off axis illumination and design-specific customized illumination that enable low k1 (< 0.35) lithography process for the 90 nm, 65 nm, 45 nm and below technology nodes. CPL creates a high contrast wafer images with the combination of two neighboring π- phase edges. The phase shift region is created by etching the substrate of quartz to certain depth, which is dependent on the wavelength of the lithography system. There are two types of CPL: pure phase and zebra type for critical line dimensions. Both types of CPL masks require chrome pads to be added in the circuit line junction region to enhance the contrast and resolution. Compared to Att-PSM, CPL has better flexibility on process window tuning by optimizing the chrome shielding. CPL is a single mask, single exposure and much easier to handle in terms of data handling as compared to Alt-PSM. Unlike the Alt-PSM, CPL does not require complicated phase coloring, restricted design rule and double exposure. With the combination of customized off axis and polarized illumination, strong phase shift mask (CPL PSM), OPC and high NA lens, CPL enables fabrication of devices for advanced technology nodes [30-40]. 25

43 Fig. 2.9: Schematic diagram for a chromeless phase lithography (CPL) mask 26

44 2.3.3 Off Axis Illumination (OAI) There are two types of illumination system: on axis and off axis illuminations. In on-axis illumination, the larger the partial coherence factor, the higher the resolvable spatial frequency. However, using large partial coherence factor to print dense patterns is not optimal as it increases the DC background rather than contributing to image contrast or image formation [15]. As illustrated in Fig. 2.10, three point sources: 0 th, 1 st and -1 st orders are represented by the shaded region. The DC background, which will degrade the image contrast, is contributed by the shaded but un-hashed area. -1 st order 0 th order 1 st order DC only Contribute to contrast Fig. 2.10: Three point sources: 0 th order, 1 st order and -1 st order 27

45 Off axis and customized source illuminations have become popular as they are able to improve printing resolution and increase the DoF for dense pitch patterns without having a higher-na lens or shorter wavelength of lithography system. The amount of DC background can be reduced with off axis illumination. The resolution is enhanced by modifying the direction of incidence of the illumination on the photomask. Compared to on-axis illumination, off axis illumination directs the beam of light through the photomask in a direction that makes it strike the projection-lens at the edge of the entrance pupil rater than the center of entrance pupil. Diffraction angle increases when pitch of pattern decreases. Printing resolution with both on-axis illumination and off axis illumination are comparable when the diffraction angle is small, as shown in Fig (a) and (b). However, when the diffraction angle is big, as shown in Fig (a) and (b), entrance pupil in on-axis illumination system will not be able to capture the 1 st orders of light. Pattern on wafer will be unresolved. Compared to off axis illumination, entrance pupil in off axis illumination system is still able to capture 1 st order and 0 th order light. Hence, off axis illumination demonstrates advantages in dense pattern resolution enhancement. One of the limitations of off axis illumination is that it does not give the same resolution enhancement for both isolated and dense patterns. Compensation for loss of illumination is necessary. There are two methods for off axis illumination: by blocking the light path (hard-stop aperture) or DOE (diffractive optical element). A DOE is preferred compared to a hardstop aperture as a DOE is able to preserve the energy from the light source to the mask and reduce throughput loss. Furthermore, several types of complex source shapes can be 28

46 created with a smooth distribution of light across the aperture. It makes the implementation of off axis illumination easily as lithography manufacturers can provide any of the illumination aperture types as requested by lithographer. Some common off axis illumination configurations are shown in Fig Most of the commercial simulation tools use pixel-based representation, which is able to handle continuously distributed light sources. The total energy falling onto a mask can be described as [41]: E = A S( x, y) dxdy (2.1) where S is the source function and A is the source area. The throughput of a wafer printing process is dependent on this energy. 29

47 +1 st 0 th -1 st Best focus Out of focus Fig. 2.11: (a) Schematic of on axis illumination (small diffraction angle / big slit) +1 st 0 th -1 st Best focus Out of focus Fig. 2.11: (b) Schematic of off axis illumination (small diffraction angle / big slit) 30

48 +1 st 0 th -1 st Pattern unresolved Fig. 2.12: (a) Schematic of on axis illumination (big diffraction angle / small slit) +1 st 0 th -1 st Best focus Out of focus Fig. 2.12: (b) Schematic of off axis illumination (big diffraction angle / small slit) 31

49 Fig. 2.13: Common off axis illumination configuration (a) quadrupole, (b) dipole (c) annular Polarization effects in optical lithography In describing polarization, the electric field vector is included while the magnetic field is ignored. The electric field vector consists of two components, namely the TM (transverse-magnetic) and TE (transverse-electric) waves. The TM wave is expressed as a p-like electric field while the TE wave is expressed as an s-like electric field. As illustrated in Fig. 2.14, polarization plays an important role in optical lithography as it affects the contrast of a printed wafer image. In a low NA optical system, the effect of TM is not significant. However, in a high NA optical system, the TM component can degrade the image contrast which is expressed as (Imax-Imin) / (Imax + Imin) or (I TE - I TM ) / (I TE + I TM ). As shown in Fig. 2.15, polarization can be classified into homogeneous 32

50 and inhomogeneous types. The Y Linear and X Linear are homogeneous type, used for a single directional design pattern. Azimuthal (TE) and Radial (TM) are inhomogeneous type used for a 2D complex pattern [42-44]. Fig. 2.14: Polarization effects on low NA and high NA lens 33

51 X Linear Y Linear (a) Azimuthal (TE) Radial (TM) (b) Fig. 2.15: Source Polarization (a) homogeneous (b) inhomogeneous 34

52 Chapter 3 Theoretical Analysis This chapter reviews the theory of optical lithography (Rayleigh criterion and extension), and CPL mask transmittance and diffraction orders. 3.1 Rayleigh criterion and the extension Device line width is getting narrower with an increase in complexity of integrated circuits. Conventional light sources and CoG (chrome on glass) patterning are no longer able to resolve the small feature on wafer printing. Advanced technological improvements become a must in the semiconductor industry. Contact printing which was introduced in 1960s defines the theoretical resolution as [15]: Resolution, 3 λz R = (3.1) 2 2 where λ is the exposure wavelength, and z is the photoresist thickness. 35

53 Proximity printing was then introduced. Proximity printing creates a gap between the photomask and the wafer surface to prolong the life time of the photomask. Proximity printing resolution can be improved by reducing the gap between the photomask and the wafer or introducing shorter wavelength of exposure light. The theoretical resolution of proximity printing is [15] Resolution, R = 3 λ ( g + z ) (3.2) 2 2 where g is the distance between the photomask and the resist surface. Projection printing was introduced in the mid-1970s to improve the resolution. Resolution of projection printing depends on the exposure wavelength, coherence of the incident light and the numerical aperture, NA of the lens. The achievable resolution is governed by Rayleigh s criterion. Rayleigh s equation defines half-pitch resolution as Resolution, λ R = k1 (3.3) NA λ Depth of Focus, DoF = k (3.4) 2 2 NA where λ denotes illumination wavelength and NA denotes numerical aperture of the lens. k 1 and k 2 are proportionality constants that can be defined as degree of process difficulty. Both k 1 and k 2 depend on the specific resist material, process technology and image formation technique. From Rayleigh s equations, resolution of the image can be 36

54 enhanced with a higher NA and shorter exposure wavelength but it will reduce depth of focus (DoF). DoF of a lens is inversely proportional to the square of the numerical aperture or NA. Limited DoF will cause some points of the wafer to be out of focus and not able to achieve required CD target on wafer due to imperfect wafer surface flatness. As a result, lithographer has to consider the compromise between resolution and DoF dealing with projection lithography. The numerical aperture NA of a lens is defined as NA = nsinθ (3.5) where n is the refractive index of the medium surrounding the lens and θ, as shown in Fig. 3.1 is the highest diffracted angle that can be captured by the lens [45]. Based on Rayleigh s equations, two methods to improve the resolution limit are to apply shorter wavelength of exposure light source or incorporate higher numerical aperture of projection lens in the lithography system. However, these methods result in the loss of DoF. As shown in Fig. 3.2, higher NA will reduce DoF. Several methods have been proposed by lithographer to allow operation of manufacturable lithography processes at lower k 1 factors, which include introduction of RET, shorter wavelength and the recent immersion lithography technology. 37

55 Condenser lens reticle v Entrance pupil Exit pupil wafer Light source v v v v θ v v Illumination system Projection system Fig. 3.1: Imaging in Optical Lithography Exit pupil Exit pupil High NA Low N.A. Wafer Wafer DOF DOF Fig. 3.2: Effect of varying NA on Depth of Focus (DoF) 38

56 In 2003, F 2 lithography using 157 nm exposure light source was removed from the optical lithography roadmap. Several key problems in F 2 lithography are still insurmountable. The 157 nm pellicle membranes cannot withstand more than 10 exposures; hard pellicle technology is far from manufacture-worthy, ditto for the F 2 resist systems and lens makers are still facing quality and quantity problem with the lens material, CaF 2. Besides, F 2 lithography system requires an oxygen-free and water-vaporfree atmosphere, together with many other complications [46]. Immersion lithography system is better than a system with shorter vacuum wavelength as the development effort on new mask; lens and resist materials are greatly reduce. Immersion lithography uses exposure tools whereby the space between the last elements of the imaging lens and the surface of the photoresist on the wafer is filled with fluid such as water, as shown in Fig With a higher-index medium, light of higher spatial frequencies can be coupled to the resist, hereby improves the resolution. The liquid coupling also minimizes the reflection loss at the two interfaces affected. In dry lithography, light will suffer total internal reflection when the NA reaches its limit. By taking advantage of the refractive index of the liquid, immersion lithography is effective for both resolution enhancement and DoF improvement [47-48]: Resolution (dry), R d λ = k1 (n = 1) (3.6) NA d Resolution (immersion), λ Ri = k1 (n > 1) (3.7) nna i 39

57 Assuming, R = R d i NAd NAi = (3.8) n k2λ Depth of Focus (dry), DoFd = (3.9) 2 NA k2λ Depth of Focus (immersion), DoFi = 2 NA d i k λn 2 = 2 2 (3.10) NA d = n 2 DOF d (n > 1) (3.11) Fig. 3.3 Schematic dry and immersion systems 40

58 3.2 Chromeless Phase Lithography (CPL) mask transmittance and diffraction orders CPL mask is a three beam (-1, 0, +1 diffraction orders) imaging system [49]. CPL mask uses destructive interference between light transmitted through 0 and 180 regions to form dark images on wafer printing. Aerial image intensity determined by primary diffraction orders is controlled by mask feature transmittance value. For coherent illumination, the intensity transmittance function T(x) is related to the complex amplitude transmittance function t(x) for the electric field and can be expressed as [49][50]: t( x) = T ( x).exp( jφ( x)) (3.12) where φ(x) denotes phase shift introduced by the shifter for Att-PSM or quartz depth for strong phase shift mask which include CPL. Considering an infinite grating on a clear field mask with a line width, w, line space, s, pitch, p, the mask transmittance, m(x) can then be expressed as p x 1 x x 1 ( ) ( ) ( ) ( 2 x m x = rect comb T rect ) comb( ), p = s + w (3.13) p s p p s p From Fourier optics, the electric field transmitted by the mask forms a distribution in the pupil plane, which is proportional to the mask spectrum. The field for a point source is given by the following equations: E (x) = F [ P( f ) F( t( x))] x (3.14) 41

59 I(x) = E ( x) E * ( x) (3.15) where, t(x) is the mask transmittance function and F(t(x)) is the mask spectrum that directly contributes to the electric field. F is the Fourier transform operator, F is the inverse transform operator, P is the pupil function, f x is the pupil frequency coordinate, E is the electric field, and I is the intensity at the image plane. Fourier transform of Eq. (3.13) can then be expressed as 1 sin( πk xs) sin( πk xw) n F{ m( x)} = {[( s )] [ b * exp( πjk x p)]}* δ ( k x ) p πk S πk w p x x (3.16) where p sin( θ ) = nλ, k = sin(θ ) x The 0 th order and ±1 st order amplitude can be calculated using the following equations: for 0 th order: 1 1 F 0 ( k x ) = ( s w T ) = [ p w(1 + p p T )] (3.17) for ±1 st order: 1 F 1 ( k x ) [sin( πs w ) T sin( π 1 πw = + )] = sin( )(1 + T ) π p p π p (3.18) Eq. (3.17) indicates that the 0 th order amplitude decreases as the mask intensity transmittance increases. Eq. (3.18) indicates that the ±1 st order amplitude increases as the mask intensity transmittance increases. Eq. (3.17) and Eq. (3.18) can be further simplified for pure phase and zebra type with 50% transmittance. 42

60 For CPL with pure phase type, the 0 th and ±1 st order amplitude can be expressed as 0 th 1 order, F 0 = [ p 2w] (3.19) p ±1 st 2 πw order, F 1 = sin( ) (3.20) π p For CPL with zebra type (50% transmittance), the 0 th order and ±1 st order amplitude can be expressed as 0 th 1 order, F 0 = [ p w(1.707)] p (3.21) ±1 st πw order, F 1 = sin( ) π p (3.22) For CPL with pure phase type (100% transmittance), 0 th order component is not present when 1:1 line to space ratio is used or when p = 2w, as discussed in Eq. (3.19). The lens pupil receives only ±1 st order light as the 0 th order light is cancelled and no images are formed on the image plane. 43

61 Chapter 4 Simulation Work Lithography simulation approaches are presented in this chapter. Several commercial lithography softwares: Lithocruiser, CPLBuilder and Maskweaver of ASML and SOLID- E of Synopsys are introduced. Layout decomposition into pure phase, chrome and zebra type, OPC, placement of SRAF and 3D mask simulation setup are discussed. 4.1 Simulation models Two phases of simulation are carried out. The first phase is based on mathematical calculation which considers the 0 th and ±1 st orders amplitude as mentioned in Chapter 3. The second phase of the simulation is based on a resist model, which is highly dependent on the properties of the wafer resist and bottom anti-reflective coating. Typically, the electromagnetic wave transmitted through a thin film (wafer resist in this case) can be expressed as [23]: E = Aexp( iφ) (4.1) 2πn ~ d φ λ 44

62 where E denotes the electromagnetic wave, A is the wave amplitude, i is a complex number, φ is the phase change, d is the resist thickness and λ is the wavelength of the lithography system. n ~ is the complex reflection index that can be expressed as: n ~ = n ik (4.2) where n denotes the real index of refraction, which influences the phase while k denotes the extinction coefficient which influences the transmittance. Both n and k are critical in a resist model based simulation which predicts the mask performance on wafer printing. Substituting the Eq. (4.2) into Eq. (4.1), the electromagnetic wave can be expressed as: E = 2πd 2πd Aexp( i n)exp( d) λ λ (4.3) The intensity in the resist can be expressed as I( x) = E( x) E ( x) (4.4) CPL mask simulations are performed with several commercial lithography softwares: Lithocruiser, CPLBuilder and Maskweaver softwares of ASML and SOLID-E software of Synopsys. 45

63 4.2 Lithocruiser Lithocruiser simulation software of ASML, as shown in Fig. 4.1 can be used to develop new lithography processes and optimize existing processes at the design, photomask and imaging levels. Lithocruiser can take in all lithography parameters such as numerical aperture, illumination types, wavelength and resist parameters. Lithocruiser simulates, analyzes and optimizes the ASML scanner performance and mask design simultaneously. Many functions can be carried out with Lithocruiser such as pupil, OPC, NA, source optimization and process analyzer. Lithocruiser consists of 7 pages and 4 modules. Page 1: Numerical Setting - to have general image, grid and FEM settings. Page 2: Machine - to select machine type, magnification and wavelength. Page 3: Reticle Design - to create test pattern to be studied and evaluate. Page 4: Resist - to define resist and ARC (anti-reflective coating) parameters. Page 5: Exposure - to define exposure condition and illumination types. Page 6: Rule OPC - to create simple rule based OPC (Optical proximity correction) on main features. 46

64 Page 7: Metrology - to define features to be measured and analyzed. The 4 modules are Analysis, Optimization, Simulations and Viewer modules. Fig. 4.1: Graphic User Interface (GUI) of Lithocruiser of ASML 47

65 4.3 CPL Builder CPL Builder of ASML is a commercial mask design tool for CPL mask development with GUI (Graphic User Interface), as shown in Fig Fig. 4.2: Graphic User Interface (GUI) of CPL Builder of ASML 48

66 CPL Builder consists of 4 pages: Page 1: Input/Output - to set gds input and output information Page 2: Model Setup - to set parameters for illuminators, exposure, and SRAF rule file Page 3: Zone Det - to decompose original layout into 3 zone: pure phase, zebra and pure chrome types Page 4: Model OPC - to define snippet and model based OPC options CPL Builder can take parameters from all the pages and output the data in target layer (original data), mesa layer (pure phase layer), chrome layer, 1 st write layer, 2 nd write layer, and contour layer. Mesa layer (pure phase layer) and chrome layer are needed for lithographer to review the layout after decomposition. These layers, which represent physical data (chrome, quartz or etched quartz) on the photomask, will be used in mask inspection process. 1 st write layer and 2 nd write layer are needed for mask writing process. 1 st write layer is to define geometry on the photomask while 2 nd write layer is to remove the chrome layer on the photomask. Contour layer is to allow lithographer to review the aerial image or latent image based on calibrated optical model or resist model. Figure 4.3 shows a sample of original data, mesa layer, chrome layer and contour layer. CPL Builder will allow multi threads CPU running in order to speed up the data generation. The minimum resolution of output grid size is 0.1 nm. 49

67 a) Original Data Phase Layer Pure Chrome Pure Chrome b) Mesa Layer (Phase Layer) and Chrome Layer output from CPL Builder c) Contour image (Intensity plot) Fig. 4.3: Illustration of original data, mesa, chrome and simulated contour layers 50

68 4.4 Maskweaver Empirical Model Optical Proximity Correction Maskweaver of ASML provides a full-chip, hierarchical, model-based OPC capability with native implementation of ASML s patented CPL Builder. It helps lithographer to address the low k 1 imaging requirements by giving precise OPC model, which is calibrated to actual wafer results. Maskweaver Empirical Model Optical Proximity Correction is able to model all pitches. Model calibration is made directly from SEM photos, as shown in Fig. 4.4 which account for the localized proximity effect for both line-end and line width. Maskweaver Empirical Model Optical Proximity Correction will take numerical aperture and illumination setting into consideration. Isolated, semi-dense and dense features can be calibrated under the same OPC model. Figure 4.5 shows Maskweaver Empirical Model Optical Proximity Correction calibration steps to apply model-based OPC on an actual device (full chip solution) for mask making. A good model-based OPC calibration engine requires: - ease of calibration - able to handle different types of complex 2D patterns - high precision and is able to predict the process behavior 51

69 - capability to perform calibration for SRAF (Sub-resolution Assist Feature) SPIF (System Pseudo-Intensity Function) is an Optical Proximity Correction (OPC) model developed from ASML for Chromeless Phase Lithography (CPL). n = α i M ( x, y) * ψ i ( x, 2 ) (4.5) i= 1 SPIF( x, y) y where αi is a weighting coefficient to be calibrated and optimized M ( x, y) is the mask transmission function ψ ( x, y) is the set of basis functions that have been chosen to represent optical imaging i system such as Eigen functions of an optical system (a) Dense Main Features (b) Isolated Main Features Fig. 4.4: Sample of Scanning Electron Microscope (SEM) images 52

70 Step 1: Define critical patterns for model calibration Step 2: Provide three inputs to Maskweaver OPC engine (for the 1st calibration only) Input 1: SEM photos of resist patterns (70kx or higher magnification, same magnification for all photos) SEM CD data for calibration Input 2: Original Gds data (no OPC) that is corresponding to the resist SEM photos Input 3: Process parameters for resist patterns: NA, illumination types, exposure dose, resist thickness and substrate. Step 3: Perform Empirical Model Calibration Step 4: Output Empirical Model (SPIF Kernel) parameters Step 5: Verify the calibration performance on non-calibrated resist pattern Step 6: Apply model OPC on the actual device data to make reticle Fig. 4.5: Maskweaver empirical model OPC calibrations steps 53

71 4.5 SOLID E SOLID E of Synopsys models all of the processes and techniques involved in optical microlithography. It can simulate the evolution of three-dimensional topographic features in integrated circuit devices throughout the various phases of the microlithography process. Due to its sound physical approach, SOLID E has a high predictive power, enabling lithography engineers to draw on simulation results to develop and optimize process technologies. SOLID E sets a new standard in lithography simulation, addressing the challenges found in current and future process technology nodes. It provides a powerful analysis tool to simulate rigorously the outcome associated with the most advanced RET including immersion lithography, effects due to mask and wafer topography, and their impact on the resulting photoresist profile. As shown in Fig. 4.6, all features of SOLID E are embedded in an intuitive GUI, which allows lithographers to navigate easily through a wide range of lithography simulation capabilities. SOLID E simulator consists of 5 pages: Page 1: Exposure Tool - to set parameters for illuminators and exposure conditions Page 2: Mask - to define the size of main feature and the types of feature such as chrome, 0 phase, 180 phase or shifter. 54

72 Page 3: Stack - to define stack scheme and thickness on the mask such as quartz, chrome or shifter. Page 4: Resist & ARCs - to define stack scheme and thickness on the wafer such as silicon substrate, type of resist and type of ARC (antireflective coating). Page 5: Metrology - to define features to be measured and analyzed. Fig. 4.6: Graphic User Interface (GUI) of Solid E simulator 55

73 Figure 4.7 shows sample of parameters setting on illuminators and exposure conditions. Information on stepper or scanner types, exposure wavelength, numerical aperture, and illumination types are needed to carry out the simulation study. Inner radius and outer radius are relative values and without unit. These values control total amount of light passing through the lens. Figure Fig show the 2D and 3D mask view generated by SOLID E after taking consideration of features dimension, distance between the features, types (pure phase and zebra) and stack scheme (quartz and chrome thickness). The effect of SRAF placement on isolated features is studied. The 2D and 3D mask setup are to study near field 3D mask effects on different conditions of CPL mask. The advantages and disadvantages of the different CPL masks designs are studied. All simulation results are included in Chapter 6. 56

74 Exposure settings: Stepper convention: ASML Wavelength: ArF (193 nm) Magnification: 4X Numerical Aperture: 0.85 a) Annular b) Quasar Inner radius: 0.68 Inner radius: 0.68 Outer radius: 0.92 Outer radius: 0.92 Angle: 30 Segments: 4 Rotation angle: 45 Fig. 4.7: Solid E parameters setting on illuminators and exposure conditions 57

75 H W 1000 nm Fig. 4.8: 2D and 3D view of CPL mask: Isolated pure phase feature H W SB W SB W W SB W SB 1000 nm Fig. 4.9: 2D and 3D view of CPL mask: Isolated pure phase feature with SRAF 58

76 W Cr H Cr P Cr H W 1000 nm Fig. 4.10: 2D and 3D view of CPL mask: Isolated zebra feature W SB W SB W SB W Cr H Cr W SB P Cr H 1000 nm W Fig. 4.11: 2D and 3D view of CPL mask: Isolated zebra feature with SRAF 59

77 H W P Fig. 4.12: 2D and 3D view of CPL mask: Dense pure phase feature H P Cr H Cr W Cr W P Fig. 4.13: 2D and 3D view of CPL mask: Dense zebra feature 60

78 Chapter 5 Experimental Work This chapter presents the experimental work that has been carried out to study CPL mask lithographic performance. The experimental work begins with CPL mask tapeout, proposed mask fabrication processes and finally wafer printing with lithography tool. 5.1 Chromeless Phase Lithography (CPL) mask tapeout A 193 nm CPL mask is built to carry out the experimental work. Figure 5.1 shows a CPL mask tapeout flow from test pattern generation to mask delivery. Several types of test patterns are drawn with commercial software (IC Graph software of Mentor Graphic), which include linearity, through pitch, SRAM and logic test cells. These test patterns are duplicated to generate different mask types, which include pure phase, zebra and pure chrome type. The test patterns are split with and without Optical OPC. Test patterns with OPC are generated through layout decomposition using CPL Builder software and data preparation process with Maskweaver software of ASML, which is dependent on feature size and proximity effect. To improve the DoF of isolated feature, chrome scattering bar or SRAF are placed adjacent to the main feature. SRAF placement is accomplished using Maskweaver software of ASML. 61

79 Test pattern generation using IC Graph Gds data format conversion Mask layout decomposition using CPL Builder Data prep, OPC generation and SRAF placement using Maskweaver Layout assembly using Calibre Workbench Data tapeout to mask house Mebes data fracturing Mebes jobview and release for mask writing process CPL mask delivery from mask house to end user Fig. 5.1: Chromeless Phase Lithography (CPL) mask tapeout flow 62

80 a) Original Data Pure Phase Pure Chrome SRAF (Chrome) Zebra b) CPL layout decomposition, data prep and SRAF placement Fig. 5.2: Layout decomposition of original data to different mask types with SRAF 63

81 Figure 5.2 shows the layout decomposition of original data to different mask types with SRAF. The final layout assembly and chips placement are carried out with Calibre Workbench software of Mentor Graphic. The output gds data (processed data) is then transferred to mask house for fracturing process and conversion into mebes data format. Five layers of data which are sent to mask house to build the CPL mask are described below: 1 st layer: original data, as shown in Fig. 5.2 (a) 2 nd and 3 rd layers: phase and chrome data, as shown in Fig. 5.2 (b). 2 nd and 3 rd layers are to define chrome area and phase area on the physical mask. The data will be used for mask inspection tool. 4 th and 5 th layers: 1 st and 2 nd mask write data, as shown in Fig. 5.3 (a) and (b). 4 th and 5 th layers are used in mask writing process. 1 st mask write data is to define the geometry on the mask while 2 nd mask write data is to define chrome area and phase area on the mask through exposure, development and etching processes. The digitized area polarity for 1 st mask write layer is dark while 2 nd mask write layer is clear. In other words, the feature on the 1 st mask write data will appear as resist feature on the mask after 1 st mask writing/developing process while the feature on the 2 nd mask write data will appear as resist space on the mask after 2 nd mask writing/developing process. 64

82 a) 1 st mask write data b) 2 nd mask write data Fig. 5.3: Chromeless Phase Lithography (CPL) 1 st and 2 nd mask write data 65

83 The logical operation for these layers can be defined as Phase layer = 1 st mask write layer AND 2 nd mask write layer (5.1) Chrome layer = 1 st mask write layer NOT 2 nd mask write layer (5.2) Data conversion from gds to mebes format is necessary as mask writing and inspection tools are able to recognize data in mebes format only and are not able to read in gds data. Mebes jobview is carried out with K2 viewer software of Synopsis to ensure that data are converted correctly for mask fabrication process. It takes about 20 days to write, measure, inspect and deliver a CPL mask to the end user. Illustration of a CPL mask end product is shown in Fig Quartz (Phase 0 ) Chrome Chrome Etched Quartz (Phase 180 ) Fig. 5.4: Chromeless Phase Lithography (CPL) physical mask data 66

84 5.2 Chromeless Phase Lithography (CPL) mask fabrication process Figure 5.5 shows an illustration of proposed Chromeless Phase Lithography (CPL) mask fabrication flow. The flow starts with the raw material (blank material) and ends with the final product. A raw material consists of three material stacks which include photoresist, chrome and quartz. A 50keV electron-beam mask writing tool is used in 1 st mask writing process (exposure with negative resist) while a laser-writing tool is used in 2 nd mask writing process (exposure with positive resist). Electron-beam mask writing tool has better resolution compared to laser mask writing tool [51-54]. The mask background is etched to achieve 205 phase shift relative to pure phase features. The etch depth required to produce a phase shift ofφ can be calculated based on the equation below [23]: Etch depth, d = λφ 360( n qtz 1) (5.3) where n qtz is the real part of the refractive index of quartz at wavelength λ. At 193nm wavelength, n qtz is In order to achieve effective phase shifting [54-60], the etch depth of the quartz is controlled at 195 nm +/- 1.5 nm or 205 +/

85 An advanced mask CD SEM tool is used to measure the dimension of the critical features on the mask. Mask CD performance, through pitch and linearity, overlay and phase uniformity performance are measured during the mask fabrication process. FIB (Focus Ion Beam) repair tool is used to repair any mask defect while advanced DUV (Deep Ultraviolet) mask inspection tool, equipped with tri-tone inspection algorithm is to qualify the CPL mask. (i) Qualify high quality binary photomask Photoresist Chrome Quartz (ii) 1 st mask writing process (resist patterning with Electron-beam writing tool and development) Fig. 5.5 Chromeless Phase Lithography (CPL) mask fabrication process flow 68

86 (iii) Chrome etching process Photoresist Chrome Quartz (iv) Resist strip process (v) Quartz plasma etching process (use chrome as hard-mask to create mesa ) Challenges: Anti-reflective (AR) coating loss, depth uniformity and sidewall angle (SWA) (vi) Reticle inspection (consider as binary mask) Fig. 5.5 Chromeless Phase Lithography (CPL) mask fabrication process flow 69

87 (vii) Reticle Critical Dimension (CD) measurement (consider as binary mask) CD?? Photoresist Chrome Quartz (viii) Resist coating for 2 nd mask write process (ix) 2 nd mask writing process (resist patterning with laser writing tool and development) (x) Chrome etching process (forming 3 mask types) Chrome Pure Phase Zebra Fig. 5.5 Chromeless Phase Lithography (CPL) mask fabrication process flow 70

88 (xi) Reticle inspection (Tri-tone inspection algorithm: chrome, 0 and 180 ) (xii) Reticle Critical Dimension (CD) measurement CD?? Photoresist Chrome Quartz (xiii) FIB repair (Focus Ion Beam) - to repair any mask defect Fig. 5.5 Chromeless Phase Lithography (CPL) mask fabrication process flow 71

89 xvi) Phase angle measurement Photoresist Chrome Quartz xvii) Pellicle mounting and final inspection xviii) Ex-factory and deliver final product to end user Fig. 5.5 Chromeless Phase Lithography (CPL) mask fabrication process flow 5.3 Chromeless Phase Lithography (CPL) mask wafer printing Lithography tool The 193 nm CPL mask exposures are carried out with an ArF scanner tool and a maximum projection lens at 0.85 NA. The scanner tool is a high NA Step & Scan lithography tool designed for volume 300 mm wafer production. The scanner tool combines the imaging power of a variable NA, double telecentric 4x 193 nm reduction lens with AERIAL II Illuminator technology. Prior to the exposure, a silicon wafer is coated with a resist and a bottom ARC. 72

90 5.3.2 FEM (Focus Exposure Matrix) wafers Several FEM (Focus Exposure Matrix) wafers with a 65 nm CD are printed with different dose energy, defocus and different types of OAI. FEM wafers are used to define the variation of linewidth (and possibly other parameters) as a function of both focus and exposure energy. As shown in Fig. 5.6, an exposed FEM wafer shows an incremental focus setting from left to right column and incremental exposure energy setting from bottom to top row of the shots. Line width of a specific feature or CD (Critical Dimension) is measured using SEM which is used to measure resist profiles and CD by bombarding a sample with electrons and detecting backscattering of the electrons. All CD data are plotted as line width versus focus for different exposure energy setting and these plots are often referred to as smiley, spider, or Bossung plots. Best focus and exposure energy settings are defined from these plots based on the largest process window and closest point to the targeted CD. incremental exposure energy setting incremental focus setting Fig. 5.6 FEM (Focus Exposure Matrix) wafer setting 73

91 5.3.3 Process window Process window is a window created by plotting contours that correspond to various specification limits, as a function of exposure and focus. One simple process window, called the CD process window, is a contour plot of high and low CD specifications as a function of focus and exposure. Other typical process windows include sidewall angle and resist loss. Often, several process windows are plotted together to determine the overlap of the windows. In photolithography, DoF and exposure latitude (EL) are used to define process window. DoF is the total range of focus that can be tolerated, that is, the range of focus that keeps the resulting printed feature within a variety of specifications (such as line width, sidewall angle, resist loss, and exposure latitude). EL is the range of exposure energies (usually expressed as a percent variation from the nominal) that keeps the line width within specified limits. Process window can be improved through RET as mentioned in Chapter DOE (Design of experiment) Table 5.1 and 5.2 illustrate the design of experiments for different illumination types and FEM settings. Table 5.1 is a preliminary investigation to obtain the best exposure energy and focus settings for pure phase, zebra and chrome types that can meet 65 nm CD target. Table 5.2 is to verify repeatability of the lithographic performance (exposure latitude and depth of focus) for pure phase, zebra and chrome types on the best lithography printing conditions (optimum exposure energy and focus). The experimental work is carried out 74

92 with ArF scanner tool at 0.85 NA (sigma in: 0.68, sigma out: 0.92). The exposure energy step and focus step for FEM setting is 0.5 mj/cm 2 and 0.05 um respectively. Table 5.1: Design of experiment I Slot Illumination Type Exposure Energy Settings (mj/cm 2 ) Focus Settings (um) Exposure Energy Matrix (mj/cm 2 ) Focus Matrix (um) 1 Annular to to Annular to to Annular to to Annular to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to

93 Table 5.2: Design of experiment II Slot Illumination Type Exposure Energy Settings (mj/cm 2 ) Focus Settings (um) Exposure Energy Matrix (mj/cm 2 ) Focus Matrix (um) 9 Annular to to Annular to to Annular to to Annular to to Annular to to Annular to to Annular to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to Quasar (30 ) to to

94 Chapter 6 Results and Discussion This chapter presents the results and discussion for lithographic performance of CPL mask under various RET, which include both simulation and experimental results. 6.1 Data handling optimization Three zone layout splitting Figure 6.1 shows wafer CD plotted against designed CD for various mask types with and without SRAF. It shows that pure phase type has the minimum changes on wafer CD against designed CD. Figure 6.2 shows MEEF plotted against designed CD for pure phase type. It is seen that MEEF decreases when designed CD increases. MEEF is low (positive and less than 1) in resolution limit (feature size smaller than 85 nm designed CD). However, with increasing designed CD, MEEF decreases to negative values indicating that no appropriate bias can be applied on the mask feature. From the experimental results, it shows that pure phase type should be used in resolution limit as MEEF is low. For mask feature greater than 75 nm and 180 nm, zebra and pure chrome type could respectively be used. 77

95 DICD, 1x (nm) ISO_OPC without SRAF ISO_OPC with SRAF ISO_Zebra without SRAF ISO_Phase without SRAF ISO_Chrome without SRAF Designed CD, 1x (nm) Fig. 6.1: Experimental results for CPL wafer CD against designed CD MEEF MEEF Designed CD (nm) Fig. 6.2: Experimental results for MEEF against designed CD for CPL pure phase type 78

96 Diffraction Order Amplitude Pure Phase (1 st Order) Pure Phase (0 th Order) Zebra (1 st Order) Zebra (0 th Order) Designed CD (nm) Fig. 6.3: Diffraction order ratio against designed CD at 160 nm pitch Depth of Focus (um) DoF_Pure Phase (Annular) DoF_Pure Phase (Quasar) DoF_Zebra (Annular) DoF_Zebra (Quasar) Designed CD (nm) Fig. 6.4: Comparison of depth of focus from experimental results for different mask types and off axis illumination (OAI) at designed pitch of 160 nm 79

97 Figure 6.3 shows simulated diffraction order amplitude against designed CD for pure phase and zebra type at a pitch of 160nm. It is seen that the optimum process window of CPL is located at a point where the 0 th order curve intercepts the 1 st order curve. For pure phase type, optimum window is achieved at 42 nm designed CD while for zebra type optimum process window is achieved at 50 nm designed CD. Figure 6.4 shows the summary experimental results of DoF for pure phase and zebra type with different illumination types at 0.85 NA and designed pitch of 160 nm. The raw data of experimental FEM results with different designed CD (40 nm, 50 nm, 60 nm and 70 nm), different CPL types (pure phase and zebra) and different illumination types (annular and quasar) can be found in Appendix A. The experimental results show that DoF with the target CD of 65 nm +/- 10 % can be enhanced by optimizing the designed CD, changing the CPL and illumination types. The pure phase type achieves the best DoF with 40 nm designed CD while the zebra type achieves the best DoF with 60 nm designed CD. As shown in Fig. 6.4, there is no process window for 70 nm pure phase CPL type under both annular and quasar illumination at the pitch of 160 nm. For CPL with pure phase type, the 0 th order and 1 st order mask amplitude can be expressed as 0 th 1 order, F 0 = [ p 2w] (6.1) p 80

98 ±1 st 2 πw order, F 1 = sin( ) (6.2) π p where p is the pitch and w is the line width When the line to space ratio is 1:1 or close to 1:1, lens pupil only receives 1 st order light and the 0 th order light will be cancelled. As a result, no images are formed for designed CD of 70 nm and 80 nm at the pitch of 160 nm. This problem can be overcome by changing the CPL type from pure phase (100% transmittance) to zebra type (50% transmittance). Comparison of results between simulation and experimental as indicated in Figs. 6.3 and 6.4 show that the optimum mask feature size agrees well for pure phase but not for zebra type. For pure phase type, simulated and experimental optimum mask feature size are 42 nm and 40 nm respectively. For zebra type, simulated and experimental optimum mask feature size are 50 nm and 60 nm respectively. The difference in the zebra type is due to mask process limitation. The chrome islands on zebra type are fabricated with bigger resolution limit and reduced transmittance. Figure 6.5 shows a top-down SEM view of a 40 nm pure phase mask feature at a pitch of 160 nm. The DICD is targeted at 65 nm +/- 10 %. The experimental results show that 40 nm pure phase mask feature is able to achieve 0.30 um DoF with 14 % of EL. The minimum pitch that can be printed (i.e. the current pitch limit) using existing lithography 81

99 tool (193 nm wavelength and 0.85 NA) is 140 nm, as illustrated in Fig. 6.6 and based on Rayleigh s equation, the value of k 1 is given by: Resolution, R = k 1 λ NA 65*0.85 k 1 = 193 = 0.29 (the current limit) 82

100 E= 22.0mJ E= 23.0mJ E= 23.5mJ E= 24.0mJ E= 25.0mJ E= 25.5mJ F= -0.10um 64.41nm F= -0.05um 65.08nm F= 0.00um 65.72nm F= 0.05um 69.85nm 67.39nm 66.73nm 63.94nm 63.1nm 60.43nm F= 0.10um 66.83nm F= 0.15um 65.79nm F= 0.20um 65.24nm Fig. 6.5: Top-down SEM view of 40 nm pure phase mask features at a pitch of 160 nm 83

101 140nm 40nm Fig. 6.6: A SEM view of a 40 nm pure phase mask features at a pitch of 140 nm Implementation of OPC (Optical Proximity Correction) and SRAF RET refer to the techniques that improve the imaging resolution without changing the wavelength or NA of the imaging system. In general, PSM and OAI do not work for fullchip tapeout unless accompanied by OPC. OPC is employed to move absorber edges on a layout or mask to improve printing resolution. Application of strong OAI on wafer printing can amplify the iso-dense bias. Iso-dense bias occurs when features on a mask with the same dimensions but different pitches print 84

102 with different line widths on a wafer. An isolated line scatters light uniformly over the lens used for wafer lithography while an array of dense lines creates a distinct diffraction pattern that uses only certain parts of the lens [15]. Diffraction angle of the light leaving the mask is highly dependent on the pitch of the mask features. When a pitch is small, diffracted light arises with higher angles. Normally, bigger DICD line width appears at a dense region rather than at an isolated region. Sizing a mask to give correct CD on a wafer for various pitches certainly is feasible however it can not address iso-dense bias problem by just apply the bias. The response of an isolated feature to focus and exposure errors is significantly different to that of a dense main feature of the same size. Different shapes of Bossung curves produce different shapes of process windows, which limit the overlapping DoF even when the features have similar optimum exposure dose. The size of SRAF has to be carefully adjusted so that it will not print over the required process window. This factor determines one of the most important tradeoffs in scattering bar design: maximize assist features in order to create a more dense-like mask pattern, but not so large as to print over the process window. In general, SRAF is dependent on an optimized OAI. With the placement of SRAF, the difference in focus response between isolated and dense feature can be reduced. A combination of SRAF and bias OPC for a main feature with different pitches will lead to an increase in the DoF. If only bias OPC is used, the increase in DoF is less significant. SRAF can also improve the printing 85

103 capability of isolated main features, especially for a feature size which is closed to the resolution limit. Application of SRAF to improve the DoF of isolated main features is not complicated, if it is applied on an isolated main feature only. In reality, an actual layout contains main features with a variety of pitches, each of which must be applied with an optimum SRAF, if possible. Bias OPC has to be applied on intermediate cases where the space between two main features is not large enough to accommodate a SRAF. Besides, SRAF is used on line ends and corners together with the bias OPC to improve pattern fidelity on wafer printing, as shown in Fig. 6.7 and Fig

104 Line end extension SRAF Original Data Data after OPC Fig. 6.7: Through pitch structure at a pitch of 160 nm with OPC and SRAF Line end extension Original Data Data after OPC SRAF Fig. 6.8: Through pitch structure at a pitch of 250 nm with OPC and SRAF 87

105 Figures 6.9 and 6.10 show respectively a comparison of experimental results for isolated main features with and without SRAF for CD which ranges from 30 nm to 180 nm. Pure phase type is used for feature size from 30 nm to 60 nm and for 90 nm, zebra type is employed while for feature size greater than 120 nm, chrome type is used. From the experimental results, isolated main feature of 30 nm can be observed if SRAF is placed adjacent to the main feature. Placement of SRAF on isolated main feature of 60 nm and 90 nm will also enhance the image contrast and pattern quality and LER are reduced. The improvement is significant compared to isolated main feature without SRAF. Isolated main feature of 30nm will not resolve on wafer without placement of SRAF. It is noted that the effect of SRAF is not significant for isolated main feature greater than 120 nm. Figures 6.11 and 6.12 show respectively the summary DoF against designed CD for pure phase and zebra type (with and without SRAF) under both annular and quasar illuminations. The raw data of experimental FEM results for isolated main feature with different designed line width CDs (50 nm, 60 nm and 70 nm), different CPL types (pure phase and zebra), different illumination types (annular and quasar) and, the split of with and without SRAF can be found in Appendix B. The experimental results show that DoF with the target CD of 65 nm +/- 10 % can be improved easily with the placement of SRAF adjacent to isolated main feature regardless of any designed line width (50 nm 70 nm), CPL types and illumination types. For isolated main feature, the DoF can be improved up to 200 % if the SRAF is placed adjacent to the main feature. As mentioned above, it is important to ensure that the SRAF should not be printed within the required process window. 88

106 Gds Data (Isolated feature with OPC and SRAF) Wafer Data (Isolated feature with OPC and SRAF) Gds Data (Isolated feature with OPC only) Wafer Data (Isolated feature with OPC only) NA Designed CD: 30 nm Designed CD: 30 nm Designed CD: 30 nm Designed CD: 30 nm Designed CD: 60 nm Designed CD: 60 nm Designed CD: 60 nm Designed CD: 60 nm Designed CD: 90 nm Designed CD: 90 nm Designed CD: 90 nm Designed CD: 90 nm Fig. 6.9: Comparison of experimental results for isolated main features (CD: 30 nm - 90 nm) with and without SRAF 89

107 Gds Data (Isolated feature with OPC and SRAF) Wafer Data (Isolated feature with OPC and SRAF) Gds Data (Isolated feature with OPC only) Wafer Data (Isolated feature with OPC only) Designed CD: 120 nm Designed CD: 120 nm Designed CD: 120 nm Designed CD: 120 nm Designed CD: 150 nm Designed CD: 150 nm Designed CD: 150 nm Designed CD: 150 nm Designed CD: 180 nm Designed CD: 180 nm Designed CD: 180 nm Designed CD: 180 nm Fig. 6.10: Comparison of experimental results for isolated main features (CD: 120 nm nm) with and without SRAF 90

108 Depth of Focus (um) Pure Phase (SRAF) Annular Pure Phase (SRAF) Quasar Pure Phase (no SRAF) Annular Pure Phase (no SRAF) Quasar Designed CD (nm) Fig. 6.11: DoF against designed CD for pure phase type (with and without SRAF for both annular and quasar illumination) Depth of Focus (um) Zebra (SRAF) Annular Zebra (SRAF) Quasar Zebra (no SRAF) Annular Zebra (no SRAF) Quasar Designed CD (nm) Fig. 6.12: DoF against designed CD for zebra type (with and without SRAF for both annular and quasar illumination) 91

109 For a full-chip tapeout, it is necessary to include OPC and SRAF placement rules in the main features which are designed with a variety of pitches (isolated, semi-dense and dense). A set of test patterns which consist of seven line patterns and the center line is always measured are created. 65 nm lines are measured on a wafer for pitches of: 150 nm, 160 nm, 180 nm, 250 nm, 360 nm and 500 nm with optimized OPC and SRAF placement rules. For pitches from 150 nm to 250 nm, the spaces between the main features are too tight to allow insertion of SRAF in between the lines. Instead, SRAF are added on the outermost lines only. For pitches from 150 nm to 250 nm, a larger OPC bias or a larger movement of the main feature edges (-16 nm to -25 nm) is applied to achieve 65 nm feature size as shown in Table 6.1. For pitches between 250 nm to 500 nm, adding a single SRAF is essential the printing process. A smaller OPC bias (-4 nm) is required at these pitches. For pitches of 500 nm and beyond, adding more SRAF is possible with a smaller OPC bias (4 nm), as shown in Table 6.1. Illustration of SRAF placement in a variety of pitches of main features is as shown in Fig A suitable size of SRAF which would not be printed within the required process window for all the pitch sizes is 25 nm. 92

110 Table 6.1: OPC bias and SRAF placement rules pitches (nm) original feature size (nm) OPC bias (nm) CPL type final feature size (OPCed) phase (nm) chrome (nm) number of SRAF between main feature SRAF size (nm) zebra NA pure phase 40 NA NA pure phase 42 NA NA pure phase 49 NA zebra zebra

111 Pitch: 150 nm Pitch: 160 nm Pitch: 180 nm Pitch: 250 nm Pitch: 360 nm Pitch: 500 nm Fig. 6.13: SRAF placement in a variety of pitches of main features 94

112 Figure 6.14 shows top-down SEM view of zebra type through pitch test pattern (without OPC) with annular illumination and 0.85NA. For other CPL and illumination types (without OPC), the results are shown in Fig to Fig It is seen that without OPC biasing and placement of SRAF, both zebra and pure phase through pitch main features are not able to achieve target CD of 65 nm +/- 10 %. Without OPC biasing and placement of SRAF, both zebra and pure phase main features through pitch performance cannot be improved by changing the illumination types. It is clearly indicated that zebra and pure phase main features without OPC biasing and placement of SRAF are not able to resolve on the pitch of 150 nm and 500 nm. The response of main features with different pitches to focus and exposure error are different, which limits the printability for all main features even when the features are exposed with the same exposure dose. Figure 6.18 and Fig show respectively top-down SEM view of OPC through pitch test pattern (with SRAF) with annular and quasar illumination. It is seen that the OPC test pattern (with SRAF) are able to resolve in all pitches and achieve target CD of 65 nm +/- 10 %. Figure 6.20 shows summary of through pitch performance for zebra and pure phase feature without OPC and SRAF while Fig shows summary of through pitch performance for feature with OPC and SRAF. It is observed that all features which received OPC biasing and SRAF treatment are able to achieve target CD of 65 nm +/- 10 % on wafer printing. Both illumination types (annular and quasar) give reasonably good results. 95

113 Figure 6.22 shows a comparison of results for semi-dense main features (pitch: 250 nm and 360 nm) with and without SRAF. All main features receive OPC biasing. The results show that the wafer image contrast and fidelity can be improved significantly with placement of SRAF adjacent to the main features and without SRAF, the main feature may break off. For main features without SRAF, line width roughness is worst compared to main features with SRAF. 96

114 Pitch: 150 nm DICD: NA Pitch: 160 nm DICD: 86.9 nm Pitch: 180 nm DICD: 73.8 nm Pitch: 250 nm DICD: 60.9 nm Pitch: 360 nm DICD: NA Pitch: 500 nm DICD: NA Fig. 6.14: Top-down SEM view of zebra type (without OPC, through pitch test pattern) with annular illumination and 0.85 NA Pitch: 150 nm DICD: NA Pitch: 160 nm DICD: 90.9 nm Pitch: 180 nm DICD: 69.5 nm Pitch: 250 nm DICD: 66.1 nm Pitch: 360 nm DICD: 49.0 nm Pitch: 500 nm DICD: NA Fig. 6.15: Top-down SEM view of zebra type (without OPC, through pitch test pattern) with quasar illumination and 0.85 NA 97

115 Pitch: 150 nm DICD: NA Pitch: 160 nm DICD: 81.9 nm Pitch: 180 nm DICD: 71.2 nm Pitch: 250 nm DICD: 64.1 nm Pitch: 360 nm DICD: 52.7 nm Pitch: 500 nm DICD: NA Fig. 6.16: Top-down SEM view of pure phase type (without OPC, through pitch test pattern) with annular illumination and 0.85 NA Pitch: 150 nm DICD: NA Pitch: 160 nm DICD: 86.7 nm Pitch: 180 nm DICD: 66.9 nm Pitch: 250 nm DICD: 69.9 nm Pitch: 360 nm DICD: 54.8 nm Pitch: 500 nm DICD: NA Fig. 6.17: Top-down SEM view of pure phase type (without OPC, through pitch test pattern) with quasar illumination and 0.85 NA 98

116 Pitch: 150 nm DICD: 79.5 nm Pitch: 160 nm DICD: 65.8 nm Pitch: 180 nm DICD: 62.0 nm Pitch: 250 nm DICD: 61.0 nm Pitch: 360 nm DICD: 66.5 nm Pitch: 500 nm DICD: 66.7 nm Fig. 6.18: Top-down SEM view of OPC through pitch test pattern (with SRAF) with annular illumination and 0.85 NA Pitch: 150 nm DICD: 90.7 nm Pitch: 160 nm DICD: 63.7 nm Pitch: 180 nm DICD: 61.9 nm Pitch: 250 nm DICD: 67.5 nm Pitch: 360 nm DICD: 69.0 nm Pitch: 500 nm DICD: 63.1 nm Fig. 6.19: Top-down SEM view of OPC through pitch test pattern (with SRAF) with quasar illumination and 0.85 NA 99

117 Wafer CD (nm) Zebra Annular Zebra Quasar Pure Phase Annular Pure Phase Quasar Designed Pitch (nm) Fig. 6.20: Through pitch performance for zebra and pure phase feature (without OPC and SRAF) OPC_SRAF Annular OPC_SRAF Quasar Wafer CD (nm) Designed Pitch (nm) Fig. 6.21: Through pitch performance for feature with OPC and SRAF 100

118 Gds Data (Semi dense feature with OPC and SRAF) Wafer Data (Semi dense feature with OPC and SRAF) Gds Data (Semi dense feature with OPC only) Wafer Data (Semi dense feature with OPC only) Pitch: 250 nm Pitch: 250 nm Pitch: 250 nm Pitch: 250 nm Pitch: 360 nm Pitch: 360 nm Pitch: 360 nm Pitch: 360 nm Fig. 6.22: Comparison of experimental results for semi-dense main features (Pitches: 250 nm and 360 nm) with and without SRAF 6.2 Illumination optimization Process window of several types of illumination including conventional, quasar, annular, high sigma, multipole and multipole setting were compared. Figure 6.23 shows a conventional on axis illumination setting. For off-axis illumination, the settings are shown in Fig Fig It is seen that quasar and multipole settings consist of 4 quadrants while annular and high sigma are designed in donut shape. 101