Immersion Lithography Process and Control Challenges

Transcription

1 management solutions ymsyield Spring Visualizing the Wafer s Edge 22 Broadband Brightfield Inspection Enables Advanced Immersion Lithography Defect Detection 28 New Inspection Technology for 45nm Wafers 33 Unpatterned Wafer Inspection for Immersion Lithography Defectivity 40 Comparing Cost of Image Qualification and Direct Mask Inspection 44 Enabling Double Patterning at the 32nm Node 48 Improving Scanner Productivity and Control through Innovative Connectivity Applications Cover Story: Immersion Lithography Process and Control Challenges

2 Contents COVER STORY 07 Immersion Lithography Process and Control Challenges TECHNOLOGY TRENDS 18 Visualizing the Wafer s Edge 22 Broadband Brightfi eld Inspection Enables Advanced Immersion Lithography Defect Detection New Inspection Technology for 45nm Wafers 33 Unpatterned Wafer Inspection for Immersion Lithography Defectivity Comparing Cost of Image Qualifi cation and Direct Mask Inspection 44 Enabling Double Patterning at the 32nm Node Improving Scanner Productivity and Control through Innovative Connectivity Applications 2 Spring 2007 Yield Management Solutions

3 DEPARTMENTS Editor-in-Chief Charles Lewis Senior Editors David Pinto Reeti Punja Production Editor Robert DellaCamera Art Director and Production Manager Inga Talmantiene Production Consultant Joann Barbou-des-Places Circulation Editor Nancy Williams KLA-Tencor Worldwide Corporate Headquarters KLA-Tencor Corporation 160 Rio Robles San Jose, California International Offices KLA-Tencor France SARL Evry Cedex, France KLA-Tencor GmbH Munich, Germany KLA-Tencor Limited Wokingham, United Kingdom Editorial ProdUCt news the last Word WEB EXCLUSIVE 04 The 32nm Node is Already Here 51 Archer Puma 91xx Series 53 VisEdge CV PROLITH Surfscan SP2 XP 56 Sub-32nm Nodes Bring Megabucks Lithography KLA-Tencor (Israel) Corporation Migdal Ha Emek, Israel KLA-Tencor Japan Ltd. Yokohama, Japan Advantages of Broadband Illumination for Critical Defect Capture at the 65nm Node and Below KLA-Tencor Korea Inc. Seoul, Korea KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia KLA-Tencor (Singapore) Pte. Ltd. Singapore KLA-Tencor Taiwan Hsinchu, Taiwan KLA-Tencor Software India Pvt. Ltd. Chennai, India KLA-Tencor China Shanghai, China Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions and web exclusive articles, subscribe online at: For literature requests, visit: For information, visit: KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identifi ed by trademarks of their respective companies or organizations. 3

4 Editorial The 32nm Node is Already Here Ben Tsai CTO, KLA-Tencor Corporation To technologists at the leading edge of chip development, the 45nm node is almost a done deal. They are looking ahead already to the challenges of 32nm and beyond. Since the most advanced inspection and metrology technology must keep pace with the latest developments, I want to briefly mention some of the issues we see emerging at the 32nm node. Customers are well aware that new tools and inspection strategies are essential to overcome the blurring of defect categories in deep nanometer-scale device designs. With the extremely tight process windows of 45nm and below designs, a slight variation in the process can appear to be almost like a random defect because so many conditions are close to the process window margin. It can be very hard to distinguish systematic from random defects. Advanced metrology and inspection tools must produce not only accurate data and information, but enable users to take corrective actions that improve yield. Accurate defect classification and binning to distinguish systematic from random defects is one of the most critical areas of development. The patterning process is going to be a second challenge. Many experts believe that patterning will continue to use 193nm immersion lithography tools, but with double or even triple patterning methods. More patterning layers, plus more interactions between the patterning layers, will require much more control to stay within the process window. There will also be more reticles to inspect. All of this patterning complexity means that more overlay and CD measurement steps will be needed to ensure that the lithography process is under control. Between now and 2010, when 32nm is expected to be in production, the precision requirements of metrology tools are pushing beyond CD-SEM capability, making optical CD (OCD) scatterometry even more important. I expect the adoption of OCD technology to increase significantly because it provides more precise measurements for increasingly tight process windows. OCD throughput is much faster than CD-SEM, allowing chipmakers to do more measurements, a requirement for 32nm devices. Ben Tsai ben.tsai@kla-tencor.com Overlay metrology is also positioned for growth. With double patterning, the CD linewidth is closely linked to the interlayer overlay. Overlay precision requirements are much tighter, and customers will need to measure the overlay much more often. They may have to start measuring the overlay on every wafer. At the 32nm node, the industry is likely to introduce new materials, including more widespread adoption of high k materials and additional use of low k materials. Greater variety of materials requires inspection tools to have a higher level of sensitivity to find more defects, as well as greater wavelength flexibility to find the defect and measure it on a wider range of materials. The approach to 32nm is revealing many additional applications for e-beam inspection, in layers where it wasn t necessary before. Customers are now developing combinations of optical and e-beam technologies to develop and qualify and monitor certain layers within a comprehensive inspection strategy. We are working closely with our customers to develop BKMs for different layers and materials, using the optimal sampling methodology and strategy between e-beam and optical technologies. Technologists at KLA-Tencor and our customers are already working at 32nm design rules. This kind of futuristic work is what keeps our industry vibrant and always moving forward at high speed. We hope that this issue of YMS magazine helps highlight interesting areas of technology that help our customers stay on the bullet train of Moore s Law. Spring 2007 Yield Management Solutions

5 PERFECT YOUR PATTERNING PROCESS BE FIRST LITHO SOLUTION: RETICLE QUALITY ASSURANCE With tolerances shrinking and processes constantly changing, maintaining reticle quality is a growing challenge. Take charge with KLA-Tencor litho control solutions. Get the precise data you need for making smart decisions quickly to ensure reticle quality. With the right reticle qualification strategy, you can pinpoint yield-relevant mask defects before they print. Before they affect yield or device performance. Result: a higher-yielding, reliable patterning process. Your patterning process control resource

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7 Cover Story Immersion Lithography Process and Control Challenges Irfan Malik, Viral Hazari, Kevin Monahan, Matt Hankinson, Mike Adel, Marcus Liesching, Edward Charrier KLA-Tencor Corporation Immersion lithography enables higher resolution, but also introduces new defect mechanisms. Process development, characterization, and ongoing cell qualification and monitoring must be adjusted to represent the new interactions and dynamics of immersion technology. It is critical for fabs to implement new defect management strategies that can handle immersion-specific defects, immersion-related overlay errors, and new sources of CD variations. Hyper-NA immersion 193nm (ArF) lithography provides the technological advances required to obtain production yields in 65nm (half-pitch) patterning and to progress towards 45nm. With added technology, such as double patterning and fluids with indices of refraction greater than that of water, immersion lithography (ilitho) is likely to extend to 32nm and beyond. Immersion optics enable the printing of smaller design rules by increasing the effective numerical aperture (NA) of the imaging lens. 1 In the case of water immersion, NAs up to 1.35 have been achieved. 2 While this allows printing of smaller features at higher yields with a better process window than equivalent dry systems, 3, 4 immersion imaging is a more complex process that presents numerous challenges. Process integration for ilitho is more challenging as it involves a tighter coupling of illumination, mask, imaging optics, optomechanics, wafer, materials, dynamics, and process control. Immersion lithography also introduces several new problems in the areas of image modeling and creation, defectivity, systematic errors, and materials. While some of these problems are understood and contained, solutions are still needed for others in order to reach competitive manufacturing yields.

8 Cover Story Sub-wavelength Lithography Deep Sub-wavelength Lithography 365nm 350nm Wavelength Linewidth 248nm 193nm Immersion lithography Liquid recovery Projection optics Wafer stage Scanning motion Liquid supply 180nm 157nm 130nm 90nm 65nm OPC at 180nm 45nm Aggressive OPC at <130nm Process window shrinking on average >30% per node 32nm Figure 1: New technologies must be introduced to continue to enable design rule reduction well below the exposing wavelength. 5 This paper explores the manufacturing challenges related specifically to the integration of ilitho, including: New materials (fluid, topcoat, resist) which have new physical and chemical interactions New thermodynamics due to the thermal mass and evaporative cooling of the immersion fluid New interactions from the edge of the wafer and scanner stage New defect mechanism sources Increased optical interactions due to hyper-na imaging Resist Topcoat Fluid Incoming Wafer ilitho Defectivity Carryover from Stage Unprecedented coupling of scanner hardware and wafer Figure 2: Contributors to immersion litho defectivity. 6 Scanner Scan Parameters Developer Additionally, we discuss control strategies for process development, litho cell monitoring and production line monitoring, including the identification of best-known methods (BKMs) for mitigating some ilitho problems and possible tools and approaches for unresolved challenges. Immersion Lithography s Impact on CD The higher NA of immersion scanners allows smaller features to be patterned when compared to an equivalent dry system, since a dry system cannot have a NA greater than 1.0. The depth of focus (DoF) is enhanced by immersion relative to equivalent dry imaging, but the process window is still very small. Other effects are also important, including polarization, polarization homogeneity, optical surface effects, birefringence, absorber characteristics, and mask and wafer topography. 7, 8 Resist profile control is becoming a significant portion of final critical dimension (CD) control. The smaller patterns are sensitive to any change in sidewall angle (SWA). The greatest effect on SWA is seen for some resists with post-exposure wetting time, suggesting that the photo-acid generator leaches after exposure. 9, 10, 11, 12,13 Leaching and water absorption change the n and k of the resist. Leaching of resist components can also create t-topping or defects such as bridging. 14, 15 Topcoats generally reduce leaching effects. Thermal variations also affect CD uniformity, with perturbations seen as a first wafer effect, or as variations across the wafer. 9 Swelling due to water uptake 16 may also have global CD impact or cause localized CD variations. 17 Fabs are increasingly using metrology tools to monitor CD and sidewall angle (SWA) on production lots, and this becomes even more important with immersion creating additional mechanisms which impact SWA within a very tight CD Spring 2007 Yield Management Solutions

9 Cover Story budget. Fabs also make use of the CD and profile measurement capabilities of spectroscopic ellipsometry-based CD (SCD) metrology systems for immersion studies and in-line measurement. Given the additional complexities of the patterning process with immersion and hyper-na optics, modeling has become an essential part of quickly designing and optimizing the process. Because of the large illumination and imaging angles, vector models are absolutely required. The model must account for: Source shape and polarization Mask 3D topography effects Mask material characteristics Optical proximity correction (OPC) and phase-shift mask (PSM) strategies Pupil effects Resist characteristics To obtain the largest possible process window and to avoid zero-yielding collapsed windows, every aspect of the process and its components must be modeled and optimized. Lithographers typically use a simulation tool, such as PROLITH TM, to investigate alternatives. Walking a thin tightrope with the use of OPC, lithographers must also make sure that resist features do not print, causing systematic pattern defects. Optimizing Overlay for Immersion Lithography Ongoing reduction of design rules continues to squeeze overlay requirements, and immersion lithography adds additional hurdles, some of which are not yet completely understood. High overlay error is a yield detractor (Figure 3). Overlay Limited Yield (%) Gate Overlay Error (nm) Figure 3: Overlay-limited yield at gate layer nm 180nm 130nm 90nm 65nm 45nm Several components contribute to overlay error on product wafers, including: Scanner performance Process contributions to scanner and metrology error Thermal effects, both global and local Overlay mark design Measurement tool error Sampling errors Inappropriate models Unexplained errors which cannot be corrected The major scanner manufacturers are shipping scanners with 7-8nm single machine overlay error, which is higher than dry performance. 18 While improvements will be made in each successive scanner generation, the current performance is weaker than that desired by leading fabs and device designs. Overlay models are used to understand the contributors to overlay error, and to extract corrections which may be fed back to the exposure tool to compensate for the errors. The better the model represents what is happening during exposure, and the more inputs the scanner can take for correctables, the better the resulting overlay will be. However, not all identifiable components are correctable. Some may be adjustable during a lot exposure (or between lots), some may require a scanner adjustment or calibration, and some will just be the characteristic fingerprint of the scanner (or individual stage). Whatever cannot be explained by an appropriate model will show up as unexplained errors, often called residuals. With immersion, higher residuals have been seen, and data presented in the literature suggest that there are a few ilitho specific areas which may contribute to overlay degradation. Temperature of the wafer, stage(s), and fluid impact overlay. These may result in a constant error, or may vary over time as components change and equilibrate. First wafer effects have been seen, where the first wafer(s) in a lot exhibits different overlay behavior from the remainder of the lot. 9 If a delay slows the progress of a lot, wafers which follow the delay may also exhibit this effect. 9 Additionally, test wafers, which are more like first wafers from a lot, may give misleading results which do not represent manufacturing conditions. In the past, overlay performance across the lot tended to be uniform, showing low wafer-to-wafer variation. This meant that fabs could effectively sample any wafer from the lot and know with a high degree of confidence what any other wafer in the lot looked like. But with the dynamic thermal effects coming from immersion, that may no longer be a valid assumption, and test wafers will also be less reliable predictors. Some fabs have taken to measuring a larger number of wafers from a lot to better understand and control wafer-to-wafer variation. The moving mass of water and the air curtain contribute to overlay error on a more local scale. Rapid motion of the wafer and puddle under the lens may create inhomogeneous thermal conditions, resulting in unmodeled overlay error (shown as higher residuals). 19 Grid scaling error has been seen to increase as the trailing edge water contact angle decreases, suggesting cooling from evaporation from more hydrophilic surfaces. 10

10 Cover Story Within the field, scanning-direction magnification error increases with receding edge contact angle. 10 Both of these errors are correctable, but they must be characterized and monitored. When droplets of water are left behind, evaporative cooling creates localized error. 20 Differential overlap of fluid between fields (the puddle extends beyond the current exposure field into fields which have not yet been exposed) makes the thermal history of each field challenging to decompose and model. Fabs use overlay measurement and analysis to model these effects, as described in the section on control strategies. The boustrophedonic (zig-zag) motion of the scanner (field and grid) has not contributed to overlay error for several generations. However, with immersion, a hydrodynamic 20 or fluid drag 9 effect has been suggested to contribute to higher residuals. Water on the wafer backside has also been seen to degrade overlay accuracy, introducing up to 10nm of additional error. 20 While measures are taken in the scanner design to avoid backside water droplets, a failure can have an impact on overlay residuals. Inspection for evidence of backside water is discussed in the defect section. Since defect data analysis tools can represent backside defect data in frontside coordinates, it may be possible to correlate backside inspection results to some overlay residuals. No manufacturing data have been presented on this, so it is not clear if such problems will systematically appear in consistent locations, or whether the spot placements will be random. It does suggest that backside monitoring should be done periodically to ensure that droplets do not end up on the backside, and that the engineer responsible for overlay should be aware of backside inspection monitoring. Topcoats are still being investigated by most fabs; their impact on overlay and other issues is explored below. Immersion-related Defects Defects arising from immersion lithography are not dramatically different from established litho defects, but they do come from different mechanisms, and arrive in different ratios than in dry lithography. Source determination takes wellestablished approaches, but requires understanding of new mechanisms. New and immersion-enhanced defects include particles, bubbles, watermarks (with pattern effects of bridging, line slimming and broadening, and drying stains) and bridging, 15, 16, 17, 21, 22, 23, 24, 25 as shown in figure 4. Higher scan speed generally contributes more defects through multiple mechanisms, and this is compounded with contact angle. 21, 26, 27 Lower hydrophobicity (smaller receding contact angle) tends to increase the number of observed defects. The most obvious new source of defects is the immersion fluid and its transportation of particles. Particles can come from multiple sources, such as the wafer (front surface, bevel, backside), the scanner stage, lens and shower mechanism, or the water itself. Particles may also come from damage resulting from the motion of the water across the edge. Filtration should remove particles suspended in the immersion fluid in most cases, but failure of the system can happen. Periodically, a contaminating event will drive up the count, saturating the filter or leaving contamination in places where it can be picked up again. On-scanner cleaning systems can suppress particles to counts below 0.04/cm 2. Particles can generate several types of defects: Particles which are in place during exposure block or scatter light (micromasking), creating extra or distorted pattern. These particles may be in the puddle, or in contact with the wafer surface. 17 Particles remaining on the wafer after exposure can act as a developer block, creating extra pattern. They may even remain after development and rinse. Particles which have been picked up and not filtered are often seen as deposits parallel to the scan direction, 28 or as semicircles at positions where the scan turns (Figure 5). Bubbles in the water during exposure, particularly those adhering to the wafer surface, act as lens elements. This results in extra, missing, or otherwise distorted patterns. 28 Most reports identified bubbles as a large problem during early immersion development, but current showerhead designs seem to have eliminated them, at least away from the wafer edge. It is useful to be aware of bubbles as a potential defect type in case of an Bubbles Microbridging Droplets / Watermarks Small and large particles Figure 4: Examples of immersion-specific defects Spring 2007 Yield Management Solutions

11 Cover Story Resist and Topcoat Topcoats and low-leaching resists are being investigated as a W_01 W_02 solution to some metrology and W_03 W_06 defect problems. In general, W_07 W_08 topcoats allow more flexibility W_09 in managing the contact angle, W_10 W_11 which affects numerous aspects W_12 W_13 of patterning quality. Topcoats W_14 chosen for a higher contact W_15 W_22 angle reduce the number of W_23 defects as compared to no topcoat or a topcoat with a lower W_18 W_19 W_20 contact angle. 21, 22, 40 Topcoats add cost and time to the process, but currently provide the Figure 5: The accumulated particles from the stacked maps enhance the signature from the path of the puddle. 9 best route to improved results. However, adding another film excursion. Next generation fluids may also see the return of creates the opportunity for bubbles. additional defects (in the film and in coating errors), and can create other process challenges. A topcoat may be developer soluble, or may need a separate solvent. A post-exposure rinse on a soluble topcoat can reduce defects. 40 Droplets of water which escape the trailing edge of the puddle or are atomized through splashing may dry and leave residue. The escape of water droplets increases with scan speed and with decreasing contact angle of the trailing edge of the puddle. Numerous researchers have proposed various mechanisms by 16, 17, 21, 22, 23, 24, 28 which these create pattern errors, including: Leached substances (typically the photo acid generator (PAG) and quencher) from the films are dissolved in the water droplet. When it dries, they precipitate, and act as a developer stop. These are sometimes called drying stains. Leached substance depletion changes the solubility of the resist. This can result in line slimming, bridging, or t-topping. Leached substances are concentrated during drying, and migrate back into the resist, changing the resist solubility. This can result in line slimming, bridging, or t-topping. A droplet on a yet-to-be exposed area may swell the resist stack or leach chemicals, resulting in CD variation, bridging, or slimming. Absorbed water creates migration of substances within the resist, changing the solubility in the local vicinity. In addition, some of the transported particles may be water soluble, or some failure within the system may result in the water supply not being as clean as expected. Pre- and post-exposure rinses have been shown to reduce the number of water spots and particles for some materials prior to 25, 40 development, although they do increase wafer cycle time. Post-exposure rinse is most effective when the droplet is still liquid, as the spot may not be as easily removed if it has had the opportunity to dry. 17, 24 This means that the conditions for the portion of the wafer exposed early are different from the portions exposed later. It is good to be aware of the exposure path when diagnosing defect problems in general, and for water spots in particular. Excess BARC, resist, or topcoat film near the edge, on the bevel, or on the backside can flake or be lifted during immersion exposure. Edge engineering is done to reduce defect sources from the wafer edge. 32 With immersion, the fluid puddle can sweep up particles from the edge, and even delaminate the films near the edge. 25, 40 The force of the water, either from the onrush of the puddle, or from capillary force from the trailing edge, can lift films at the edge and then rewww.kla-tencor.com/ymsmagazine The topcoat can also increase stress on the wafer, adding additional overlay errors. 27 On wafers with underlying topography, a thin topcoat over steps may create pattern deformation, and a thin topcoat may result in scaling error. 20 The error can come from both the exposure tool s alignment system and from the metrology tool, so it is important to understand the process-induced error, and how to optimize each tool s setup to minimize it. At this point, most fabs are choosing to use topcoats, although the development of effective low-leaching resists may reduce the need. The Wafer s Edge To maximize useful real estate on the wafer, fabs have been squeezing the edge exclusion farther out to the edge of the wafer, with 1.5mm targeted for the 65nm node. 30 However, device yields near the edge are challenging, and may be 50% of yields on the rest of the wafer. 31 During resist coating, surface tension in the liquid resist film can cause a physical buildup (or bead) of resist at the wafer s edge and on the bevel. Once dry, this buildup can create problems for the exposure tool focus for fields near the wafer edge, or it can flake off and create defects. By cleaning the edge and bevel of the wafer, edge bead removal reduces contamination on wafer handing arms and carriers. Ilitho makes this even more important. 11

12 Cover Story Bubble Delamination Particle Debris After Exposure Before Develop BARC Before Exposure BARC a. b. c. Resist Resist Figure 6: Wafer edge defects: a) SEM image of blister undergoing delamination; b) Typical bubble, delamination, and debris; c) Delaminated BARC due to peeling by showerhead. deposit flakes elsewhere on the wafer, or on the stage or lens assembly. Anything which is on the edge of the wafer, even on the backside edge in some cases, can deposit onto the working front side. 25 Immersion lithography demands greater consistency in edge engineering. These requirements, along with the drive to maximize the useful area of the wafer, necessitate a better understanding of the full wafer, including its edge. 30 Until recently, it has been difficult to obtain adequate quantitative information about the edge of the wafer. New tools have been developed to specifically address this requirement. (Please see the paper Visualizing the Wafer s Edge on page 18 for further details.) A recently introduced edge inspection tool inspects the bevel, apex, and the front and back of the wafer near the edge using several information channels. It can identify whether defects are bumps or divots, and it clearly images flakes, popped films, and many other defect types (Figure 6). Its output is compatible with defect analysis tools, so defects found on the edge can be correlated to events found on the front (and back) of wafers by other inspectors. Control Strategies Defect, CD, and overlay control approaches are well established in the lithography cell. These strategies generally also apply to immersion, although fabs are making some modifications and focusing attention in slightly different ways. This section describes existing BKMs and new applications for ilitho process control. Process Development and Engineering Analysis One goal of process development is to identify and minimize critical yield issues. This includes: 12 Finding all important defect types and identifying their sources; Optimizing the process window and understanding the parameters which reduce it; Validating models and collecting data for input into design for manufacturing (DFM) tools; Identifying systematic overlay components, both adjustable and non-adjustable. The learning during this phase establishes the baseline for production, and creates libraries of known defects and parametric behaviors. Initially, this knowledge is used to qualify the scanner, while eventually it aids in production monitoring of process window, overlay error, and defectivity. Furthermore, early detection and ongoing management of killer litho defects and process window excursions result in significant cost savings through yield, rework, and immersion litho cell productivity improvements. 33 Process development and early yield characterization can be divided into the following categories: bare wafer characterization; defect process optimization; CD and overlay optimization; and, process modeling. Each of these is described in further detail below. Bare Wafer Characterization Inspection of bare wafers and blanket films plays an important role in ilitho process characterization. The way that films, the scanner, and water interact on blanket wafers can help identify which defects arise from the interaction with water, leading to a better understanding of the immersion process. When using test wafers for ilitho process development, it is important to simulate the actual process and materials as closely as possible, since contamination and water droplet behavior is strongly affected by scan speed and contact angle. These cases illustrate how high-sensitivity unpatterned inspection systems can be used for ilitho process development: Water spot formation can be characterized by running both dry and wet, and comparing the inspection results. Identification of different defect characteristics of exposed and unexposed regions can be accomplished Spring 2007 Yield Management Solutions

13 Cover Story by running tests with no exposure and exposure but no develop, and comparing the inspection results. Rapidly establishing a baseline by defect type using unpatterned inspections can help quickly ramp the ilitho cluster, and is useful for process improvement, ongoing monitoring and future process changes. The post-exposure rinse and development process can be optimized by running wafers through the process without exposure and monitoring how defect levels vary with changes to the process parameters. It is important to be aware of the scanner path across the wafer to determine if there is a correlation between the time droplets are created, and the ability of the post-exposure rinse to clean them off. Characterization of defect signatures can be related 28, 34 to the scan path. Using bare wafers as a development tool, IMEC employed a particle per wafer pass (PWP) test methodology to determine whether defects came from the resist stack or from immersion process interactions. By running the test on bare wafers and on the stack, and comparing results from the unpatterned and patterned inspectors, defect sources were more clearly pinpointed. 34 (For more information, see the paper Unpatterned Wafer Inspection for Immersion Lithography Defectivity on page 33.) An important component of bare wafer characterization and overall process yield development is Defect Source Analysis (DSA), a tool used to partition process steps to determine the specific process step where a defect appeared. DSA enables more efficient process optimization by allowing the engineer to focus only on current process level defects. DSA works with defects from many inspectors, including those found using backside inspection. As shown in figure 7, DSA can be used to identify defects specific to the immersion process. DSA of blanket film pre-exposure inspection results and post-exposure broadband brightfield inspection results has greatly assisted in the identification of pre-exposure defects related to pattern defects. Short-loop Process Optimization Defect Short-loop experiments utilize patterning on blanket or bare wafers to represent the full process step. The three types of short-loop processes include: Blanket film for process window and defect optimization, providing the least pattern noise; Patterned film for process window, overlay, and defect optimization, most closely simulating the manufacturing process, but with increased noise; Bare silicon for investigating immersion defect interactions. For defect issues, the Photo Cell Monitor (PCM) is a wellestablished method for qualifying a litho cell, and for ongoing production monitoring. It uses a short-loop process to maximize sensitivity to the defects of interest, while suppressing noise from other patterned layers. The basic PCM steps include: Determine the films to use. Inspect the incoming wafer prior to patterning. Pattern (coat, expose, develop) using either a test reticle or a device layer reticle. Inspect on a broadband brightfield inspector. Use DSA to identify added defects. 35 Track defects by type using automatic defect classification and binning. Short-loop experiments, combined with PCM, are used to quickly determine which process conditions produce the fewest defects. Comparisons can be made between different film stacks, dry and immersion exposures, or variations in other parameters such as scan speed or post-exposure rinse times. Non-Immersion Specific Immersion & Non-Immersion Specific (a) Bare Si Defect (b) BARC (c) Resist Coating Defect (d) Resist Coating Defect (e) Exposure & PEB Defect (f) Development Defect Developed Topcoat After PEB Resist BARC Wafer * DSA (defect source analysis) is the method to superimpose multiple layers of defects and track the defect source back into the prior process steps. * DSA can filter out non-immersion specific defects. Figure 7: Klarity TM Defect Source Analysis separates new defects from previously existing defects. 13

14 Cover Story Composite wafer maps made by stacking data from multiple wafers and/or multiple lots are used for enhancing defect signatures when there are not many defects on individual wafer maps. Field stack composite maps where all fields from a wafer or set of wafers are combined have been useful in identifying immersion-related signatures. For Process Window Qualification (PWQ), a special case of PCM, the focus and dose are varied to determine the patterning limits of the process window and to evaluate the impact of the process window on pattern defect formation. Defect inspection using PWQ will identify patterns in the mask design which fail within the process window, and are not specifically measured on the CD tool. Known weak points established by this inspection become candidates for CD measurement and profile characterization with SCD, and are fed back into DFM. Fabs typically perform defect process optimization using high-na broadband brightfield inspectors. 29 DSA, composite maps, and spatial signature analysis (SSA) provide a rich toolset for driving the process to minimum defect levels. Once the process has been developed, baselines for defect types are established, which are then used for ongoing litho cell production monitoring. 14 Controlling CD and process window now requires use of line profile, or sidewall angle. For both CD and overlay, the primary impact of immersion is on uniformity across the field, the wafer, and the lot. Short-loop Process Optimization CD and Overlay As described above, CD unifomity and overlay issues related to immersion may arise from several sources, including thermal stabilization, leaching of PAG and quencher, and water absorption into the resist and topcoat. While researchers continue to investigate these effects, suppliers are developing resists and tools which mitigate their impact. As each new process is introduced, fabs will be required to characterize and optimize the process window and process capability index (Cpk) for their product mix. Characterization approaches for overlay and process window are not significantly different than in prior generations, considering that feature sizes are incrementally smaller. Control- ling CD and process window now requires use of line profile, commonly represented as SWA. For both CD and overlay, the primary impact of immersion is on uniformity across the field, the wafer, and the lot. Wafer-to-wafer variation is affected by the first wafer effect and the delay effect. The stability of the first wafer effect within a given litho cell and among litho cells is yet to be determined. If it varies over time, fabs will need to sample more carefully within the lot. However, if the first-wafer effect is stable, then it may be possible to have compensating scanner recipes for the first wafers. The delay effect is more complicated. More work needs to be done to eliminate the delay and to find ways to compensate for any occurring delay. Across-wafer variations arise from a combination of thermal effects and wetting times. A large portion of the CD and overlay related yield loss is seen near the wafer edge, suggesting that more attention to the edge may help to identify sources of variation. While overlay models do not account for the grid nonlinearities seen near the edge, some fabs are exploring whether a segmented model (one for edge fields, another for the rest of the wafer) may provide better adjustments, with appropriate spatial sampling. Increased sampling does impact throughput. Some SCD tools have a CD and SWA measurement time of only two seconds per site, supporting the larger number of spatial measurements needed for adequate CD uniformity characterization and control. Also, the lower total uncertainty of SCD measurement improves the ability to detect smaller variations in CD nonuniformity. Localized CD variations and high overlay residuals are also seen elsewhere on the wafer, including field-to-field differences and across-field variations. The immersion-related sources of these localized variations are not yet well understood. In the case of overlay, fabs can now use grating targets which are small enough to be placed in internal scribes and which act as replacements for dummy-fill in device areas (Figure 8). For dry patterning, significant reductions in residuals have been achieved by enhanced intra-field sampling which enables high order field level modeling. 36, 37 Because of thermal across-field effects, this may be an enabling requirement for overlay process control when immersion lithography reaches production. Thermal variations have also been identified as a source of focus variation, resulting in CD changes across the wafer and fields. It does not make sense to create focus/dose matrices on production wafers, but SCD can estimate the dose and focus of a single measurement. Evaporative cooling from backside droplets contributes to localized overlay error. If backside inspection is done after patterning, it should be possible to use the backside maps to correlate water spots to overlay errors. Given that droplets are random, the inspection will need to be done on the same wafer. During development, a suspect wafer can be sent to the inspection system for analysis, but during production, the focus must be more on eliminating any backside water. Spring 2007 Yield Management Solutions

15 Cover Story Process Modeling Lithographers use modeling to develop new processes. Hyper-NA immersion lithography needs accurate modeling treatment to account for OPC, polarization, and mask topography effects. Predictive model accuracy should co-optimize the OPC rules and the process (Figure 9). AIM TM Overlay Target µaim TM Overlay Target Figure 8: Micro-graling overlay targets (µaim) are small enough to be placed at multiple locations within the scanner exposure field. Once the process is established, fabs monitor CD, SWA, process windows, and components of overlay error for each process layer and scanner/resist/cup combination. This identifies any weak points which will need specific monitors during production. Furthermore, as each of these CD and overlay effects is understood on a systematic basis, it may be possible to build appropriate corrections into scanner and track recipes, and into automatic process control (APC). Where the systematic variation does not fully explain the variation, it will be necessary for fabs to add the variant cases to sampling plans and fault detection and response. In each case, characterization will establish baseline specs which will then be used for photocell and product line monitoring. Exposure Latitude DOF (microns) NA = 1.2 σ = 0.73, nm lines 110nm pitch Random Azimuthal Figure 9: Co-optimization of OPC with advanced polarization requires advanced modeling with PROLITH. This example shows the increase in process window of azimuthal polarization over random polarization. 3 Litho Cell Monitor The yield optimization strategies learned during process development result in optimized baselines, often based on simplified (single layer or short-loop) processes. Fabs typically use the final parameters established during development to implement ongoing monitors. The monitors are run each shift for each resist/cup path/scanner combination. They are also used to qualify a new litho cell, or to requalify one after maintenance. The following summarizes the monitors commonly established by fabs, including the required tools: Unpatterned wafer PWP simplified process with similar hydrophobicity: Monitor and track by defect type and by total defectivity on frontside and backside; Unpatterned wafer inspectors and defect analysis tools. Defect PCM simplified process optimized for sensitivity to defect types: Monitor and track by micro defect type and total micro defectivity; Printed with test reticle; Broadband brightfield inspectors and defect analysis tools; Monitor and track macro defects by type for coat (BARC, resist, topcoat) and develop; Macro wafer inspectors and defect analysis tools. CD and SWA simplified process: Monitor and track specific CD features; SCD metrology systems. Process window simplified process: Monitor process window determined by CD and SWA for nominal dose, dose range, nominal focus, focus range; SCD metrology systems with total process window analysis; Monitor defect process window; Printed with test or chosen product reticle; Broadband brightfield inspectors, PWQ application and defect analysis tools. Overlay simplified process: Monitor components of overlay including sub-field monitor; Overlay tools with extracted overlay error components. 15

16 Cover Story Production Line Monitoring Immersion litho defect control is most cost-effectively served by PCM for pattern defects, unpatterned wafer PWP for contamination, and product line monitor for macro defects. Each should have a baseline established by defect type, and monitored against the established limits. One risk associated with immersion lithography is the potential for scanner stage contamination and the costly side effects which include yield loss and litho cell downtime. If a single wafer arrives with heavy contamination on the top surface or edge, the puddle can move particles to the scanner stage. From that point on, those particles will become an ongoing source of defects until the problem is recognized, and the stage is cleaned. A long cleaning will reduce the immersion litho cell s productivity. As a result of this risk, it may be most cost effective to carefully inspect a significant number of all wafers coming into immersion cells, including the wafer edge. The major difference for immersion is that the new nonlinearities which result in global and localized errors must be represented by appropriate sampling. Because of the sensitivity to focus observed with immersion, it is important to monitor focus on production wafers. However, it is not practical to place a focus/dose matrix on production wafers. SCD, through its calculation model, can provide scanner focus and dose information from the feature profile. 38, 39 This helps to monitor and provide focus information on product wafers. The cost of defect excursions will be significant. Based on past experience with dry lithography, a typical excursion impacts about 30 lots of wafers. Assuming a fab uses immersion on four critical layers, rigorous sample planning analysis estimates that excursions due to new immersion defects can cost a fab about US $31M per year, nearly the cost of a new litho cell. This is on top of excursion costs for defects not specific to immersion, which have been estimated to be US $13M to US $150M annually for defects preventable by PCM. 33 Summary Immersion lithography brings the advantage of higher resolution, but also brings many new challenges. Researchers are working to fully understand ilitho defect mechanisms, and to reduce their frequency through process, material, and tool innovation. Only gross defectivity has been addressed to date; as volume production ramps up further improvements will be made. This paper explores some of these mechanisms, and identifies defect management strategies appropriate for immersion lithography, with particular emphasis on immersion-specific defects. Edge-sourced defects are a new and significant cause of defects. New tools, combined with established practices, show promise in controlling defects coming from wafer edges. One risk associated with immersion lithography is the potential for scanner stage contamination. If a single wafer arrives with heavy contamination on the top surface or edge, the puddle can move particles to the scanner stage, resulting in reduced litho cell productivity. Economic Considerations Several fabs have observed that, due to the complexities added by immersion, process development and litho cell qualification are taking longer than comparable dry systems. This means that ramp time for a new process is greater, putting more pressure on getting a new process to market on time. Implementing the yield management and process development optimization strategies outlined in this article are important components for reducing the time and money required to ramp the immersion litho cell. Depreciation for an immersion litho cell is on the order of US $1M per month, making any downtime very costly. Production monitoring solutions must be implemented in order to quickly recognize and correct excursions. Stage contamination is a new and significant issue for immersion, and cannot be resolved quickly without repeated requalification. Furthermore, the addition of water to the scanning system suggests that production litho cells may have lower reliability than comparable dry systems. Immersion overlay performance is weaker than comparable dry overlay. Overlay models do not yet account for the observed immersion effects, most of which appear to be affected by the dynamic thermal environment. Greater CD variations have been seen with immersion than with dry lithography; this larger variation presents a yield challenge. The ability to measure feature profile is a useful tool for CD control and to better determine the process window. Ilitho process development, characterization, and ongoing cell qualification and monitoring are similar to existing practices, but must be adjusted to represent the new interactions and dynamics of immersion. While many of the problems related to immersion lithography are well on the way to being minimized, failures of subsystems do happen in real production. Fabs will avoid significant costs if they can detect and respond to these excursions quickly. The learning here will extend to the next immersion generation, when water is replaced with a higher index fluid. 16 Spring 2007 Yield Management Solutions

17 Cover Story Acknowledgements The authors would like to thank Scott Ashkenaz for his assistance with this paper. References 1. W. Taberelli and E. Loebach, Apparatus for the photolithographic manufacture of integrated circuit elements, U.S. Patent No. 4,346,164 (1982). 2. W. Arnold, Extending 193nm Optical Lithography, Semiconductor International, September C. Mack, Exploring the Capabilities of Immersion Lithography, IEEE/ SEMI Advanced Semiconductor Manufacturing Conference, D. Gil, et al, Characterization of Imaging Performance for Immersion Lithography at NA=0.93, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, K.M. Monahan, Enabling DFM and APC Strategies at the 32nm Technology Node, IEEE International Symposium on Semiconductor Manufacturing, I. Malik, B. Pinto, Immersion Changes Litho Cluster Qualification, Semiconductor International, September 2006, 7. W. Conley, The Capability of a 1.3NA stepper using 3D EMF Mask Simulations, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, N. Yamamoto, et al, Mask Topography Effect with Polarization at Hyper NA, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, P. Leray, S. Cheng, Immersion Challenges, KLA-Tencor Future Technology Conference, Grenoble, October S. Nagahara, et al, Immersion Effects on Lithography System Performance, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, I. Pollentier, M. Ercken, P. Foubert, and S. Y. Cheng, Resist profile control in immersion lithography using scatterometry measurements, Optical Microlithography XIX, Proc. of SPIE Vol. 5754, R. R. Dammel, G. Pawlowski, A. Romano, F. M. Houlihan,W-K Kim, R. Sakamuri, and D. Abdallah, Resist Component Leaching in 193nm Immersion Lithography, Advances in Resist Technology and Processing XXII, Proc. of SPIE Vol. 5753, S. Kishimura, R. Gronheid, M. Ercken, M. Maenhoudt, T. Matsuo, M. Endo, and M. Sasago, Impact of Water and Topcoats on Lithographic Performance in 193nm Immersion Lithography, Advances in Resist Technology and Processing XXII, Proc. of SPIE Vol. 5753, K. Ronse, Continued scaling in integrated circuits - trends in lithography and requirements from device/circuit perspective, Microlithography, SPIE, N. Stepanenko, et al, Topcoat or no topcoat for immersion lithography? Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, A. Otoguro, et al, Analysis of 193nm immersion specific defects, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, B. Streefkerk, et al, A Dive into Clear Water: Immersion Defect Capabilities, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, M. D. Levenson, Immersion Symposium report: Industry optimistic about commercial success, Wafer News, 17 October, 2006, K. M. Monahan, Enabling Double Patterning at the 32nm Node, IEEE International Symposium on Semiconductor Manufacturing, K. Shiraishi, et al, Basic Studies of Overlay Performance on Immersion Lithography Tool, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, S. Kanna, et al, Materials and Process Parameters on ArF Immersion Defectivity Study, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, G. Wallraff, et al, The Effect of Photoresist/Topcoat Properties on Defect Formation in Immersion Lithography, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, M. Carcasi, et al, Defectivity Reduction by Optimization of 193nm Immersion Lithography using an Interfaced Exposure - Track System, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, T. Tomita, et al, An Investigation on Defect-generation Conditions in Immersion Lithography, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, M. Kocsis, et al, Immersion Specific Defect Mechanisms: Findings and Recommendations for their Control, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, I. Malik, Immersion Lithography Defectivity and its Improvements, KLA-Tencor Yield Management Seminar, Singapore, G. Wallraff, et al, The Role of Evaporation and Surface Properties in Defect Formation in Immersion Lithography (How can we engineer new surfaces for immersion lithography?), International Symposium on Immersion Lithography, Kyoto, Japan, October, C. Robinson; D. Corliss; S. Ramaswamy, Immersion Lithography Defect Learning, International Symposium for Immersion Lithography, Kyoto, Japan, October, C. Perry-Sullivan, et al, Immersion Lithography Defect Detection using Broadband Brightfield Inspection, KLA-Tencor YMS Magazine, Winter D. Patel, et al, Defect Metrology Challenges for the 45nm Technology Node and Beyond, Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE Vol. 6152, F. Burkeen, et al, Visualizing the wafer s edge, KLA-Tencor YMS Magazine Winter M. Randall, et al, A universal process development methodology for complete residues from 300mm wafer edge bevel, Advances in Resist Technology and Processing XXIII, Proc. of SPIE Vol. 6153, I. Peterson; N. Khasgiwale, Cost- and Sensitivity- Optimized Defect Photo Cell Monitor, KLA-Tencor Yield Management Seminar, San Francisco, F. Holsteyns, et al, The use of unpatterned wafer inspection for immersion lithography defectivity studies, Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE Vol. 6152, K. Nakano, S. Owa, I. Malik, T. Yamamoto, S. Nag, Analysis and improvement of defectivity in immersion lithography, Optical Microlithography XIX, Proc. of SPIE Vol. 6154, B. Schulz, et al In-chip overlay metrology in 90nm production, IEEE International Symposium on Semiconductor Manufacturing, Y. Ishii, et al, Improving Scanner Productivity and Control through Innovative Connectivity Application, Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE Vol. 6152, K. Hung, et al, Scatterometry Measurements of Line End Shortening Structures for Focus-Exposure Monitoring, Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE Vol. 6152, M. Cusacovich, et al, An Integrated Approach to the Determination of a Manufacturable Process Window in Advanced Microlithography, Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE Vol. 6152, T. Fujiwara, et al, Wafer Management between Coat/Developer Track and Immersion Lithography Tool, Optical Microlithography XIX, Proc. of SPIE Vol. 6154,

18 Defect Management Visualizing the Wafer s Edge Frank Burkeen, Srini Vedula, Steven Meeks KLA-Tencor Corporation Silicon wafers have edges, where the wafer ends and something else a wafer stage, a chuck, or a robot arm begins. Within this critical edge zone, thermal cycling and plasma exposure can degrade film adhesion, robots can break off particles from the edge bevel, and wet processes can cause delamination. Particles from all of these sources can contaminate devices across the wafer surface, or can migrate to the lithography tool s exposure stage. New, highproductivity edge inspection technology allows chipmakers to find defect sites at the wafer edge and correlate them with yield results. Process specifications have long recognized an edge exclusion zone, in which uniformity specifications are not necessarily met and process performance is not guaranteed. Die which encroach into the exclusion zone are not expected to function. Yet the existence of an edge exclusion zone implies that all other die on the wafer should be fine, whether they are near the edge or not. In reality, though, what happens on the edge can easily affect the rest of the wafer. The transition from a planar surface to the wafer bevel and apex regions creates a high-stress area susceptible to film delamination. Normalized Yield Widespread Edge Yield Issue (data averaged across 10 leading-edge fabs) Wafer Radius (cm) Figure 1: A benchmark study of ten fabs (averaged in the graph) by KLA-Tencor found that yield in the near-edge region was as much as 50% less than yield in the center region. More than half of near-edge yield loss was due to defects. During process integration, interfacial stress may cause films to not adhere properly to the underlying layers in these regions. Wafer handling robots and other mechanical contact can chip films coating the edge bevel, breaking off particles. Thermal cycling and contamination sources can degrade film adhesion, causing blisters along the edge. If these blisters pop during handling, more particles result. Wet processes can erode edge films like waves attacking a coastline, causing delamination and generating more particles. Immersion lithography in particular drags a fluid bubble across the wafer at high speed, generating a virtual tsunami at the edge of the wafer. Particles from all of these sources can contaminate the device surface, or can migrate to the lithography tool s exposure stage. A benchmark study of ten fabs found that yield in the near-edge region was as much as 50% less than yield in the center region (Figure 1). More than half of near-edge yield loss was due to defects, rather than parametric variation. Edge defectivity is not unique to 300mm wafers; the benchmark study found near-edge yield loss on both 200mm and 300mm wafers. However, the larger wafer size places more die near the edge. A 10mm-wide annulus at the edge of a 300mm wafer has an area of about 9110mm 2, while one at the edge of a 200mm wafer has about two-thirds the area, encompassing about 5970mm 2. In fact, the 10mm ring at the edge of the 300mm wafer accounts for about 13% of the total wafer area, and about 23% of the new area gained by the larger wafer size. Clearly, high yield loss in the near-edge region can have a significant impact on overall wafer yield and fab profit. In a typical situation, the edge zone might contain 150 die and suffer 30% excess yield loss. Valuing the lost dies at US $5.00 each and assuming 10,000 wafer starts per week, edge defects could be responsible for as much as US $2.5M in lost profit per week. Spring 2007 Yield Management Solutions

19 Defect Management Defects are There, But How to Monitor Them? Until recently, edge defect inspection focused on chips, cracks, and other kinds of structural damage to the wafer itself. Though catching these flaws at incoming inspection is important, structural damage is rare once wafers enter the production line. Process-induced edge defects often involve interactions among several process steps. For example, an area of poor adhesion might originate with a water spot or other residue, but the actual delamination might be caused by thermal expansion and contraction of the film during subsequent processing. Once a blister exists, further thermal expansion can allow it to grow, or mechanical contact can crush it. All of these effects are more commonly seen in the BEOL interconnect process, after several metal and dielectric layers have accumulated on the edge bevel. For effective process control, fabs must both identify edge defects and sort them into the appropriate defect types. Both tasks are especially challenging because the edge region is very noisy. It may have varying thicknesses of several different films and contain numerous chips and scratches due to normal handling. While pre-production wafer inspection is likely to find only a handful of defects, applying the same techniques to a BEOL product wafer might find hundreds, or even thousands of abnormalities. SEM review is slow, can typically extend only up to the upper bevel region and large scale review is not economically feasible (Figure 2). Film delamination on top bevel Figure 2: Manual review, with SEM or optical microscopes, is slow with virtually no possibility of scaling into production. Some systems attempt to apply existing inspection technologies to edge defect detection. One approach relies on laser scattering, currently used for inspection of incoming wafers and unpatterned particle monitors. While the technology works well for these applications, the technology is not sensitive to most IC manufacturing defects related to films, such as delamination, flakes, and residues. Figure 3: CCD image With CCD-based technology and current optics, the shallow depth of focus makes high resolution imaging difficult. Brightfield and darkfield imaging are important tools for patterned wafer inspection and defect classification, and have also been applied to edge defect detection. Yet this technology also faces severe challenges. Patterned wafers have moderate topography, but the surface is still essentially planar. Depthof-focus requirements are moderate, with no more than a few microns separating the tallest peaks from the deepest trenches. The edge region, in contrast, includes the full 3mm width of the edge exclusion zone. Defects can appear on the top surface Most existing inspection technologies are not sensitive to edge defects, such as delamination, flakes and residues. of the wafer, the top bevel, the apex of the bevel, the bottom bevel, or the bottom surface of the wafer. A single CCD camera focused on the edge cannot hope to keep the entire region in focus at the resolution needed for micron-scale defect imaging (Figure 3). Without a clear image, accurate defect detection and classification is impossible. Another compromise to address the DOF challenge results in imaging at lower magnifications, resulting in a resolution compromise. Because CCD imaging depends on what is essentially a microscope, with discrete optics and a limited field of view, designing a system that can image the whole near-edge region is difficult. The imaging camera itself is fixed in place, adding another requirement for multiple cameras for wider coverage an option not practical for production-level monitoring. Finally, defect imaging fidelity (color, shape, etc.) is impacted by the viewing angle (angle of incidence). Detection algorithms based on color and contrast have trouble separating actual defects from normal edge variations. 19

20 Defect Management Specula (reflected light) Phase Shift Frontside Defects (darkfield) Topography Scattered Light Laser Diode Polarizer Figure 4: Optical surface analysis (OSA) offers the fast scan, high data rate, multi-channel imaging capability necessary for accurate detection and classification of the widest range of edge defect types. Scatter Specular Topography Phase Phase Image best indicates popped vs. un-popped blisters Figure 5: Wafer apex blisters (VisEdge images) With its multi-sensor Optical Surface Analyzer technology, VisEdge provides manufacturers with simultaneous independent measurement of phase shift, reflected light, topographic and scattered light. Top Bevel Apex Top Bevel Apex A New Approach KLA-Tencor s new edge inspection platform, utilizing optical surface analysis (OSA) technology, addresses these challenges with a revolutionary multi-sensor approach. This technology is already well established in the hard disk drive and compound semiconductor markets. The tool works by imaging light emitted from the edge region (Figure 4). The laser source traces a beam of polarized light over the wafer edge from top surface to bottom surface. Detectors capture both scattered and reflected light, measuring scattering intensity, polarization, beam deflection, and phase contrast. Each of the four resulting images supplies different information (Figure 5). The reflected light and phase channels are most sensitive to film defect sources, such as delamination, flakes, and residues. The scattered light channel is most sensitive to particle sources, chips, and cracks. Together, the images give a complete picture of the wafer edge. Comparing different images from the same region can help differentiate between delamination, particles, and other defects. Though the imaging data is helpful in itself, automated defect detection and classification makes it even more useful, giving a defect map that is fully comparable to the maps provided by wafer die inspection tools. Process engineers can trace die loss to its source at the wafer edge in much the same way that they would attack any other yield problem. Integral Part of a Complete Yield Solution Wafer maps and full die inspection gave manufacturers the ability to see clusters of defects, separating random particles from defects clearly attributable to process problems. Partial die inspection has helped manufacturers track defects originating near the edge exclusion zone, warning of potential problems before they could spread to product die. Edge inspection completes the package, allowing manufacturers to find defect sites at the wafer edge itself and correlate them with yield results (Figure 6). In order to recoup their investment in 300mm wafer manufacturing, fabs must maximize the yield from the new wafer area that the larger wafers provide. Much of that area lies near the wafer s edge, in a region known to suffer from poor yield. Better detection and classification of edge defects is essential to overall wafer yield and, ultimately, fab productivity. The proven technology of KLA-Tencor s edge inspection system supports rapid detection and accurate classification of these critical defects. Apex Defects Edge Source for Front Surface Defects Acknowledgement The authors would like to thank Katherine Derbyshire for her assistance with this paper. Figure 6: VisEdge offers a better understanding of how edge defects are correlated to surface defects, improving total die yield. 20 Spring 2007 Yield Management Solutions

21 Benvenuto! ASMC 2007 Moves to Italy 18th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference June 11-12, 2007 Grand Hotel Bristol Stresa, Italy ASMC, a leading international technical conference on semiconductor manufacturing processing, has a new home for Cosponsored by SEMI and IEEE,ASMC 2007 will be held June at the Grand Hotel Bristol in the Northern Italian lake-side town of Stresa. Semiconductor professionals from industry, academia and consortiums will learn the latest practical applications of advanced manufacturing strategies and all methodologies used to achieve manufacturing excellence. Real solutions, direct from the fab Papers will address these and other topics: Advanced Metrology Advanced Processes and Materials Advanced Process Control Analog, High-Power and High-Voltage Contamination-Free Manufacturing (CFM) Cost Reduction, Equipment Reliability and Productivity Data Management and Data Mining Tools Defect Inspection and Reduction Design for Manufacturability (DFM) Factory Automation and Factory Dynamics Industrial Engineering Lithography Advances and Challenges Time to Market Yield Enhancement and Modeling 300mm Prime Initiative Introducing beautiful Stresa The charming resort town of Stresa is located on Lago Maggiore, the second-largest lake in Italy, which stretches between Lombardy and Piemonte into the Alps. The region is a world-class meeting destination. The four-star Grand Hotel Bristol overlooks the lake.two Milan airports, Malpensa International and Linate, serve the region, which is also accessible by train and the Autostrad. Mark your calendars and join us in beautiful Stresa, Italy. For more information and agenda updates visit

22 Defect Management Broadband Brightfield Inspection Enables Advanced Immersion Lithography Defect Detection Catherine Perry-Sullivan, Erwan Le Roy, Steven R. Lange, Irfan Malik, Avinash Yerabaka, Adrian Wilson, Mark Shirey, Becky Pinto KLA-Tencor Corporation The materials employed in the immersion litho cell vary widely over different layers, products and fabs. A highly flexible brightfield inspector ensures maximum sensitivity over a broad range of immersion litho materials and defect types. Immersion lithography is a key enabling technology for 65nm and 45nm device patterning. However, the introduction of a fluid between the wafer and scanner has led to new defectivity issues related to the intricate interactions between multiple process parameters including the resist, topcoat, scanner and fluid. 1 While some immersion-specific defects, such as bubbles, have been successfully controlled or eliminated, immersion litho defect reduction remains a major challenge for chipmakers. 2,3,4,5 Long the standard for patterned wafer litho/photo-cell monitoring, 6,7 high-resolution broadband brightfield inspectors offer unique features that benefit immersion litho defect detection, monitoring and control. These features include a high numerical aperture (NA), a tunable illuminator covering DUV, UV and visible wavelengths, selectable optical apertures, and advanced automatic defect classification capability. This paper presents experimental and theoretical data on several immersion litho defects and layers, showing how tunable broadband illumination and selectable optical apertures uniquely fulfill the resolution and noise suppression requirements for immersion litho defect detection. Several use cases demonstrate how broadband brightfield inspectors, with features such as automatic defect classification, help chipmakers solve immersion litho defect issues and successfully implement immersion lithography in production. These optical properties vary with differing materials and defect types, and are also a function of the illumination wavelength and optical apertures. As the combination of materials employed in the immersion litho cell varies widely over different layers, products and fabs, the use of a brightfield inspector with a tunable broadband illuminator and selectable apertures ensures maximum sensitivity over a broad range of immersion litho materials and defect types. This section presents theoretical modeling data showing the wavelength and aperture dependence of two immersion litho defects. Additional simulation data is presented which demonstrates how small changes in material thicknesses in the resist stack can dramatically affect the optimal wavelength required for maximum defect sensitivity. Simulation Model Simulation studies were performed for two immersion litho defects bridging and line thinning. Immersion litho bridging defects result in blocked pattern between adjacent lines and can be caused by water marks, stains or particles. Line Immersion Lithography Defects: Simulation Studies Inspection tool sensitivity can be described as being directly proportional to defect signal and inversely proportional to wafer noise. Maximizing the signal-to-noise ratio or, the contrast between a defect and its surroundings is necessary for the successful detection of critical immersion litho defects. For brightfield inspection, the optical properties of the defect and the surrounding material determine the relative contrast. 22 Figure 1: Example of bridging (left) and line thinning (right) defects. Spring 2007 Yield Management Solutions

23 Defect Management thinning is a defect specific to immersion lithography which results in a deformation of the lines critical dimension. Example SEM images of bridging and line thinning defects are shown in figure 1. Cross-section Top view 45nm Line-space Resist SiON Gate Oxide SiN Poly Si Si 100nm 230nm 27nm 50nm 140nm 23nm Figure 2: Cross-section and top view of the gate ADI layer used for the simulations. The pattern consists of 45nm resist lines on a SiON BARC. The bridging defect (bottom left) is 100nm long. The line thinning defect (bottom right) is 100nm long and 23nm wide. Signal-to-Noise Ratio Wavelength (nm) a. Bridging Signal-to-Noise Ratio Wavelength (nm) b. Line Thinning BF VIB ECP BF VIB ECP Figure 3: Theoretical wavelength dependence of the signal-to-noise of a bridging defect (a) and a line thinning defect (b) on a 45nm gate ADI layer. Results for three different optical apertures are shown (BF, VIB and ECP). The optimal signal-to-noise depends on both the illumination wavelength and optical aperture. These data indicate that both defect types would exhibit sufficient signal-to-noise for simultaneous defect capture by using a DUV illumination source ( nm) with the ECP aperture. A gate ADI process layer was used in the modeling studies. A cross-section and top view of this layer are shown in figure 2. The pattern consists of 45nm resist lines on a SiON bottom anti-reflective coating (BARC). The bridging defect used in the simulations is 100nm long, while the line thinning defect is 100nm long and 23nm wide. Included in the model were two noise sources: line edge roughness and color variation due to resist thickness variations. For both defects, the theoretical signal-to-noise ratio was calculated. This was done by first calculating the defect s gray level signal, that is, the difference in gray level between an image with the defect and an image without the defect. Similarly, the noise gray level value was found by taking the difference in gray level between an image with line edge roughness and color variation noise and an image without any noise sources. The signal-to-noise was then calculated by taking the ratio of the defect gray level signal and the noise gray level value. The simulations looked at both the wavelength dependence of the signal-to-noise, and the effect of different optical apertures on the signal-to-noise ratio. Modeling Results The theoretical wavelength dependence of the signal-tonoise of the bridging and line thinning defects is shown in figure 3. Simulations were performed using three different optical apertures: (1) BF, a standard brightfield aperture; (2) ECP (Edge Contrast Plus), an illumination technique which allows high-angle illumination; and, (3) VIB (Varied Illumination Brightfield), an illumination technique which allows low-angle illumination. Figure 3a shows that the optimal wavelength for the bridging defect depends strongly on the aperture utilized. The highest signal-to-noise ratios are obtained using either the ECP aperture with an illumination spectrum near 270nm, or the brightfield aperture with an illumination spectrum near 230nm. The wavelength dependence of the signal-to-noise for the line thinning defect (Figure 3b) is similar for the three apertures, with the highest signal-to-noise obtained using the VIB aperture with an illumination spectrum near 290nm. These simulation data indicate that for this 45nm gate ADI immersion litho layer with line edge roughness and color noise, sufficient signal-to-noise for simultaneous detection of both defects would be obtained using the ECP aperture with a DUV illumination source covering nm wavelengths. While these modeling data suggest that a brightfield inspector with a tunable broadband illumination source and selectable apertures is necessary for detection of different defect types on an immersion litho layer, the following section demonstrates that these brightfield attributes are required to address the optical property variations exhibited by different resist stacks. Materials Wavelength Dependence The compositions and thicknesses of BARC, top anti-reflective coating (TARC), resist and other materials used in immersion lithography can vary dramatically over different process levels, products and fabs. These varying resist stacks exhibit different physical and optical properties. Modeling data from two 23

24 Defect Management different resist/barc stacks demonstrate how small changes in stack composition can result in widely varying optical properties. 8 These simulations were performed for a bridging defect on a 90nm line-space array. Both material stacks were based on fab prescriptions for 193nm litho and cross-sections are shown in figure 4. Stack A consisted of 230nm of resist on 27nm of a SiON BARC, while Stack B had 150nm of resist on 45nm of BARC. The theoretical wavelength dependence of the brightfield gray-level signal for the bridging defect on these two stacks is shown in figure 4. The optimal wavelength for detection of the bridging defect depends strongly on the resist/barc stack composition. The highest defect signal for Stack A is obtained with visible light in the nm range, while the highest defect signal for Stack B is obtained with DUV light in the nm range. Future modeling studies will include a closer investigation of the wavelength dependence of specific immersion litho stacks and materials at smaller design rules. Immersion Lithography Defects: Experimental Data Experimental signal-to-noise ratios from defects on two immersion litho wafers are presented below. Results from one wafer focus on the wavelength dependence of the signal-to-noise ratios, while data from the second wafer examine the effect of different optical apertures on the signal-to-noise. Metal ADI Wafer The following studies were done on a metal ADI wafer patterned using an immersion scanner. This is a flash device with ~55nm design rule. The experimental data on this wafer were collected using a broadband brightfield inspector with a tunable illumination source and selectable apertures. These data include signal-to-noise ratios calculated from TDI sensor difference images. A difference image highlights the signal and noise characteristics of a defect and is the image that nm 27nm BF GL Signal Stack A Resist Si SiON Wavelength (nm) Stack B Resist 150nm 45nm Stack B Stack A Figure 4: Modeling data shows the wavelength dependence of the brightfield gray-level signal of a bridging defect on a 90nm line-space array for two different litho stacks. Stack A (orange line; 27nm of BARC topped with 230nm of resist) exhibits the strongest defect signal in the visible wavelength range ( nm), while Stack B (green line; 45nm of BARC topped with 150nm of resist) has the strongest defect signal in the DUV wavelength range ( nm). Si results from subtracting the raw sensor image of a reference die from the raw sensor image of a defective die. Figure 5 shows examples of TDI sensor difference images for a bridging defect on this wafer. These difference images were taken using three different illumination wavelength ranges deepband, broadband and I-line with the standard brightfield aperture. Deepband covers a range of DUV wavelengths, broadband covers DUV and UV wavelengths, and I-line centers around 365nm UV wavelength. The number under each image is the signal-to-noise ratio of the defect, calculated from the difference image by measuring the signal of the defect and the noise of the surrounding pattern area. These data show deepband as the best illumination source for noise suppression and defect detection. Qualitatively, the area surrounding the defect Signal-to-Noise Ratio Deepband Broadband I-Line 25/5 = /4 = /11 = 0.82 Figure 5: TDI sensor difference images of a bridging immersion litho defect from a ~55nm metal ADI layer. Images were collected with a 2800 broadband brightfield inspector using different wavelength ranges. These images show that deepband illumination covering a range of DUV wavelengths is best for suppressing noise and maximizing the defect s signal-to-noise ratio. Bridge - 1 Bridge - 2 Small Particle G-Line GHI-Lines I-Line Midband Blueband Deepband Broadband Figure 6: Signal-to-noise ratios of three immersion litho defects (two bridges and one small particle) on a ~55nm metal ADI wafer calculated from TDI sensor difference images collected using a 2800 broadband brightfield inspector using different wavelength bands and the standard brightfield aperture. While a defect will not be detected unless its signalto-noise value is above 1.0 (red horizontal line), it is sufficiently above the noise floor for consistent detection when its signal-to-noise value is above 1.3 (yellow horizontal line). These data show that deepband illumination covering a range of DUV wavelengths is best for maximizing the signal-to-noise ratio for all three defects. Spring 2007 Yield Management Solutions

25 Defect Management Signal-to-Noise Ratio appears quiet, while quantitatively, the highest signal-tonoise ratio is obtained with deepband illumination. Figure 6 shows the signal-to-noise ratios for three different immersion litho defects from this wafer, collected using seven different illumination bands with the standard brightfield aperture. Deepband, blueband and midband all cover different DUV wavelength ranges while broadband covers both DUV and UV wavelengths. G-line centers around 436nm visible wavelength, I-line centers on 365nm UV wavelength, and GHI-line covers a range of UV and visible wavelengths. These data show that G-line and I-line illuminations provide poor signal-to-noise for two of the three defects. Likewise, while the signal-to-noise ratio is very high for one bridging defect using midband and blueband, these illumination ranges result in marginal signal-to-noise ratios for the other two defects. Broadband illumination provides adequate signal-to-noise for all three defects. However, deepband proves to be the best illumination source for noise suppression and defect detection on this particular wafer as all three defects have high signal-to-noise ratios. These data demonstrate how the signal-to-noise ratios are strongly affected by the wavelength range selected for illumination. CD Variation - 1 CD Variation - 2 Protrusion Residue Type A Residue Type B Broadband HPS Broadband VPS Broadband HPEC Figure 7: Signal-to-noise ratios of five immersion litho defects from a ~45nm PCM wafer calculated from TDI sensor difference images. A 2800 broadband brightfield inspector using broadband DUV illumination and three different apertures was used to collect the images. The yellow horizontal line indicates the signal-to-noise value (1.3) that is sufficiently above the noise floor for consistent defect detection, while the red horizontal line indicates the absolute minimum value (1.0) necessary for detection. These data show that the HPS aperture which suppresses horizontal pattern edges is best for maximizing the signal-to-noise ratio for all five defects. Defect Density (/cm 2 ) bridge gross bridging PCM Wafer These experimental data were collected on a PCM (photo-cell monitor; resist on silicon) wafer patterned using an immersion scanner. This is a flash device with ~45nm design rule. The data on this wafer were collected using a broadband brightfield inspector with a tunable illumination source and selectable apertures, and include signal-to-noise ratios calculated from TDI sensor difference images for five different defects. The immersion defect types studied include: CD variation (widening of the line), protrusion, and two types of residues. These data were collected using broadband DUV illumination with three different apertures. The apertures utilized include two which suppress horizontal or vertical pattern edges (HPS and VPS), and HPEC (Higher Performance Edge Contrast) which is an optical technique that allows darkfield imaging. The signalto-noise ratios are shown in figure 7. These data clearly show that the HPS aperture provides the highest signal-to-noise ratio for all the immersion litho defects on this particular wafer, and is the best aperture to utilize for maximum defect sensitivity. While the experimental data in the previous section demonstrated the value of a tunable illumination source for minimizing noise and maximizing defect detection, these data demonstrate how different apertures can affect the resulting signal-to-noise ratios. In order to obtain maximum defect sensitivity on a variety of immersion litho layers and defects, a brightfield inspector requires the flexibility provided by both a tunable broadband illumination source and selectable apertures. Immersion Lithography Defectivity: Use Cases Two of the following use cases compare the defect detection capabilities of DUV broadband brightfield and UV broadband brightfield inspectors on immersion litho wafers. The third use case focuses on the value of automatic defect classification for immersion litho defect monitoring. protrusion 2351 & 2800, Dry & Wet between line DETAILED CLASSIFICATION embedded small particle 2351 Dry Wet Dry Wet 2800 TOTAL COUNT TOTAL 2351 Dry 2351 Wet 2800 Dry 2800 Wet Figure 8: Defect detection comparison between the 2800 DUV broadband brightfield inspector and the 2351 UV broadband brightfield inspector on a 90nm array immersion litho wafer. 9 The 2800 shows 2x to 4x higher defect capture and unique capture of bridging defects. 25

26 Defect Management Scanner Qualification One scanner manufacturer recently studied defectivity levels obtained with its immersion scanner under different process conditions. 9 As part of these studies, the immersion defect detection capability of a DUV broadband brightfield inspector was compared with a UV broadband brightfield inspector on 90nm array devices. While no defects specific to the immersion process were detected, the DUV broadband brightfield inspector did detect unique bridging defects and provided 2x (dry) to 4x (wet) higher defect capture than the UV broadband brightfield inspector (Figure 8). The DUV broadband brightfield inspector also captured 45nm defects a 2x improvement in the minimum defect size detected by the UV broadband brightfield inspector. The improved sensitivity and defect capture demonstrated by the DUV broadband brightfield inspector prove its necessity for defect detection and control on immersion litho layers. Immersion Lithography Integration One semiconductor manufacturer implemented a comprehensive defect monitoring strategy involving both unpatterned and patterned wafer inspection in order to accelerate immersion lithography development and production integration. 10 As part of its investigation of patterned wafer inspectors, it compared the immersion defect detection performance of a DUV broadband brightfield inspector with a UV broadband Relative NRnd Defect Counts Repeater Atten w/µ-bridge Attrenuated Attenuated NV Bubble High Power BB-DUV BB-UV Figure 9: Defect Pareto comparing the immersion litho defect detection performance of the 2800 DUV broadband brightfield inspector and the 2365 UV broadband brightfield inspector on a resist imaging stack on bare silicon. 10 The 2800 shows much higher defect capture, and uniquely captures defect types A (protrusion repeater) and D (attenuated). Extra Pattern Collapsed Line Embedded brightfield inspector on resist imaging stacks on bare silicon. The resulting Pareto and example images of defect types are shown in figure 9. This Pareto shows that the DUV broadband brightfield inspector provided higher capture of all defect types when compared to the UV broadband brightfield inspector. Though they are grouped with similar defect types in the Pareto, the chipmaker indicated that protrusion repeaters (defect type A in figure 9) and attenuated defects (type D) were uniquely captured by the DUV broadband brightfield inspector. The chipmaker considered the attenuated defect to be a key immersion litho defect type. Overall, this chipmaker found that the DUV broadband brightfield inspector provided higher total defect capture, and was better at capturing smaller and more subtle immersion litho defects. These results show that the DUV broadband brightfield inspector is a key tool for the identification and characterization of immersion-specific defects. For this chipmaker, the implementation of a comprehensive defect monitoring strategy, including a DUV broadband brightfield inspector, resulted in the successful production of 45nm test lots in the immersion cluster at defect densities equivalent to those obtained with dry lithography. Automatic Defect Classification As immersion lithography is integrated in production, chipmakers must quickly isolate and identify specific defectivity issues. As part of this process, it is important that an inspector not only capture the critical immersion litho defects, but also provide automated review sample shaping to filter nuisance defects and bin defects of interest. Integrated automatic defect classification allows chipmakers to work on process fixes in a logical order first addressing the most critical immersion litho defect types, then tackling defects with less yield impact. For one immersion litho engineering team, it was difficult to diagnose and fix critical immersion litho process problems based on the high total number of defects reported on each wafer. The value of automated defect classification was demonstrated using a DUV broadband brightfield inspector which utilizes proprietary information from the detection algorithms and optics to bin defects by specific attributes. This automated binning capability reduced time to critical information by removing line roughness nuisance defects from the defect population and by binning the remaining defects by type particularly, separating protrusions from other real defects such as bridging and stringers (Figure 10). This binning capability allowed the litho engineer to diagnose immersion process problems associated with major bridges and stringers first, before moving on to process issues related to the more subtle protrusion defects. Utilizing an inspector with automatic defect classification capability reduces time to meaningful results and assures that resources are allocated towards fixing the most significant immersion litho yield issues. 26 Spring 2007 Yield Management Solutions

27 Defect Management Bin 40 Bin 80 Bin 90 Stringer Bridge Protrusion Line Roughness (Nuisance) Segment Multi+0... Magnitude Magnitude < < > < < > Figure 10: The 2800 DUV broadband brightfield inspector provides advanced automatic defect classification capability with inline Defect Organizer TM (ido TM ). ido utilizes proprietary information to bin defects by specific attributes and includes an intuitive graphic interface. In this example, ido removed line roughness nuisance from the defect population, and binned the remaining defects by type. This allowed the immersion litho engineers to focus on yield issues related to the stringer and bridging defect types (bin 40) before moving on to the less-critical protrusion defects (bin 80). Conclusion As immersion scanners are integrated into 65nm and 45nm production, chipmakers face new and complex challenges associated with immersion litho defectivity. As the experimental and theoretical data in this paper demonstrated, a broadband brightfield inspector with a tunable illumination source and selectable apertures is required for reducing common litho noise sources, maximizing the contrast of a range of immersion litho defects, and handling the optical property variations resulting from different stack compositions and materials. Future modeling studies will further explore the wavelength and aperture dependence of varying immersion resist stacks on 45nm design rule devices. Use cases demonstrated the immersion litho detection capability of a DUV broadband brightfield inspector for both scanner qualification and immersion litho production integration. Additionally, the use of automatic defect classification reduced time to results and focused resources on the most critical immersion litho defect issues. By providing the flexibility required to maximize defect sensitivity on a variety of immersion litho layers and materials, broadband brightfield inspectors are well positioned to address the immersion litho defectivity issues associated with production integration. References 1. I. Malik and B. Pinto, Immersion Changes Litho Cluster Qualification, Semiconductor International, September L. Peters, Defectivity Issues Drive Immersion Lithography, Semiconductor International, April S. Warrick, D. Cruau, A. Mauri, V. Farys and S. Gaugiran, A defectivity checkpoint for immersion lithography, Microlithography World, August I. Malik and S. Nag, Defectivity Challenges in Immersion Lithography for sub 90nm Technologies, Lithography Users Forum, February M. David Levenson, Immersion Symposium report: Industry optimistic about commercial success, Solid State Technology, October S. Ashkenaz, I. Peterson, P. Marella, M. Merrill, L. Cheung, A. Sethuraman, T. DiBiase, M. Stoller, and L. Breaux, Defect Management for 300mm and 130nm Technologies, Part 2: Effective Defect Management in the Lithography Cell, Yield Management Solutions, Fall I. Peterson, L. Breaux, A. Cross and M. von den Hoff, Successful demonstration of a comprehensive lithography defect monitoring strategy, SPIE Vol. 5041, pp , S. Lange, B. Pinto and J. Fernandez, Advantages of Broadband Illumination for Critical Defect Capture at the 65nm Node and Below, Electronics Journal (Japanese), July K. Nakano, S. Nagaoka, S. Owa, T. Yamamoto and I. Malik, Immersion defectivity analysis using volume production immersion exposure tool, 3rd International Symposium on Immersion Lithography, October C. Robinson, D. Corliss, S. Ramaswamy, Immersion Lithography Defect Learning, 3rd International Symposium on Immersion Lithography, October

28 Defect Management New Inspection Technology for 45nm Wafers Becky Pinto, Jason Saito, William Shen, Lisa Cheung, Albert Wang KLA-Tencor Corporation A new unpatterned inspection system captures all intrinsic, polishing and fall-on defects, then separates them into re-workable versus scrap defect types. In the past, the role of the substrate in integrated circuit manufacturing was primarily one of physical support for the devices built upon it. The substrate had to be flat and relatively free of particles, flakes and residues in active areas so that these defects were not incorporated into the structure of the transistor. The substrate s crystallographic properties, or equivalently its electronic structure, can be engineered to play an active role in enhancing carrier mobility or decreasing leakage current. Substrate quality and uniformity have become critical to ensuring the best possible device performance. Not only are wafer flatness, microroughness and particle count critical, but crystallographic defects also need to be detected and distinguished from particles and other fall-on defects. IC manufacturers typically have zero tolerance for intrinsic (grown-in) defects because they can impede or kill the device. On the other hand, particles or residues can often be removed Wide by re-cleaning or re-polishing the wafer. The ability to know which wafers have to be scrapped, and which can be re-worked, is of tremendous economic and technical advantage to both wafer and IC manufacturers. A new evolution of the Surfscan SP2 system, the Surfscan SP2 XP, supports surface and near-surface defectivity requirements for wafers used for 45nm device manufacturing. For prime wafers, a previously undifferentiated category of defects known as large light point defects (LLPDs) can now be separated into reworkable defects and fatal process-induced defects. Scratch detection has also improved for prime wafers. For silicon-on-insulator (SOI) wafers, the new technology improves the ability to distinguish cleanable particles from detrimental voids. Finally, device-killing epi stacking faults (ESFs) can now be separated from more benign particles and flakes on epitaxial silicon ( epi ) wafers. Altogether, these advancements lead to fewer scrapped wafers for wafer manufacturers, and improved ability for device manufacturers to systematically build high performance devices at high yield. Narrow Rotating Wafer Scan Bright Field DIC Normal Illumination Oblique Illumination New Wafer Inspection Technology A reliable way of detecting crystallographic defects on epi, prime and SOI wafers and separating them from fall-on defects is now available on the Surfscan SP2 XP. These capabilities are driven by new subsystem technology, including an extended dynamic range, an integrated differential interference contrast (DIC) channel, and a new ability to scan each wafer using both oblique- and normal-incidence scans without reloading the wafer. New algorithms compare scattering intensities from different available channels of data to deliver defect binning with substantially higher accuracy and purity. 28 Figure 1: Optical design of Surfscan SP2 XP system. While the wafer spins below, the darkfield subsystem uses a 355nm laser to illuminate a spot on the wafer from a normal or oblique angle of incidence. Darkfield collectors span either narrow or wide solid angles. A separate, normalincidence brightfield DIC channel operates simultaneously with either of the darkfield channels, and uses a 632nm laser. Surfscan Optical Design Surfscan SPx wafer inspection systems work by rapidly scanning a laser spot in a spiral pattern across the surface of the wafer. Scattered light is collected in large solid-angle collectors, which integrate the signal to detect even small defects (Figure 1). Because the shape, size and material of the defect Spring 2007 Yield Management Solutions

29 Defect Management and the wafer substrate affect the way the defect scatters light, normal and oblique incidence angles, narrow and wide collection channels, and selectable polarizations provide flexibility to capture all defect types. Brightfield Differential Interference Contrast (DIC) Channel While all Surfscan SPx systems provide darkfield inspection, as described above, the new system incorporates a brightfield channel as well. (Darkfield detection relies on light scattered out of the direct beam, while brightfield detection makes use of the direct beam.) The brightfield channel not only provides another means of detecting challenging defect types, it also includes a DIC capability. 1 This technique makes use of the phase of the laser beam to distinguish concave from convex defects. The DIC signal polarity is useful as a descriptor for defect classification. Dual-Incidence Scans and Throughput Increase One lot of wafers may contain a number of different defect types: some are captured more readily using oblique-incidence darkfield, some using normal-incidence darkfield, and some using brightfield. For this reason, the new Surfscan SP2 XP can perform two successive scans on the same wafer, covering both oblique and normal incidence, without removing the wafer from the system. The brightfield channel operates simultaneously with either or both scans. As a result, data are collected for five optical configurations: Oblique-Narrow (ON), Oblique-Wide (OW), Normal-Narrow (NN), Normal-Wide (NW), and Brightfield (BF). New algorithms allow sizing comparisons among the available collection channels to aid in distinguishing defect types of interest. Wafer inspection systems typically report the amount of light scattered in units of latex sphere equivalent (LSE) size. The reference is the amount of light scattered by polystyrene latex spheres of a given physical diameter. LSE size is also a function of the angles of incidence and collection; thus, sizing of a given defect differs from one channel to another. Some defects scatter so strongly that they saturate the detection channel, and no specific size can be assigned. The Surfscan SP2 XP system increases the dynamic range of the darkfield collection channels by raising the saturation limit by a factor of sixteen (Figure 3). This allows more defects to be given an LSE size (Figure 4). LSE size in each channel is an important comparative descriptor for defect classification; therefore, extending the dynamic range of the collection channels enables classification of more defect types. Scattering / ppm nm Dynamic Range Extension Wide Narrow Size / nm Current SP2: nm SP2 XP : nm Figure 3: Improved PMT signal processing methods underlie a sixteenfold increase in the dynamic range of the Surfscan SP2 XP, compared with Surfscan SP2. New system, single incidence New system, dual incidence* Oblique Narrow vs. Oblique Wide: SP2 system HT ST HS +21% +38% +40% +53% +33% +33% Oblique Narrow [µm] Sat Residue Shiny Flake Particle Small Particle Stacking Fault Defects not sized (saturated solo defects) When the range of defect types on the wafer necessitates dual-incidence scanning, throughput is a consideration. The Surfscan SP2 XP delivers a 20% throughput increase for single scans, and a 40% throughput increase for dual scans, compared with the Surfscan SP2 (Figure 2). Extended Dynamic Range *per wafer scan Figure 2: Throughput improvement for Surfscan SP2 XP relative to Surfscan SP2. HT = high throughput; ST = standard throughput; HS = high sensitivity. Wafer inspection systems such as Surfscan SP1 and SP2 detect defects by collecting light scattered by the defect as a laser spot traverses it. The amount of light scattered by the defect is related to its physical size and shape and its reflectance. Normal Narrow [µm] Oblique Wide [µm] Sat Normal Narrow vs. Oblique Wide: SP2 XP system Residue Shiny Flake Particle Sphere Shaped Particle Small Particle Stacking Fault Oblique Wide [µm] Figure 4: Sizing in the Oblique-Wide channel versus the Oblique-Narrow channel shows that for this wafer, many defects fall into the saturated category for one or both channels on the Surfscan SP2. The extended dynamic range of the Surfscan SP2 XP allows all defects on the wafer to be assigned a size in both channels. Sat Sat 29

30 Defect Management Cross-Channel Rules-Based Binning With two darkfield angles of incidence and two independent darkfield collectors, plus the brightfield (DIC) subsystem, the new inspector has a total of five distinct data channels (Figure 5). The dual-scan capability means that multiple-channel data can readily be collected on every wafer. Ratios of defect sizing by various channels can be used as attributes for rules-based binning (RBB), providing new capability to distinguish among defect types. Wide Narrow Oblique Normal Actionable LLPD Classification for Prime Wafers BF DIC Figure 5: Dual scan capability of the Surfscan SP2 XP collects inspection data from all five channels. These data are used as defect attributes for advanced binning, using logical and comparison rule-based algorithms. Large light point defect (LLPD) is an empirical defect classification referring to any defect captured by both brightfield and darkfield channels by an unpatterned wafer inspection system such as a Surfscan. Defect review shows that LLPDs fall into two broad categories (Figure 6): intrinsic crystalline defects best described as faceted pits, but also called air pockets or air bubbles; and polishing defects, including polishing divots and chatter marks. Faceted pits are generated during ingot pulling and are exposed after the ingot is sliced and polished. These large defects 20 to 200µm are not re-workable, and if they align with an active area of the device, they typically cause device failure. IC manufacturers reject all wafers having faceted-pit defects. On the other hand, polishing defects can be reworked for prime wafers in some cases, either through an additional cleaning process or by re-polishing the wafer. A small number of polishing defects can be tolerated for 45nm device manufacturing. The Surfscan SP2 XP uses two aspects of its new technology to separate previously undifferentiated LLPDs into faceted pits and polishing defects. First, the brightfield channel is necessary for its differential interference contrast capability, because faceted pits are always captured in both brightfield and darkfield channels and always produce a negative DIC polarity. While polishing defects are also captured in both brightfield and darkfield channels, their DIC polarity can be either positive or negative. Second, the extended dynamic range clearly differentiates between the two categories: faceted pits and polishing. As a result of this advance in detection and method of binning, prime wafers that were previously scrapped because their LLPD count was too high, can now be re-worked for cases in which polishing defects predominate in the LLPD count. Detecting Scratches and Emerging Defects in Prime Wafers Certain defect types have been difficult to detect using the standard light point defect mode on wafer inspection systems. Besides looking for localized scattering events, the Surfscan SP2 XP can also generate a high-resolution haze map, called SURFimage. 2 First introduced on the Surfscan SP2, SURFimage has been improved further on the new system. With a pixel size one-third as large as that of the original SURFimage, the Surfscan SP2 XP can capture even more shallow and faint CMP scratches (Figure 7) which have been shown to affect yield for flash applications. 3 The new high-resolution SURFimage has also uncovered previously unnoticed defect types such as orange peel, watermarks, slurry residue, and surface roughness changes. These emerging defects have low scattering intensity and a fullwafer signature. With tighter focus on surface quality, emerging defect types may prove important to high k gate performance. Distinguishing Voids from Particles for SOI Wafers Figure 6: LLPDs fall into two broad categories: intrinsic crystalline defects best described as faceted pits, but also called air pockets or air bubbles (red); and polishing defects, including polishing divots and chatter marks (blue). Silicon-on-insulator wafers can provide speed and power consumption advantages over polished silicon wafers. SOI wafers, like prime wafers, contain defect types which can be addressed by the new technology. A void is an intrinsic or crystallographic defect at the surface of the SOI wafer effectively a material rip-out which could arise in either the bonded-wafer process when the top silicon is separated from the bottom or when particles are present on the substrate before BOX implant for the SIMOX process. Like faceted pits in prime wafers, voids are fatal to device manufacturing and are not tolerated by IC manufacturers. 30 Spring 2007 Yield Management Solutions

31 Defect Management The Surfscan SP2 XP system s new technology enables the separation of voids from the relatively innocuous particles and other fall-on defects, which may be cleanable or otherwise re-workable. When the dual-incidence capability of the new system is used, LSE sizing from the oblique and normal darkfield scans can be compared. Figure 8 shows a plot of defect sizing from the Normal-Narrow and Oblique-Wide channels. For both types of SOI wafers (SIMOX and bonded), voids are Regular SURFimage High Resolution SURFimage Hazeline Scratch Detection Figure 7: New high resolution SURFimage with a smaller pixel size demonstrates better defect detection on shallow scratch defects. Normal Narrow Size (µm) SOI Void Classification by Normal Narrow / Oblique Wide Oblique Wide Size (µm) Void Residue LPD DNN / DWO size ratio = 1.3 Defect Count SOI Void Classification by Normal Narrow / Oblique Wide Void Size Ratio 2 Void Residue LPD Figure 8: Comparison of defect sizing from the Normal-Narrow and Oblique-Wide channels. For SOI wafers, voids are clearly distinguishable from particles and other fall-ons. The impact of this capability is that wafers having large particles only would not be scrapped along with wafers having voids. EPI Stacking Fault Classification by Normal Narrow / Oblique Wide 1.4 EPI Stacking Fault Classification by Normal Narrow / Oblique Wide 12 Normal Narrow Size (µm) Stacking Fault Residue LPD DNN / DWO size ratio = 1.5 Defect Count S.F. Stacking Fault Residue LPD Oblique Wide Size (µm) Size Ratio Figure 9: Comparison between Normal-Narrow and Oblique-Wide sizing distinguishes ESFs from other defect types. Wafers having ESFs will be scrapped, while wafers having small numbers of relatively innocuous defect types may pass IC manufacturers requirements for 45nm. 31

32 Defect Management clearly distinguishable from particles and other fall-ons using this method. The result is that wafers having large particles only would not be scrapped along with wafers having voids. Classification of Stacking Faults on Epi Wafers Epitaxial silicon wafers are designed to provide advantages in device speed, breakdown voltage, and latchup resistance. Demand for epitaxial wafers is expected to grow 45% between 2006 and As with SOI or prime wafers, epi wafers are subject to crystallographic defects as well as particles and other fall-ons. The most common kind of crystallographic defect is the epi stacking fault (ESF). These represent a misalignment in the otherwise perfect crystal lattice, originating when a particle or other defect lies on the surface of the bulk silicon upon which the epi layer is grown. The interface defect initiates the crystal misalignment, and as the epitaxial film grows, the ESF propagates through the crystal to the surface of the epi layer. Epi stacking faults including related crystal defects such as hillocks, mounds and spikes are deadly to the transistor built upon them. IC manufacturers typically specify that epi wafers must be ESF-free. Although epi wafers cannot be reworked, the Surfscan SP2 XP enables improved separation of stacking faults from other common epi defects, such as particles and flakes. While previous Surfscan models were able to distinguish stacking faults to a certain extent, the dual-incidence scan capability of the system improves accuracy and purity by as much as 50%. The new system has demonstrated that ESF defects scatter more strongly under normal incidence, while particles and other less damaging defects scatter more strongly under oblique incidence. A comparison between Normal-Narrow and Oblique Wide sizing, as shown in figure 9, demonstrates that ESFs are clearly distinguishable from other defect types. Wafers having ESFs will be scrapped, while wafers having small numbers of other defect types may pass IC manufacturers requirements for 45nm. Summary The Surfscan SP2 XP has been introduced with new and enhanced capability to distinguish crystallographic defects from particles, flakes and other fall-ons. This ability to discern which wafers are free of intrinsic defects means that fewer wafers may be scrapped. As wafers become more complex, with epitaxial layers and strained layers of various materials, their increased cost makes the identification of intrinsic defects of tremendous economic advantage to both wafer manufacturers and IC makers. References 1. C. Dennis; R. Stanley; S. Cui, Detection of a New Surface Killer Defect on Starting Si Material using Nomarski Principle of Differential Interference Contrast, to be presented at ASMC See also SP1 Brightfield Defect Detection, Wilson Cheh, KLA-Tencor Application Note, March, A. Belyaev; A. Steinbach; Hamlyn Yeh, and B. Pinto; N. Microdevices, New Technology for Generating High-Speed, Full-Wafer Maps of Microroughness and Grain Size, July, 2006 (Japanese). Also printed in English in Yield Management Solutions, Summer 2006, pp J. Park, Memory Wafer Trend for 45 nm and Beyond, Department of Electronics and Computer Engineering, Hanyang University, Semi STP, December, Gartner/Dataquest, December AUGUST YMS Singapore, Raffles The Plaza Hotel, Singapore AUGUST YMS Taiwan, Ambassador, Hsinchu, Taiwan AUGUST YMS Shanghai, Ramada, Shanghai, China SEPTEMBER YMS Beijing, JinJiang Hotel, Beijing, China DECEMBER YMS Japan, New Otani Makuhari, Makuhari, Japan Attend KLA-Tencor s Yield Management Seminar Series For more details and registration for KLA-Tencor events, please visit Spring 2007 Yield Management Solutions

33 Defect Management Unpatterned Wafer Inspection for Immersion Lithography Defectivity Dieter Van Den Heuvel, Frank Holsteyns, Wim Fyen, Diziana Vangoidsenhoven, Paul Mertens, Mireille Maenhoudt IMEC Lisa Cheung, Gino Marcuccilli, Gavin Simpson, Roland Brun, Andy Steinbach KLA-Tencor Corporation High-yield immersion lithography requires the ability to distinguish between patterning and stack-related defects, such as wafer and resist-coating/bottom anti-reflective coating (BARC) defects. Extensive optimization of an unpatterned inspection tool, combined with advanced defect source analysis software, enables clear observation of stack-related defects through careful partitioning of individual layer inspections. The switch from dry to immersion lithography has important consequences regarding wafer defectivity. The immersion process introduces additional types of defects that are primarily related to the physical contact of the immersion fluid (water) with the wafer surface. This article refers to resist coating defects, as well as defects coming from the silicon wafer or the BARC, as stack-related defects, while other types are referred to as immersion-specific defects. Because the most common approach in the study of lithography-related defects is to make use of patterned wafer inspection tools, only patterning-related defects are revealed. However, this does not allow distinguishing stack-related defects from immersion-specific defects. This article investigates wafer defectivity throughout the various process steps prior to and including lithography, in order to understand and characterize the origin and propagation of defects (size, class, location) through each of these process steps. This requires extensive metrology optimization. Unpatterned wafer defect inspection was performed using various darkfield inspection tools including the Surfscan TM SP1 DLS and SP2, and a brightfield inspection tool (KLA-Tencor 2351 TM ). Defectivity after patterning was evaluated on the same brightfield tool. The lithographic stacks were based on commercial 193nm resist with and without immersion-dedicated topcoats. Defect review and classification were performed by SEM and optical microscopy. Unpatterned Defect Inspection Technology The Surfscan SP2 unpatterned inspection system employs a UV laser (355nm) for scanning across the wafer surface and detecting any unusual light scattering as defects. As most existing dry resist stacks have been well characterized with its predecessor, Surfscan SP1, using a 488nm laser for the existing lithography processes, the benchmarked typical resist defects are already well understood. With the shorter wavelength and a higher power laser, the SP2 not only achieves a significant improvement in the sensitivity for contamination defects but also resolves the easily overlooked process-induced flow type of defects in the resist stack. Typically, the smallest characteristic size of photolithographic structures is in the range of half the wavelength used, targeting 45nm technologies. Defects on the order of a half wavelength are therefore potential yield killers. The reduced laser spot size of the SP2 along with its optimized collection angles and faster signal processing allows the system to achieve the necessary sensitivity at a production throughput suitable for monitoring these smaller defects in the litho substrate and films. Lithography Stack Information One of the most important concerns when switching from dry to wet lithography is to overcome the leaching of resist constituents into the immersion fluid, resulting in possible contamination of the lens. Previously, the introduction of a topcoat was the primary approach to making the dry resist applicable to immersion processing. Today, the introduction of a new generation of low leaching resists, such as the PAR-IM850 (Sumitomo) makes it possible to process without a topcoat. This study focuses on the defectivity of the spincoated anti-reflective coating ARC-29A (Brewer Science/Nissan Chemicals) and PAR-IM850 layers. Both layers are organic polymers with propylene glycol monomethyl ether acetate (PGMEA) as the primary solvent. The majority of these solvents are removed from the material during a 60s soft bake at temperatures of 205 C and 105 C respectively. This bake step also promotes the adhesion and stabilizes the film. 33

34 Defect Management Scattering Intensity (ppm) Resist Stack, 70nm PSL BARC Resist (150nm) Resist Thickness (nm) SP1 DW-PU SP1 DN-PU SP2 DW-PU SP2 DN-PU Having the choice of either normal or oblique incidence enables the detection of defects of specific types at different detection thresholds. Practically, the two incidence angles lead to different responses for a PAR-IM850 resist stacked on ARC-29A with silicon as substrate. Using Klarity Defect TM, defect source analysis (DSA) can be used to compare defect locations on the two wafer maps to, in this case, a tolerance radius of 200µm (Figure 3). This map-to-map technique allows common and added/unique defects to be quantified on a histogram or identified on a wafer map. This technique was used throughout the paper to identify differences in capture rate between normal and oblique modes, and to show common and added/unique defects throughout the resist stack. In this case normal incidence appeared to give a higher number Figure 1: Scattering intensity model of a 70nm PSL sphere on a resist stack, at varying resist thickness, comparing Surfscan SP1 and SP2 (DW Dark Wide, DN-Dark Narrow) collection channels. Defect Detection on Resist Figure 1 shows the scattering intensity model of a 70nm polystyrene latex (PSL) sphere on a resist stack. A zero resist thickness, denoted on the graph, essentially represents the BARC layer on top of a bare silicon substrate. A 150nm resist thickness was used in the experiment. It is apparent that the SP2 provided a much higher scattering signal over all thicknesses than the SP1, illustrating better sensitivity of the SP2 for smaller defects. The SP2 was also better at detection of sub-100nm defects in the litho stacks. Besides resist thickness, another parameter that affects the scattering signal for detection of defects is the choice of polarization of the incident and scattered light. The polarization configuration of P-U (P-polarized for the incident optics and Unpolarized for the collection optics) was selected for the specific resist stack thickness (150nm), as seen in figure 2. The figure represents the scattering signal of a 70nm latex sphere at a specific thickness. At any particular film thickness, the combined constructive and destructive interference effect requires selection of the appropriate optical configuration to achieve the best scattering signal for these thin resist stacks, ARC-29A and the PAR-IM850. Scattering Intensity (ppm) Resist Stack, 70nm PSL Resist Thickness (nm) Resist (150nm) SP2 DW-PU SP2 DN-PU SP2 DW-SU SP2 DN-SU SP2 DW-CU SP2 DN-CU Figure 2: Scattering intensity model with P-U, S-U and C-U polarizations. of additional defects. This is mainly due to a higher number of randomly distributed unique defects sensitive to the normal incidence inspection close to the detection limit. A second contribution came from the higher count of defects from clusters. Figure 4 shows the comparison of the SP2 to the 2351 brightfield inspection results. The 2351 system s 0.25µm pixel-size inspection of the resist (visible light, avoiding any exposure of the resist) gave a comparable sensitivity to the oblique illumination of the SP2. Again, a better result was observed using the normal illumination. The variation in defect counts was mainly due to the difference in cluster reporting :PAR-IM850_Oblique 0002:PAR-IM850_Normal :PAR-IM850_Oblique 0002:PAR-IM850_Normal Defect Count :PAR-IM850_Oblique Unique normal 116 Common with oblique :PAR-IM850_Normal Defect Count Individual LPDs <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= Clusters <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= <=x<= Defect Count Figure 3: Comparison of defects for normal versus oblique illumination. 34 Spring 2007 Yield Management Solutions

35 Defect Management 2351 (0.25µm pixel) Defect counts: 154 SP2 Oblique (>72nm LSE) Defect counts: 811 SP2 Normal (>76nm LSE) Defect counts: 1449 Figure 4: Comparison of different inspection tools/modes. Noise Suppression The choice of polarization and collection angles is important for suppressing the noise contribution from surface roughness (source of N) induced by the wafer processing. Organic films typically contribute a high level of surface scattering at UV wavelengths, depending on the film-specific chemical composition. A built-in optical filter on the SP2 can suppress this surface scatter from photons carrying higher energy at the UV wavelength than ones at 488nm on SP1. Up to 50% of suppression of the background signal (haze) can be obtained. The SP2 allows the selection of either 10% or 100% of the full laser power in the recipe to minimize any potential for material damage at UV wavelengths and high power dosage, for resists and other organic films. In order to compare the potential damage to the resist, and to try and understand the mechanism behind any changes, wafers with PAR-IM850 were scanned ten times using normal incidence with the optical filters off for 10% and 100% laser power. Figure 5 shows the average haze for the wide and narrow channels after each scan. 100% power was shown to change the haze by 7% and 5% for the wide and narrow channels respectively after 10 scans. The 10% level resulted in a minor change in the haze signal. The change in haze may be a surface modification due to solvent outgassing from the surface, a minor reflowing of the top surface or a chemical change in the resist. All inspections were for this reason performed at 10% laser power. To check for modifications of the chemical bonding at 10% or 100% power, FTIR was used. The wafers, scanned with the SP2 (one scan and 10 repeated scans) were compared to a reference wafer that had not been scanned. No evidence was found for any SP2-induced change in photoresist composition or bond structure. These results indicated that probably some solvents were evaporating from the resist during the laser exposure. Recipe Summary Recipes for all resist stack layers in the study were optimized with the above considerations to achieve the best signal to noise. Table 1 summarizes the best available defect threshold (Latex Sphere Equivalent, LSE) with two sensitivity-determination methods. In all cases, the sensitivity achieved on the SP2 was better than that of the SP1, demonstrating the need for the use of SP2 for immersion lithography resist monitoring as design rules shrink. All scans on the SP2 were performed with the 10% laser power mode and the use of optical filters for both channels (wide and narrow). ARC-29A S/N = 1.5 Capture rate >95% SP2 Wide Oblique 83nm 80nm Narrow Oblique 94nm 84nm Average haze: percentage change (%) % laser power 100% laser power 100% Wide 100% Narrow 10% Wide 10% Narrow SP1 Wide Oblique 95nm 64nm Narrow Oblique 105nm 101nm PAR-IM850 SP2 Wide Oblique 75nm 71nm Narrow Oblique 72nm 65nm SP2 Wide Normal 76nm 69nm Narrow Normal 76nm 69nm SP1 Wide Oblique 90nm 87nm Narrow Oblique 82nm 78nm SP1 Wide Normal 81nm 81nm Narrow Normal 149nm 145nm Run No. Figure 5: Change in average haze of PAR-IM850 over 10 scans for 10% and 100% laser power, measured in wide and oblique channel of the SP2. Table 1: Signal to noise versus capture rate for the different layers, comparing SP1 and SP2 versus normal and oblique for the ARC and resist. SP2 recipes were set at 10% laser power and optical filters for both channels. 35

36 Defect Management Defect Analysis: Stack-Related vs. Immersion-Specific Defects When monitoring an immersion lithography tool (ASML XT:1250Di) or process with particle per wafer pass (PWP) tests, a typical tool monitoring technique, it is important to be able to understand whether the defects are related to the resist stack or they are intrinsic to the immersion process itself. A clear distinction allows one to continue the ongoing improvement in defect reduction. Thus, a partitioning experiment was performed to allow the calculation of the impact of each layer on total defectivity, and determine the impact of these defects on the overall pattern formation. An overview of the partitioning experiment is given in figure 6. Note that specific patterning defects were excluded from this study. Si SP2: normal 2351: 0.16µm pixel ARC-29A PAR-IM850 SP2 SP2 SP2 PAR-IM850 Scan at zero dose ASML XT:1250Di Scan (nominal dose)+peb+develop Figure 6: Pathway of partitioning experiment with intermediate inspection steps. The starting material, bare silicon (MEMC p Mon F130), was first inspected with a SP2 recipe at LSE >52nm including a crystal originated particle (COP) classification to determine incoming baseline defectivity. An ARC layer was coated on the silicon wafer, followed by a soft bake. This layer was inspected by the SP2 in the oblique mode for LSE >83nm. The follow- ing part of the stack consisted of a photoresist PAR-IM850 coating and soft bake. This layer was also inspected by the SP2 in normal mode at LSE>76nm. In some practical cases the intermediate inspection of the ARC layer was skipped. The next lithography processing step on the ASML 1250i was either a scan at zero exposure dose (simulating an immersion lithography process) or full exposure plus post-exposure bake and development to give the printed pattern. Finally, defect maps before and after scan/development were compared, and a defect source analysis was performed on the results to distinguish between stack-contributed defects and immersion-specific defects. In the experiment, the unpatterned wafer inspected area was 660.5cm 2, using high sensitivity mode, with 5mm edge exclusion. The patterned inspection used a different inspection area, determined by the number of available die on the wafer that could be inspected using the 2351 ( cm 2 ). This would have affected the results if defects had been found at the edge of the wafer; however, the SP2 inspection results showed that the majority of the defects were not from this region. Scan at Zero Dose After the stack formation, the wafer was scanned with water (in the ASML XT:1250Di) at zero dose to mimic a typical wafer passing under the immersion head, and determine the effect of the water flow over the wafer during exposure. The wafer was then re-measured on the SP2 to isolate immersion-related defects from the stack defects. From the results in figure 7, the impact of each layer during the stack formation was observed. A map-to-map coordinate comparison at each step allowed the close examination of defects contributed from each specific process step with a :Silicon 0002:PAR-IM :PAR-IM850-latent Immersion induced defects Defect Count Substrate / Coating defects Silicon PAR-IM850 PAR-IM850-latent Figure 7: Defects reported throughout the stack: Silicon, ARC-29A/PAR-IM850 (post ARC/resist coat) and PAR-IM850 (latent: post scanning at zero dose) for LSE >76nm. It is clear that a significant number of defects were added during the immersion step. 36 Spring 2007 Yield Management Solutions

37 Defect Management :Silicon 0002:ARC-29A 0003:PAR_IM :2351_UV_0.16 Patterning defects Defect Count Resist / Coating defects Silicon ARC-29A ARC29A PAR_IM _UV_0.16 Figure 8: Defect reported throughout the stack: Silicon, ARC-29A, PAR-IM850 (post resist coat) and PAR-IM850 after exposure/patterning. comparison stack tolerance set at 200µm (ARC and resist comprised one measurement). It was clear that a significant number of defects (>76nm LSE (optimized recipe)) were added during the immersion step. However, the various types of stack-related defects were not to be neglected. They were typically embedded in the resist. The final impact of these defects (stack-related or immersion-related defects) on the lithographic process is not known; a detailed study on the impact on patterning is required patterned inspection a. Figure 9: a) Inspection and optical review of the wafer after patterning; b) Streak TM inspected by the Surfscan SP2 SURFimage. Exposed Wafer Tests (Regular Patterning), Example 1 To study the impact of stack-related defects on patterning defects, and distinguish them from immersion-related defects, the wafers were exposed and parallel lines were patterned in the resist. A parallel study was conducted using a wafer in which the stack was formed and measured in the same manner as above, except that the wafer was exposed with a small die (10x10mm 2 ) reticle, using exposure conditions to produce 100nm line/space features. b. Defects originating from the incoming silicon wafer were traced through the ARC-29A coat step and the PAR-IM850 coat step, as illustrated in figure 8. The influence of the ARC-29A-defects was traced through the resist coat step and also the final develop and rinse steps. In this case ~30% of the defects inspected after pattern formation were attributed to the previous layer, with the resist layer having the highest influence. The remainder of the defects were attributed to current-layer patterning. As indicated by the optical review results (Figure 9), the majority of the defects added during the resist coat step were particles in or on the surface of the resist. The 37

38 defect ManagEMEnt a. b. a. Normal Narrow b. Multiple defects captured c. Example of two extracted parameters: defect length and area. Defect Count Figure 10: a) SURFimage of PAR-IM850 from the normal narrow channel, and b) the corresponding fl ow defect (originated from a cluster defect) captured by algorithm. Defect feature Defect Length (mm) Defect Area (mm 2 ) Defect ID Figure 11: a) SURFimage of PAR-IM850 from normal narrow, and b) all fl ow defects captured by the algorithm, c) with the defect length and area parameters displayed for each defect :Silicon COP Classified 0002:ARC-29A 0003:PAR-IM :2351 Patterned Silicon COP Classified ARC-29A PAR-IM Patterned 86 Patterning defects Stack related defects Figure 12: Defects reported throughout the stack: Silicon, ARC-29A, PAR-IM850 (post resist coat) and PAR-IM850 after exposure/patterning. 10 critical patterning defects (Figure 10) which later were found to originate at the resist steps were clearly mapped to a streak defect by the Surfscan SP2 SURFimage map an enhanced haze capability on the Surfscan SP2 earlier in the inspection steps. The defect cluster with its comet tail caused a high defect count. More important, the small variation in resist uniformity can lead to a more signifi cant effect of subsequent variation in line width due to a thinnerthan-nominal resist layer, or a missing pattern in the worstcase scenario for patterned wafers. These defects were captured by a prototype algorithm outputting a defect feature vector of over 20 attributes (such as length, area, intensity, haze statistics, orientation, etc.) which was used for classifi cation and defect binning. The streak defect feature was extracted and displayed as fi gure 10b. This extraction of feature-only representation allows the defect to be exported for display in Klarity as a clustered, extended defect. The attributes are then available for Paretos, decision making, process control, etc. Figure 11 shows a different PAR- IM850 wafer with multiple streak defects, all of which were captured by the algorithm, although one streak was captured as two different defect segments. The length and area calculated by the algorithm for each defect are displayed in fi gure 11c. Exposed Wafer Tests (Regular Patterning), Example 2 A second case, shown in fi gure 12, showed an improved defectivity level. In this case the infl uence of the stack-related defects was lower: ~5% of the defects originated from the substrate. Defects from the substrate appeared to be COPs 3 Spring 2007 Yield Management Solutions

39 Defect Management detected during the brightfield inspection. In this inspection the capture rate of the silicon defects in the ARC-29A was lower than that seen in the resist inspection or in the previous example. This was due to a slight change in the sensitivity in the ARC-29A recipe; however, the impact of the COPs/particles could be clearly seen during the resist inspection (Figure 13). The defects seen as small, dark dots on the patterned inspection map were common to the defects seen during the SP2 silicon wafer initial inspection, mostly matching the spatial patterns of the COPs. The majority of defects observed on the BARC and resist were particles, as seen in figure 14. Figure 13: Silicon defects in final pattern, filtered using Klarity. BARC Conclusions For successful and efficient process control during immersion lithography, the capability to distinguish immersion/patterning-related defects from stack-related defects is very useful. The stack-related defects were observed only after careful partitioning of individual layer inspections and defect source analysis using Klarity. The optimization of the unpatterned inspection tool, SP2, was central. Improved sensitivity at adequate signal-to-noise ratio was easily obtained on the resist stacks by using the shorter wavelength, UV-laser light of the SP2. For bare Si and BARC, oblique-incidence illumination gave better sensitivity and captured more defects. However, monitoring of the resist, and stacks with resist, required normal-incidence illumination for best scattering intensity. The use of an optical filter and the 10% laser power setting also contributed to establishing a low, stable background signal for each inspection. As immersion tool development is improved and immersion-specific defectivity is reduced, the proportion of stack-related defects will become a significant fraction of the overall defect count. A detailed method has been shown for the accurate monitoring of these stack-related defects. This includes point defects (embedded particles) or flow defects (streaks) identified and classified using SURFimage. This information was used to identify the defect origin(s) for ultimate elimination of defects in the stacks. Stack defects continue to be important for either dry or wet lithography steps, as they have direct implications to the subsequent processing steps. However, determining the direct impact of individual stack defects on the final defectivity of the immersion process will require additional studies as the immersion process further improves and matures. F Figure 14: BARC and resist defects, filtered using Klarity. 39

40 Mask Comparing Cost of Image Qualification and Direct Mask Inspection Tatsuhiko Higashiki Toshiba Corporation Kaustuve Bhattacharyya, Viral Hazari, Doug Sutherland KLA-Tencor Corporation A growing percentage of phase shift masks using DUV lithography show defect growth problems. The model described below shows that image qualification using test wafers can be about three times more expensive, compared to a direct reticle inspection solution, and that use of direct inspection can potentially save over US $4M per year. Litho-cluster cycle time is a critical economic factor at 65nm design rules and below. Besides running production, part of the litho-cluster time is also used to expose test wafers for mask qualification at periodic intervals. Incoming mask inspections as well as periodic mask inspections (re-qualification) are needed to prevent yield loss from progressive mask defect problems (such as crystal growth or haze), traditional reticle contamination, electrostatic discharge (ESD) and migrating defects (from non-critical to critical locations on the mask). Although many of the masks will remain problem-free (clean) even after numerous exposures, previous publications from other fabs indicate that on average, about 1% of binary masks (using 365nm lithography) and 6 to 15% of phase-shift masks (using DUV lithography) show defect growth problems. 1, 2 The goal of this study was to identify these masks ahead of time using periodic monitoring and thus prevent them from being used in production, before defects reach a critical level. At the end of the study, the simulation model showed that a productivity improvement of 2475 wafers per year was the result of using direct reticle inspection for this 15K wafer starts per month (WSPM) fab. Mask Monitoring Techniques Two basic techniques are typically used for mask monitoring: Indirect reticle inspection, generally known as image qualification or wafer print check. This is achieved by printing a wafer using the mask in question, followed by inspection of that printed wafer. Two possible options include: 2. a. Using a test wafer (resist-coated bare silicon wafer) to print the image; b. Using an actual product wafer (there will be underlying layers, hence more background noise. Direct reticle inspection, where the options include: a. STARlight TM ; b. Die to die transmitted light (ddt); c. Die to die reflected light (ddr); d. Die to database (both T and R). These techniques have their pros and cons based on sensitivity requirements and associated cost. This article focuses primarily on the cost of ownership (CoO) comparison between image qualification and direct mask inspection using STARlight. We developed a cost model to compare the financial impact of image qualification versus direct mask inspection. All the inspection and process tool costs were included, as well as turnaround time (TAT) at the litho-cluster for image qualification and TAT for direct mask inspection. Then, the inspection cost and the opportunity cost (for using the litho-cluster to expose test wafers other than production wafers) were combined and the net effect compared. The goal was to find the most cost effective way to do mask qualification in advanced wafer fabs. Previous work has addressed the cost advantages of reticle inspection over image qualification. 3 A wafer print check or image qualification on a test wafer will need some of the scanner and track time for the coat, expose and develop steps of the single test wafer. This means that not only should the litho-cluster cost for that time (as well as operator and wafer inspection cost) be considered, but also the opportunity cost Spring 2007 Yield Management Solutions

41 Mask for product that is not produced during that time. As the scanners are generally kept fully loaded in a production environment with little excess capacity available, this opportunity cost can be significant. All modeling numbers (tool cost, throughput, wafer starts, wafer cost, etc.) are conservative averages taken from the literature. The goal here was to gain an academic understanding of the problem at hand; the inputs do not represent any Toshiba-specific condition. Cost Model Components Several key components were taken into consideration to develop this cost model: a. Litho-cluster time time required to coat, expose and develop one single test wafer; b. Litho-cluster cost; c. Wafer inspection time time required to inspect this single wafer on the wafer inspection tool; d. Wafer inspector cost; e. Mask inspection time time required to inspect the mask on the mask inspection tool; f. Mask inspector cost; g. Review time on wafer time required to review wafer on SEM; h. SEM tool cost; i. Review time on reticle time required for reviewing the mask inspection; j. Operator cost for all the above time intervals; k. Transportation time involved between the above steps, to calculate overall TAT; l. Resist coated Si wafer cost; m. Average selling price (ASP) of production wafer; n. Litho-cluster throughput; o. Number of litho-clusters in the fab (the number considered here is mostly for ArF litho-clusters, where mask re-qualification is most needed); p. Number of inspections needed per day (for all litho-clusters) if image qualification method is used; q. Number of inspections needed per day if direct mask inspection is used; r. Wafer cost (resist coated Si wafer) can be re-used (strip and re-coat) five times. Typically, as direct mask inspection sensitivity is higher 4, the number in the item q above should be lower than item p. The cost model includes two distinct sections for image qualification or print check on the test wafer: (1) combined tool, labor and material cost per inspection (five-year depreciation) and (2) opportunity cost. The direct mask inspection will consist of item (1), but the opportunity cost will be absent there. Most wafer fabs have sufficiently sophisticated WIP control systems to effectively reduce the TAT for direct mask inspection to zero. It is important to understand items a and k because they significantly impact the overall cost model (since the tool cost and opportunity cost both use these numbers). Figure 1 describes the components of the time intervals involved. It is assumed in this model that the time required to coat-expose-develop a single test wafer (resist coated Si wafer) is five minutes (average). The time required to switch the mask in question with another mask (while the mask in question waits until the wafer inspection of the above single test wafer is finished) is about one minute. Hence the total TAT for the litho-cluster is six minutes in this example. Wafer In t in t s Stocker t out t in t s Stocker t out t in t s Stocker t out t process = 5min Coat Expose Develop t queue t CD CD Measure t queue t OL Overlay t queue Macro Litho Cluster Wafer out for image qual t switch = 1 min t in t s Stocker t out t in t s Stocker t out ADI Scanner Storage Reticle in question returns to scanner storage Next reticle goes on stage and production continues t queue twaf_insp Wafer Inspection t queue t sem SEM Figure 1: The turnaround time involved for litho-cluster and image qualification in the example shown here is six minutes. 41

42 Mask Every time an image qualification is performed, six minutes of litho-cluster time is consumed: this is six minutes of lost production time. This time will then be needed to calculate the opportunity cost involved. The mask inspection frequency and the fact that the image qualification does not provide as much early warning as direct mask inspection have been discussed in previous literature. This means that if image qualification is adopted, the overall number of inspections using this method (consuming six minutes of litho-cluster time for each) will be higher than the number of inspections needed in the direct mask inspection technique. It is assumed in this current work that the number of inspections needed using image qualification inspection will be almost two times more than that using direct mask inspection. Limiting image qualification on test wafers in a fully loaded fab can be very productive. Zero TAT for Direct Mask Inspection With the proper implementation of direct mask inspection, the masks in question can be taken out of the scanners well ahead of the time that they are due for production (exposure). Each mask can then be inspected on a reticle inspection tool and the results reviewed. If there is no issue with the mask, it can be returned back to production. As the number of steps involved in mask inspection is small and this does not impact scanner cycle time or any other process or inspection steps in the wafer fab, the above logistics can be implemented to effectively result in a TAT of zero for direct mask inspection. Comparing Image Qualification Methods Using generic numbers, the concept of this model comparing the use of test wafers and direct mask inspection using the STARlight tool is demonstrated in table 1. For example, the litho-cluster cost (scanner + track) is considered to be US $25M for this work. This value varies somewhat depending upon the make and model of the scanner-track combination. The cost model is for a fab producing 15K WSPM using five ArF (193nm) litho-clusters (additional 248nm litho cells would be required to meet production, but it is assumed for simplicity that only the 193nm scanners would be impacted by reticle qualification as most of the re-qualification needs are in 193nm litho). The model clearly shows that opportunity cost (due to loss of production during the time which image qualification takes away from the litho-cluster) drives the overall cost. It is highly unlikely that advanced fabs (especially the fabs that are ramping) have excess litho-cluster capacity, so this opportunity cost is real. In this example, the model predicts a total cost of US $7.03M per year if image qualification using test wafers is used, versus US $2.73M per year if direct mask inspection is applied. This cost includes everything from items a to r in the cost model (tool cost, operating cost, opportunity cost, inspection strategy differences, etc.). 42 Technique Inspection cost/mask* # of inspections per day* Inspection cost/year* Production lost/mask inspection** Production lost/year ** Total cost/year*** *Inspection cost **Opportunity cost ***Total cost Table 1: This cost model comparison of image qualification vs. direct mask inspection (STARlight) shows that image qualification using test wafers is significantly more expensive. The Simulation Model Image Qualification US $ US $3.33M US $411 US $3.70M US $7.03M Direct Mask Inspection US $632 The results presented in this section were generated from a comprehensive state model developed at KLA-Tencor, which simulates the flow of wafers through a fab. The model can simultaneously simulate up to four different process flows each with up to 500 steps in a fab with 80 toolsets, and with up to 20 tools in each set. The model works by assigning states to each of the lots (e.g. On Hold, In Queue, Being Processed, etc.) and to each of the tools (e.g. Up, Down, Busy, Idle, etc.). A simulation clock moves in two-minute intervals and the program updates the state of every tool and every lot in the fab and moves the lots through the fab in accordance with a fabspecific, customizable process flow (or run card). The run card contains all of the information about how to process the lot at each step the toolset used, number of wafers to be processed, and, where applicable, the target, distribution and spec limits for film thickness, CDs, overlay and defects thus making the model customizable to any fab environment. Each step in the process can assign up to three different parameters to the lot. For example, a lot going through a photo step could be assigned values for CD, overlay and defects, each of which could then be measured at a subsequent measurement step. The tool data is handled separately and each toolset can be assigned a host of productivity and reliability characteristics including throughput, MTBF, MTTR, Qual Period, Qual Time, PM Period, PM Time, Precision and Matching. In addition, the model can simulate two different cases of wafer success interrupts: one where some manual intervention is required but the lot does not have to be removed from the tool; and a second case where the lot has to be put on hold. In both cases, one can specify the MTBA, MTTA and the aver- 12 US $2.73M n/a n/a US $2.73M Spring 2007 Yield Management Solutions

43 Mask age lot-hold time (where applicable). To simulate the effect of doing indirect reticle inspection, two process flows were created. One is a regular production flow for a nine-metal level process with 29 photo steps. The other (the indirect inspection) is a short loop that prints a single wafer on one of the 193nm scanners and then sends it to a wafer inspection tool to look for potential defects. As with the cost model discussed earlier, it is assumed that the time needed to coat, develop and expose a single wafer is six minutes and the time to inspect that wafer is one hour. By varying the number of wafers started in the short loop process (i.e. the number of reticle qualifications) one can simulate the impact they have on total fab production. Figure 2 shows that increase in the number of image qualifications has a non-linear impact on the productivity. Clearly, in a fully loaded fab, limiting image qualification on test wafers can be very productive. Significant Overall Savings The modeling results clearly show that if there is no excess scanner capacity (which is the case in most advanced fabs), each extra minute of litho-cluster time becomes very valuable. This is because one should consider as lost opportunity cost for that minute not just scanner cost or other related operating costs, but also the production wafers that could have been produced during this extra minute. This makes each extra minute very expensive, considered as a function of wafer ASP, throughput and time. An image qualification method using test wafers is calculated to be about 3x more expensive compared to a direct reticle inspection solution. This work attempts to quantify the cost impact of both direct and indirect mask inspection. In the example of the 15K WSPM fab, an image qualification using test wafers is calculated to be about three times more expensive compared to a direct reticle inspection solution (TeraScan SL516h). A simulation model estimates that a productivity improvement of 2475 wafers per year is possible as a result of using direct reticle inspection for this 15K WSPM fab. It should be noted that there is another method of image qualification that uses actual production wafers, which will not impact cost as much; however, the signal to noise of printed mask defects on wafers is very low on product wafers due to the high background noise, and this is not adequate for early warning. Such a solution was not considered as a part of this study. Lost Productivity (Wafer/Yr) With proper implementation, direct mask inspection did not impact litho-cluster cycle time, so the cost associated in this case was just the tool cost and operating costs. The difference between the cost of image qualification using test wafers and direct mask inspection will continue to grow as scanner prices continue to climb and more double exposure techniques are adopted in the process, making litho-cluster cycle time even more expensive. Besides the technical requirements, such fab economics should also be considered when choosing the ideal method for mask re-qualification inspection in wafer fabs. Acknowledgements This work was previously published in Photomask Technology 2006 Proc. of SPIE Vol. 6349, 63493N, 2006 The authors would also like to thank Yoshinori Nagaoka and Toshitsugu Miyake of KLA-Tencor for their contribution. References Indirect Reticle Quals per Day Figure 2: Increasing image qualification on test wafers can seriously impact productivity. 1. K. Bhattacharyya, M. Eickhoff, M. Ma and S. Pas, A Reticle Quality Management Strategy in Wafer Fabs Addressing Progressive Mask Defect Growth Problem at Low k1 Lithography, Photomask Japan, K. Bhattacharyya, K. Son, B. Eynon, D. Gudmundsson, C. Jaehnert, D. Uhlig, A Reticle Quality Management Strategy in Wafer Fabs Addressing Progressive Mask Defect Growth Problem at Low k1 Lithography, BACUS Symposium on Photomask Technology, A. Dayal, N. Bergmann and P. Sanchez, Implementation of High Resolution Reticle Inspection in Wafer Fabs, Proceedings of SPIE Vol. 5038, K. Mai, M. Tuckermann, SPC-based In-line Reticle Monitoring on Product Wafers, ASMC

44 Patterning Enabling Double Patterning at the 32nm Node Kevin M. Monahan KLA-Tencor Corporation The use of double patterning lithography (DPL) at the 32nm node poses several challenges. The sum of edge placement errors in multiple patterning steps (CD error) can make DPL significantly more sensitive to overlay error. And the increase in cycle time, with two photo and etch steps, can result in lower throughput and higher cost. Implementing grating-based overlay technology can improve accuracy and minimize overlay model residuals, while grating-based scatterometry can be used to measure shape and profile parameters that support direct feedback of focus and exposure corrections to the litho cell. Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. This article discusses interim solutions for control of DPL. HM 1 Etch Layer PR 2 PR 2 HM 1 OLE>0 Double patterning usually consists of a first exposure step, followed by a hard-mask etch. A second exposure with a different reticle is followed by another hard-mask etch. At this point, CD and overlay error combine in the resulting pattern, so that 1 1 CDE = CDE1 + CDE2 ± OLE 2 2 Figure 2: Abbreviated DPL process with non-zero overlay error. The challenge is to control intra-layer overlay error to reduce the overall CD error. The CD error (CDE) is the sum of edge placement errors in the first and second patterning steps, including intra-layer misregistration or overlay error (OLE). In dense patterns, overlay error can produce lines that are alternately too large and too small (Figures 1-2). This is the first major objection to DPL. HM 1 PR 2 PR 2 HM 1 The second major objection is cycle time, which increases due to the extra photo and etch steps. The revenue loss ( R) arising from increased cycle time ( t) is expressed in this modified Leachman model: 44 Etch Layer OLE=0 Figure 1: Abbreviated DPL process with zero overlay error. The challenge is to match the etch CD from resist and hard mask structures. R = T D() t P( t + t) dt D( t) P( t)dt 0 T 0 Here, D is the rate of good die out and P is the average selling price at time (t) over the interval (T). If P were constant, revenue loss would be zero; but, for products like flash memory, price can decline 50% in a year, resulting in extreme sensitivity to cycle time variation. Spring 2007 Yield Management Solutions

45 Patterning 3-Sigma Vs Spec (nm) Figure 3: Traditional large box-in-box overlay targets suffer from sensitivity to process variation. Grating targets like the one above can reduce error by >2x. Figure 4: Micro-grating targets enable overlay to be measured in-die and can provide the local accuracy required for DPL (box in lower right is a simulation) Wafer Number Figure 5: Predicted 3-sigma overlay at the 32nm node relative to specification. The figure uses current technology node (65nm) composite factory data adjusted for ITRS scaling. The green bars represent stage 1 (which is consistently in spec) while orange bars represent stage 2 (which is consistently out of spec). Enabling Overlay Control for DPL DPL is up to three times more sensitive to overlay error due to the interaction of overlay with critical dimension. Consequently, overlay metrology must represent in-die misregistration accurately to enable the higher-order corrections required for DPL. To improve accuracy, overlay will be measured in the die using small grating-based targets (Figures 3 and 4) embedded in dummy-fill structures (logic) or in DFM-optimized areas (memory). This will result in more representative sampling, reduction in model residuals, and improved overlay correction. The yield benefits of in-die overlay metrology are already evident in the current generation of semiconductor technology, and these benefits are expected to increase monotonically as the industry approaches the 32nm node 1. Note that state-of-the-art immersion lithography tools have dual stages, so that dry metrology and wet exposure can be performed in parallel. Within the wafer, exposure uses alternating scan directions. These operations can produce wafer-to-wafer and field-to-field overlay error, respectively. In addition, immersion typically requires a water dispensing system with an air curtain for droplet containment. Rapid motion of the wafer under the lens may create inhomogeneous thermal conditions, resulting in unmodeled overlay error. Notwithstanding, overlay specifications for the most advanced 45nm lithographic technology are about 6nm for a single tool (26x33mm field). Overlay matching is 8-10nm, but DPL requires a specification closer to 3nm. As a result, tool and stage dedication may be needed for DPL. Figure 5 shows predicted 3-sigma overlay at the 32nm node relative to specification. Composite factory data for the current technology node were adjusted using ITRS scaling to make the comparison. Modern scanning exposure tools use two wafer stages: in Figure 5, the orange bars represent stage 1 while green bars represent stage 2. Note that stage 1 is consistently in spec while stage 2 is consistently out of spec. These disparities are not simple offsets. They arise from the variance of model residuals and may not be easy to correct. In the case of systematic overlay signatures, stage dedication may be a viable solution; however, this strategy comes with a productivity penalty. At 25 wafers per lot, the correct stage may present itself about 50% of the time, resulting in an additional productivity loss of 2%. This loss will be limited to DPL layers where stage dedication is necessary. Enabling CD Control for DPL DPL is much more sensitive to resist profile error when cycletime is forced down by performing the final etch directly after the second photo step. Part of the pattern is defined by a hard mask and part by resist. Consequently, resist profile control will be critical in order to match the result of the first patterning step. To improve resist profile control, three-dimensional focus-exposure windows can be created using data from 3D scatterometry. 2 Initially, we expect to measure bar structures in grating patterns and get width, length, and end-wall angle data that correlate strongly with focus and exposure (Figure 6). Later, as with overlay metrology, such interim methods may be supplanted by true in-die profile and shape metrology. 45

46 PattErning End WA 30nm MCD Length 30nm 5 30nm FEM - Overlap Process Window Overlap BF and BE Process Window MCD Length End WA MCD Length Exposure 3 2 MCD Width End WA Focus (nm) Focus (nm) Focus Wall Angle and Length and Width Process Window Figure 6: Robust process windows can be constructed from 3D scatterometry data, such as end-wall angle, length, and width of bars in a grating target. Spacer Etch Alternatives Several companies have developed and patented alternative pitch splitting methods based on sidewall spacer formation and etching. Such methods take some of the patterning burden away from lithography, but they also create a need for additional CVD, etch, clean, and inspection steps. In the simplest of cases, sidewall spacers are formed on each side of a sacrifi - cial structure that is then etched away selectively (Figure 7). The spacers become hard masks for subsequent etching of the underlying substrate (Figure 8). In this way, two structures are formed where one existed before. With respect to overlay, the structures are inherently self-aligned if the CDE of the sacrifi cial structure is zero. If the CDE is not zero, CD and overlay error are once again confounded. In addition, asymmetry in the spacer deposition or etch process can add incrementally to the overlay error, since 1 OLE = CDE ( CDE CDE ) 1 2 Figure 7: Simplifi ed spacer-etch alternative to DPL. A sacrifi cial structure (0) is formed, followed by spacer deposition and etch to create a left (1) and right (2) hardmask. Figure 8: After the sacrifi cial structure is removed, the pattern is etched. Although the pattern is self-aligned, overlay error is confounded with CD error of the sacrifi cial structure. For many designs, CD control may be an easier problem to solve. Although traditional methods for spacer CD measurement, such as TEM and SEM, have defi ciencies, scatterometry (SCD) has been shown to be an effective control methodology for spacers on gate structures 3. TEM cross-sections contain excellent profi le information, but the measurement is destructive, localized, and subject to human error in locating the material interfaces. SEM images contain very little profi le information, and the measurement is localized with poor defi - nition of the material interfaces and low sensitivity to small changes in spacer width. SCD, on the other hand, has the advantage of being a non-destructive, spatial averaging technique that provides excellent profile information and sensitivity. Simulations (Figure 9) show more than adequate sensitivity to detect sub-nanometer CD changes, and spacers have been measured down to dimensions of 4nm (Figure 10). Clearly, much of this work is directly applicable to spacer structures used for double patterning. Extensions of the SCD technology beyond simple oxide-nitride spacers to dual spacers 4 are promising since these are more complex structures and double patterning may require scatterometry models with a higher number of fl oating parameters. 6 Spring 2007 Yield Management Solutions

47 PattErning Alpha Beta D = 1nm Poly 300, , , ,0 700,000 D = 1nm D = 18nm D = 18nm Native Ox D Combo Film 1+ 2 GOX Si-Sub Native Ox 300, , , , ,000 Wavelength Figure 9: Simulation of spectroscopic ellipsometry data used for CD scatterometry. D is varied in 1nm increments showing high sensitivity for spacer metrology, especially in the UV. SE Spacer Width (Å) Y=1.0248x R 2 = Combo Film 1+ 2 SE Width Result (A) Linear Fitting Curve TEM Cross-section Spacer Width (Å) Figure 10: CD scatterometry results plotted against TEM measurements showing an R-squared value of 0.99 over spacer-widths ranging from 4 to 45nm. Recommendations for Success Practical interim solutions exist to support CD and overlay control in the development of DPL and its alternatives for the 32nm node and beyond. The following recommendations can increase the probability of success in double patterning: Implement grating-based overlay technology to gain accuracy and minimize overlay model residuals, so that 3nm overlay targets are achievable. Embed small grating structures in the device area where feasible. Implement grating-based 3D-CD scatterometry to measure shape and profi le parameters that support direct feedback of focus and exposure corrections to the litho cell. About 80% of CD variation is due to changes in effective focus and exposure conditions. Implement grating-based 2D-CD scatterometry to provide accurate feed-forward and feedback to the etch module. This method is critical for spacer-etch alternatives to DPL. The above solutions can be a source of accurate process metrics for enabling conjoint DFM and APC strategies. Moreover, if they can be leveraged for yield improvement and cycle-time reduction, standard factory economic models suggest gross margin benefi ts in the tens of millions of dollars per factory per year. Acknowledgement 2006 IEEE. Kevin M. Monahan, Enabling Double Patterning at the 32nm Node. Reprinted, with permission, from International Symposium on Semiconductor Manufacturing (ISSM) 2006 Conference. References 1. K. Monahan and U. Whitney, Enabling DFM and APC strategies with advanced process metrics, Proceedings of SPIE, vol. 6152, K. Hung, et al., Scatterometry measurements of line end shortening structures for focus-exposure monitoring, Proceedings of SPIE, vol. 6152, Ryan Chia-Jen Chen, et al., Application of spectroscopic ellipsometry for ultra thin spacer structure, Proceedings of SPIE, vol. 535, pp , V. Vachellerie, Gate spacer width monitoring study with scatterometry based on spectroscopic ellipsometry, in Characterization and Metrology for ULSI Technology 2005, pp Lithography Users Forum Sunday, February For more details and registration please visit

48 Patterning Improving Scanner Productivity and Control through Innovative Connectivity Applications Yuuki Ishii, Shinji Wakamoto Precision Equipment Company, Nikon Corporation Atsuhiko Kato, Brad Eichelberger Optical Metrology Division, KLA-Tencor Corporation Coupled with decreasing technology node budget allowances, alternative processing techniques are also shrinking overlay budgets. One source of overlay error is distortion matching between exposure tools. High order modeling of overlay error is proving to be an effective solution. This article shows how high order modeling of grid and distortion matching enabled overlay improvement of up to 50%. Improving overlay accuracy is now especially critical in semiconductor manufacturing. The ITRS 2005 roadmap indicated that overlay error should be halved compared to ITRS When analyzing the sources of overlay errors in semiconductor production, it becomes obvious that there are errors unmodeled by the conventional linear model. Figure 1 shows analysis of overlay in DRAM production. About two-thirds of the error is caused by the unmodeled error. These errors must be reduced in order to meet future requirements. The composition of some of this error belongs to high order terms related to exposure tool matching. To reduce these errors, high order modeling of grid errors and distortion errors can prove very effective. Grid errors are inter-shot position errors. Distortion errors are intra-shot position errors. For Nikon s exposure system, there are functions for Grid Compensation for Matching (GCM) 1 and Super Distortion Matching (SDM). GCM can adjust inter-shot exposure position error by using the coefficients of high order modeling. SDM can adjust intra-shot distortion error by adjusting aberration fingerprint and also by stage control. Figure 2 shows an example of hidden overlay errors. This data shows intra-shot distortion error. Traditional overlay sampling, within the circles, confirms that the Advanced Process Control (APC) system is controlling the overlay to about zero. Current APC systems utilize linear models for overlay control, but other errors can be seen across the exposure field, which provides evidence of non-linear effects. These errors typically go unnoticed and are hidden from conventional sampling schemes. These errors can be significant and amplified by a mix and match exposure tool environment. This article explores the value that may be realized by having a direct data link between the exposure tools and overlay tools in terms of productivity and overlay control Unmodeled errors BiB X BiB Y Impact of process Metrology Figure 1: Sources of overlay error seen in typical DRAM production. Figure 2: Hidden overlay errors are amplified in a mix and match exposure tool environment. 48 Spring 2007 Yield Management Solutions

49 Patterning Connectivity The Grand Picture KLA-Tencor and Nikon are investigating the feasibility of a solution to minimize the impact of mix and match on overlay error. The solution would involve a direct data link between Nikon exposure tool systems and KLA-Tencor s advanced overlay system. In addition to improving mix and match performance, several other useful applications are expected to be achieved with a direct scanner-metrology link (Figure 3). Nikon Scanner NSR TM AEC Applications Automated PM PM wafers run like production Shorter PM time Stage/optics tuning One example is the direct exchange of coefficients for mix and match from KLA-Tencor s database of overlay data. The mix and match coefficients will improve run-to-run overlay performance for the exposure tool. The benefit of this implementation will be improved overlay performance and reduced rework caused by mix and match errors. Another is smart sampling that can be achieved by sharing Enhanced Global Alignment (EGA) 2 results. EGA is an alignment procedure done before exposure for a lithography tool and generates data pertaining to the alignment confidence of each wafer. This data can be very helpful in determining which wafers to select for APC feedback and which wafers should be considered for an accurate disposition. Sharing this data with the overlay tool would allow the wafer slot sampling to be dynamically optimized run-to-run. The main benefit is to provide the most relevant data for process control, and yet find the most relevant wafers that would require potential rework. From the periodic maintenance (PM) perspective, common ownership of the PM data will provide numerous ways to Higher Litho Process Accuracy Tighter Equipment Control Direct Data Exchange Higher Productivity Better Tool OEE KLA-Tencor Archer TM Overlay Metrology APC Applications Mix and match Adaptive sampling More APC correctibles Figure 3: Schematic of the Nikon and KLA-Tencor connectivity solution. Tighter connectivity between Nikon and KLA-Tencor tools not only leads to improved overlay control but also improved exposure tool productivity and overall utilization. optimize productivity within the scanner fleet. Utilizing a history database of PM data will provide opportunities for an algorithm which will assist in optimizing the PM frequency. History data can also be used in the event of unscheduled maintenance to decrease the time to repair. Both of these benefits will optimize the productivity of the exposure tool. Inter-shot and Intra-shot Overlay Error Inter-shot error is the same as grid error. Variation in grid error can be attributed to wafer thermal expansion or stage mirror bow. This grid error, presented by these effects, falls into the categories of linear and non-linear error. Linear error is typically measured during the run-to-run alignment sequence before exposure using the exposure tool s EGA system. Another approach is to use a send-ahead wafer on which the data is measured and modeled by a metrology tool with linear corrections feedback to the remainder of the lot. The sources of non-linear error are typically process-induced wafer deformation, stage grid matching, and wafer thermal effects. Regardless of the above approaches, it is difficult to characterize the non-linear effect on every wafer and yet still maintain exposure tool productivity. One component of the non-linear error that can be compensated for is grid matching. This offset between scanners is normally stable from wafer-to-wafer over time. Nikon s exposure tool has GCM, which provides the ability to utilize high order models to improve grid performance. Intra-shot error is the same as distortion error. It is normally caused by distortion matching between exposure tools. As with inter-shot (grid) error, intra-shot distortion error comprises both linear and non-linear errors. Linear errors are typically compensated for by EGA and APC, but there are additional errors which cannot be fit by linear models. These errors are significant enough and will require compensation for in future technology nodes. Non-linear errors are caused by lens aberration, tool to tool distortion differences and illumination matching. For these errors, Nikon s exposure tool utilizes SDM as a means of compensating for shot distortion by high order modeling. Mix and Match Overlay using GCM and SDM Figure 4 shows an example of mix and match overlay improvement using GCM and SDM. In total, overlay error was improved from 22nm (3s) to 13nm (3s). This data was acquired by overlay matching between a KrF scanner and Nikon s S207D scanner. For the matching test, a special reticle, which has dense sampling of overlay measurement points within the field, was used. For the analysis of these improvements, grid error (shown in figure 5) is improved from 13nm (3s) to 7nm (3s) using GCM function. Furthermore, distortion error (figure 6) shows improvement from 13nm (3s) to 8nm (3s). Table 1 shows overall improvements using this adjustment procedure. Today, these corrections can be done on non-product wafers only. However, this assumes that process induced shift and/or distortion will not fluctuate. In future technology nodes, 49

50 Patterning Initial 3σx = 21.9nm 3σy = 16.6nm With GCM & SDM 3σx = 12.9nm 3σy = 11.9nm Initial Data X Y X Y (a) Offset Compensated in recipe offset (b) Grid matching (3σ) By GCM (c) Distortion matching (3σ) By SDM (d) Linear error residuals (3σ) Compensated in P.P. offset (e) Other random errors (3σ) Total ( m +3σ ) abs(a)+sqrt(b 2 +c2+d 2 +e 2 ) With SDM & GCM Improvement Method Figure 4: Overlay improvements using GCM and SDM. Table 1: Benefit summary of SDM and GCM. Before GCM Correction After GCM Correction PM Item PM wafer arrives at scanner Production Application Production wafers arrive at scanner Scanner exposes PM reference wafer with associated matching Scanner requests matching information Overlay tool returns information Overlay tool performs distortion metrology Scanner makes appropriate corrections for matching Distortion data stored in database Scanner exposes the wafer Figure 5: Grid error improvements. Improved overlay control Figure 7: Mix and match adjustments between Nikon and KLA-Tencor tools. Summary and Future Work Initial Figure 6: Distortion matching improvements. on-product overlay feedback including higher order terms will become necessary. Scanner-metrology linking will play an essential role in automating this procedure, and in doing this while running production lots. Mix and Match Flowchart With SDM Figure 7 shows a flowchart of mix and match adjustments. Distortion data is acquired at the PM timing using a reference wafer and using an associated matching reticle. The distortion data is stored in the database server. When the production wafer arrives at the scanner, the scanner requests matching information (i.e. coefficients for SDM and GCM) and the server returns the information. Then the scanner makes appropriate corrections for matching, with the end result being improved overlay performance. Another key aspect and benefit of the proposed direct link is that it enables the automatic analysis and run-to-run compensation for distortion matching. The value created by improving the connectivity between the metrology tool and exposure tool has been studied. By using this direct data exchange as a method to optimize the use of high order fitting, one can expect improved overlay, reducing overlay rework and dynamic optimization of sampling. KLA-Tencor and Nikon are working to provide an automatic feedback system of high order compensation to the exposure tool directly from metrology results. This feedback system can provide adjustment of coefficients of grid and distortion for periodic maintenance. Automating this process will not only lead to improved overlay control but also improved exposure tool productivity and utilization. Acknowledgement Yuuki Ishii, Shinji Wakamoto, Atsuhiko Kato, and Brad Eichelberger, Improving Scanner Productivity and Control through Innovative Connectivity Application, in Metrology, Inspection, and Process Control for Microlithography XX, Proc. of SPIE 6152, (2006). References 1. K. Takahisa, Y. Ishii and N. Tokuda, Induction of New Techniques for Matching Overlay Enhancement, Proc. SPIE, Vol.4346, pp , T. Umatate, Method for Successive Alignment of Chip Patterns on a Substrate, US Patent, 4,780,617, Spring 2007 Yield Management Solutions

51 Product News Archer 100 Advanced optical overlay metrology for 45nm design rules Archer 100 Benefits Signifi cantly reduces TMU to satisfy tighter overlay error budgets for 45nm design rules Enabling technology for nextgeneration immersion and double patterning lithography Improved tool utilization and CoO increases productivity by 20% over previous generation Micro-grating (µaim TM ) targets increase process robustness and higher-order overlay control Enhances measurement of lowcontrast targets; especially benefi ts HVM memory applications Pattern-limited yield is a key challenge for semiconductor manufacturers at the 45nm node and below due to tighter process tolerances and increasing chip density. Overlay is especially critical, because as error budgets continue to shrink below 30% of design rules, existing overlay tools can no longer meet current total measurement uncertainty (TMU) requirements. The Archer 100 overlay control system, based on the industry proven Archer platform, meets stringent performance and cost of ownership (CoO) requirements for 45nm design rules. Redesigned optics (better SbS matching), tighter stage tolerances (higher repeatability), new imaging system (improved SNR, lower pixel distortion), and advanced illumination modes (reduced tool induced shift) combine to improve TMU specifications by more than 30% over existing tools. These features, along with the shorter MAM time, enhanced algorithms and built-in diagnostics deliver the high levels of process robustness and productivity needed to overcome tighter overlay error budgets. Leveraging KLA-Tencor s patented AIM technology and Archer Analyzer software, the Archer 100 enables in-field metrology and analysis for advance dispositioning and higher-order overlay control. A new recipe optimization methodology (ARO) enables relatively unskilled operators to quickly and automatically create high quality recipes offline, thus freeing up valuable engineering resources and improving ease of use and overall tool utilization. Especially useful for immersion lithography, new micro-grating overlay technology leveraged on the Archer 100 together with Archer Analyzer provides accurate, robust measurements, helping to minimize overlay model residuals and achieve higher order overlay control. Questions about how the Archer 100 can address a specifi c use case or challenge? Please contact Eitan Herzel at eitan.herzel@kla-tencor.com Automatic Recipe Optimizer (ARO) enables faster, easier recipe creation and optimization Recipe Database Manager (RDM+) reduces setup time, and increases reliability, recipe success rate and traceability of measurement recipes Archer 100 Remote Client ARC ARO RDM+ ARO ARO Host Remote Client ARO The new RDM+ software enables offl ine access to a centralized database to leverage previously proven recipe components. The waferless, imageless, and Automation Recipe Creation (ARC) modes enable full automation of the recipe creation process across all KLA-Tencor overlay metrology systems. Wafer lot dispositioning and stepper correction data from Archer Analyzer helps lithographers to reduce rework and yield loss. 51

52 Product News Puma 91xx Series High performance darkfield inspector, for benchmark sensitivity at production throughputs Increasingly complex technical and economic challenges continue to emerge at 65nm design rules and below. Shrinking geometries and new device materials require increased resolution and proven noise suppression capabilities in patterned wafer inspectors. The Puma 91xx series of darkfield UV patterned wafer inspectors provides high sensitivity at high production throughputs for all layers. Enhanced data rates and the innovative Streak technology deliver fast and efficient defect detection on array and logic structures. Noise suppression capability is unparalleled with grazing-angle illumination, selectable polarizations and true programmable Fourier filters. A range of pixel combinations balances the sensitivity and flexibility requirements of a broad application space from tool monitoring to advanced etch. Built on the established and widely adopted Puma 9000 platform, the Puma 91xx series offers a 1.7x throughput increase, enabling higher sampling or improved sensitivity to control critical yield excursions. The new FAST algorithm and Brightfield Recipe Import make recipe setup quick and simple, improving productivity. Platform commonality with KLA-Tencor s 23xx/28xx broadband brightfield and es3x e-beam inspectors enables rapid production integration. With enhanced sensitivity and speed, plus reliable production performance, the Puma 91xx series meets the cost and performance requirements of advanced defect monitoring. Questions about how the Puma 91xx series can address a specifi c use case or challenge? Please contact Matthew McLaren at matthew.mclaren@kla-tencor.com Puma 91xx Series Benefits Highest available darkfi eld sensitivity at production throughputs Flexibility to meet sensitivity and throughput requirements for the broadest range of applications from tool monitoring to advanced etch Highest range of production throughputs in a single tool Improved Fourier fi ltering for better sensitivity at array/ periphery interfaces Quick and simple recipe setup with the new FAST algorithm and platform commonality Automatic defect classifi cation with ido improves binning performance and reduces time to results Throughput ~1.7x increase in throughput Increased Sampling Puma 91xx Puma 9000 Extendible architecture protects capital investment Higher Sensitivity sl5 sl8 sl10 sl15 sl20 sl40 sl60 sl70 Sensitivity The Puma 91xx provides increased sampling, higher sensitivity or lower CoO. A range of inspection pixels provides the fl exibility required to cost-effectively inspect the broadest range of applications. Puma is utilized as a cost-effective void monitor by providing high throughput, low nuisance capture of STI voids on 90nm DRAM devices.* * Reference: U. Streller et al, Monitoring Yield-Critical Defects in DRAM Structures, Semiconductor International, July Spring Winter 2007 Yield Management Solutions

53 VisEdge CV300 Wafer-edge inspection system for increased yield VisEdge CV300 Benefits Unique optical surface analysis technology offers higher sensitivity to defects of interest (broad defect capture capabilities) Powerful, rule-based classifi cation software provides objective data for process control Simultaneous multi-channel signal acquisition eliminates repeat scans Offl ine image storage and re-analysis for recipe fi ne tuning Common platform wafer handling and factory automation interface creates robust, productionworthy inspection system With many advanced IC manufacturers facing an average of 10-50% greater yield loss at the wafer s edge relative to their best yielding region, especially at 300mm, a comprehensive inspection strategy that includes advanced edge inspection is critical. The VisEdge CV300 system is the semiconductor industry s first inspection solution to meet the full range of wafer-edge inspection requirements in a production environment. Built on a highly extendible platform and using KLA-Tencor s proven Optical Surface Analyzer (OSA) technology, the tool s combination of unique optics design and advanced defect classification allows IC manufacturers to overcome the limitations of existing edge inspection techniques and enables broader capture and better distinction of defect types. With OSA technology at its heart, VisEdge offers the unique advantage of complete wafer-edge scanning and capture of both macro- and micro-based defects with high sensitivity. Unlike traditional edge inspection systems, the system s simultaneous multi-channel signal acquisition technology combines four detection methods (scatterometry, reflectometry, phase shift and optical beam deflection) to achieve greater accuracy and purity in capturing defect sources, including small particles, stains and film delamination, while eliminating the need for repeat scans. Advanced rules-based defect classification software with robust signal enhancement and smart filtering routines eliminates edge background noise a problem worsened by the severe topography at the wafer s edge that impairs the detection capabilities of other inspection techniques. This capability highlights defects of interest and enable fast identification of defect types. KLA-Tencor s OSA technology has been proven in production for advanced inspection applications with more than 300 installations worldwide. Questions about how VisEdge CV300 can address wafer edge yield challenges? Please contact Frank Burkeen at frank.burkeen@kla-tencor.com Multi-sensor imaging in VisEdge, particularly specular imaging, can distinguish between open and closed blisters on the wafer edge region (popped blisters appear white, un-popped appear black). Phase channel imaging, part of VisEdge s multi-channel approach, can reveal signifi cant fi lm fl aking and peeling in the wafer edge region. 53

54 Product News PROLITH 10 Advanced lithography optimization with powerful predictive OPC capability Taking a design from concept to production, on the newest technology node, has never been more complicated. PROLITH 10 addresses your most advanced lithography challenges, from model-based optical proximity correction (OPC) application, through mask manufacturing, to the fab fl oor. Using PROLITH 10, lithographers can optimize technologies such as focus blur, immersion, polarization and Jones pupils, as well as EUV, 193nm, 248nm and other optical lithography processes and materials. The new PROLITH-based OPC (PBOPC) capability enables early OPC learning and development for resolution enhancement technology (RET) engineers and mask data preparation (MDP) engineers working with designers to complete new product designs for the next technology node, even before a mature process exists. Unique PROLITH features include a library of expertly calibrated resist fi les, mask defect printability analysis, and dual EMF algorithms. The ever-growing library of resist fi les available with PROLITH includes many of the new resists being considered for immersion lithography, as well as resists for dry 193nm, 248nm and i-line processes. PROLITH 10 further enables analysis of pattern defect printability from reticle inspection systems such as TeraScan, and helps you determine mask defect dispositioning rules and specifi cations in collaboration with your mask supplier(s). Also, access to both rigorous coupled-wave analysis (RCWA) and fi nite-difference time-domain (FDTD) algorithms allows you to rigorously determine imaging effects, as well as to select the most suitable mask technology for your roadmap and specify the mask manufacturing tolerances for a chosen technology. As the semiconductor industry s most trusted lithography development tool, PROLITH 10 helps you accelerate design-to-production cycle times, increase overall tool utilization, rapidly implement new process technologies, and maximize yield. Questions about how PROLITH can solve your advanced lithography optimization needs? Please contact Chris Sallee at chris.sallee@kla-tencor.com PROLITH 10 Benefits Gives development teams the highest level of predictive accuracy for successful next-generation development and production ramps Enables what if exploration of the effects of processes, materials and tools on lithography results over a wide range of conditions including immersion lithography, double-patterning techniques, and EUV Delivers lithography process optimization information in seconds, speeding process development Optimizes process windows quickly and cost effectively Determines effects of the most advanced stepper technologies Resist images in 3-D using expertly calibrated resist fi les. The PROLITH library of resist fi les comprises the newest resists being considered for both dry and wet lithography. Powerful PROLITH-based OPC (PBOPC) delivers high predictive accuracy for successful next-generation design and production ramps. 5 Spring Winter 2007 Yield Management Solutions

55 Surfscan SP2 XP Unpatterned Surface Inspection System Surfscan SP2 XP Benefits Enables fi nal surface qualifi cation of traditional and engineered substrates Meets 45nm incoming quality control (IQC) specifi cations Separates intrinsic defects from reworkable defects, for fewer scrapped wafers Provides 20% to 50% higher throughput, depending upon the operating mode At the 45nm node, defect requirements are significantly tighter and encompass more types of defects. Wafer suppliers require expanded detection of all defect types early in the manufacturing process. For prime wafers, the Surfscan SP2 XP system detects crystalline defects such as faceted pits (air pockets or air bubbles), and separates them from reworkable defects such as faint scratches and particles. The system also detects emerging defects such as orange peel, slurry residue, watermarks, and surface roughness. For epi wafers, the system separates killer epi stacking faults (ESFs) from re-workable residues. For SOI wafers, killer voids can be discriminated by using the dual-incidence scanning capability and new algorithms. The system s enabling technology includes the addition of a brightfield channel with differential interference contrast (DIC) capability. The brightfield/dic channel promotes capture of large and flat defect types, and, together with the oblique- and normal-incidence darkfield channels, aids in defect separation. When defect types can be separated into reworkable and non-reworkable categories, wafer manufacturers can benefit from fewer scrapped wafers and provide their customers with improved incoming substrate quality. Questions about how SP2 XP enables cost-effective production of defect free wafers for 45nm? Please contact William Shen at william.shen@kla-tencor.com Overcomes the critical sensitivity challenge in the gate module at the 65 and 45nm nodes by using short-wavelength UV illumination Features extendable architecture for multiple technology nodes Normal Narrow Size (µm) SOI Void Classification by Normal Narrow/ Oblique Wide Void 4.5 Residue 4 LPD Void Oblique Wide Size (µm) Normal Narrow Size (µm) EPI Stacking Fault Classification by Normal Narrow / Oblique Wide Oblique Wide Size (µm) Stacking Fault Residue LPD Stacking Fault Comparison of defect sizing from the Normal-Narrow and Oblique-Wide channels of the Surfscan SP2 XP. For SOI wafers, voids are clearly distinguishable from particles and other fall-ons. Comparison between Normal-Narrow and Oblique-Wide sizing distinguishes ESFs from other defect types for epi wafers on the Surfscan SP2 XP. 55

56 The Last Word Sub-32nm Nodes Bring Megabucks Lithography Katherine Derbyshire For years, EUV skeptics (myself included), have raised their eyebrows at the likely cost of the technology. More recently, however, it has become clear that there are no inexpensive choices at the 32nm and smaller nodes. In fact, EUV s extendibility to still smaller dimensions may actually make it the most cost-effective approach to advanced lithography. Not that EUV is inexpensive, by any definition. No pricing is yet available for first-generation EUV steppers, but estimates so far land well north of US $50 million. Moreover, EUV steppers are likely to be astonishingly expensive to operate. For instance, instead of a laser light source, it uses plasma generated by heating a target with a laser beam. The net efficiency is the product of the laser efficiency, times the efficiency of plasma generation, times the fraction of emitted radiation that actually lies within the desired wavelength range. Conversion efficiencies vary depending on the source design, but capturing 5% of the laser power as useful EUV radiation is considered good. A 100W source would likely require a 2kW laser. Nor is a 100W source necessarily adequate for production use. Source power is measured at the collector element, the point where EUV radiation enters the imaging optics. Yet EUV optical elements are relatively poor reflectors, absorbing a significant fraction of the light that reaches them. Actual illumination at the wafer is likely to be significantly less. To achieve throughput of 100WPH, a photoresist with 5mJ/cm 2 sensitivity will need >115W of power at the system s intermediate focus. A 20mJ/cm 2 resist would require >200W of source power, potentially requiring a 4kW laser to produce the plasma. In contrast, conventional 193nm lasers typically deliver 60W of power to the photoresist in 10mJ pulses. Not only will EUV resists need to be sensitive to relatively weak illumination, they must also deliver superior etch resistance and line edge roughness in order to achieve the desired dimensions. High sensitivity and low line edge roughness are an unusual, and expensive, combination. EUV masks, meanwhile, depend on a completely new substrate with no supporting infrastructure behind it. Before we dismiss EUV technology, though, let s look at the alternatives, remembering that only EUV has shown it can print features beyond the 32nm node. High index immersion lithography, for example, uses both lens element and immersion fluid with high refractive indices, to achieve numerical apertures that water immersion cannot. These larger apertures increase the effective resolution of the lens. High index immersion sounds like a natural extension of water immersion, but it poses substantial problems. Lutetium aluminum garnet (LuAG), the most likely lens choice, is new to 56 Spring Winter 2007 Yield Management Solutions

57 The Last Word semiconductor manufacturing. It has been used in telescope applications, but is an intrinsically birefringent and crystalline material. Those who remember the industry s struggles with 157nm lithography which required calcium fluoride optics are probably breathing a sigh of relief that high index immersion only requires LuAG for the front element. Still, development of the LuAG manufacturing and lens making infrastructure will likely require substantial investments. Operating budgets, meanwhile, must absorb the cost of the high index immersion fluid. What this fluid might be is not yet known; companies like DuPont and JSR have offered evaluation samples of several proprietary chemistries. Any fluid, however, will have to meet stringent purity and resist compatibility requirements. Even assuming the fluid can be recycled after each wafer pass, IMEC s Geert Vandenberghe expects the immersion fluid alone will add US $1 per wafer pass to lithography costs. The third alternative, double patterning lithography (DPL), can at least use current generation exposure equipment. Superficially, it seems to be the least expensive choice. Yet, as the name implies, DPL requires two exposure passes for each mask level, an immediate and substantial throughput hit. Some process schemes also use an additional resist coat and development step to etch both halves of the pattern into a hard mask before transferring it to the wafer. Finally, DPL requires two masks per device layer. Granted, these masks can use somewhat relaxed dimensions and can avoid aggressive OPC. On the other hand, attempts to extend DPL to smaller features are likely to erase the mask simplicity advantage. Overlay errors between the two masks becomes critical, and also contributes to CD error and CD variability (Please see Enabling Double Patterning at the 32nm Node, page 44). Despite its limitations, DPL must be considered the preferred technology at this point. Among other things, it requires manufacturers to proceed with process development without waiting for capabilities that only exist in alpha tools. Still, DPL will not protect manufacturers from the most serious challenge to lithography scaling: cost. Katherine Derbyshire is writing an introduction to IC manufacturing, tentatively titled Semiconductor Manufacturing in Nontechnical Language. She has engineering degrees from the Massachusetts Institute of Technology and the University of California, Santa Barbara. She founded Thin Film Manufacturing, a consulting firm helping the industry manage the interaction between business forces and technology advances, in You can reach Katherine at kderbyshire@thinfilmmfg.com How big are EUV systems likely to be? ASML s Alpha Demo tool comes with its own gantry crane to open up the vacuum chamber. Image does not show the reticle handling system (not yet installed) or the source. Image courtesy of IMEC. 57

58 PATTERNING PRECISION BE MARKET READY LITHO SOLUTION: OVERLAY CONTROL Traditional overlay metrology can t keep pace with today s ever-shrinking specs. Stay out front with KLA-Tencor s litho control solutions. Don t miss crucial pattern placement errors. Our unique, robust metrology technology gives you the most precise overlay measurements possible. So you can make smart decisions and quick corrections. And, by maximizing yield and reducing re-work, your total cost of ownership goes down. Along with your time to market. Your patterning process control resource

59 MARCH 7-9 Diskcon Asia Pacific, Singapore MARCH SEMICON China, Shanghai, China APRIL SPIE Photomask, Yokohama, Japan APRIL Blue 2007, Hsinchu, Taiwan MAY CS Mantech, Austin, Texas MAY NTSI/Nanotech, Santa Clara, California MAY Society for Info Display, Long Beach, California JUNE 4-6 SEMI Expo CIS, Moscow, Russia JUNE ASMC, Stresa, Italy JULY SEMICON West, San Francisco, California COME VISIT KLA-TENCOR AT IMPORTANT INDUSTRY EVENTS 2007 For more details and registration for KLA-Tencor events, please visit 59

60 BE AGILE Respond quickly to a changing market KLA-Tencor Corporation