Wafer Backside Inspection Applications In Lithography

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1 Wafer Backside Inspection Applications In Lithography Kay Lederer, Manhias Scholze, Infineon Technologies 300, Dresden Ulrich Strohbach, Infineon 200. Dresden Andreas Wocko, Thomas Renter. Angela Schcenauer, KLA-Tencor, Dresden, Germany Abstract As the Semiconductor Industry starts to ramp its 1 lonm production capacity I the need for optimal uniformity across the wafer surface becomes a very important topic in lithography. Due to the tightening of depth of focus requirements the process window required to be able to print the required structure leaves little or no room for any localized deviation in the wafer uniformity. For 300mm semiconductor device manufacturing, this resulted in the use of double-side polished, so-called super flat, wafers. This paper will discuss methods to identify yield relevant defects on the wafer backside without having to sacrifice wafers. It is based on recent studies carried out at both Infiieon Semiconductor 200 and 300mm Fabs in Dresden to characterize the need and the effectiveness of wafer backside defect inspection using the BSIM (Back Side Inspection Module) on the Surfscan 8 SPl. Firstly, we focus on some general topics of setting up a backside inspection for photolithography. We show how to determine the required sensitivity in order to capture the defects of interest and to provide quantitative information on the number of wafers affected. We then discuss two studies in detail: The 1 study was an investigation into the quality of the backside of 300mm wafers pre and post lithography throughout the manufacturing process. The 2 study describes how focus spots on the front side of 200mm wafer were correlated to damage on the backside and how the root cause was identified. Finally, we draw an outline to requirements that we believe wil he an essential part of automatic backside inspection in the forthcoming future. 1. Introduction In contrast to the well-established bare wafer inspection strategies, semiconductor manufacturers are still in the early learning stages of implementing backside inspections of silicon wafers. Both inspections are based on the same methodology - a dark field illumination of the inspected wafer and a subsequent detection and analysis of the back-scattered light. The major Figure 1. Comparison of hare wafer differences between both inspections inspection to backside inspection. are depicted in figure /03/$17.00 WO03 IEEE IEEElSEMl Advanced Manufacturing Conference

2 Backside defects in the form of particles or topography is highly relevant to photolithography processing. Particularly in 300mm photolithography, where super flat wafers are used, such defects reduce the surface uniformity and lead to undesired effects on the exposure chuck. The two most common effects are focus spots and vacuum failures. For critical lithography layers with small process windows the former effect has a direct impact on the yield of the manufacturing process. The later impairs manufacturing efficiency as it causes downtime of manufacturing tools. Moreover, any sort of serious backside contamination often results in time-consuming cleaning procedures of the exposure tool chuck. The experience gathered so far shows that 200mm and 300mm manufacturing share largely the same backside issues. Effects that a wafer s backside can have on the devices built-up on the front side are largely known, but have not heen systematically characterized. This is due mainly to having to scrap wafers with suspected backside problems by placing them upside down to conduct a thorough inspection of the defects. This reverse side inspection damages the devices on the front side and, possibly, contaminates the inspection tool. In our studies, we used the Surfscan@ SPI which is the industry standard for un-patterned wafer inspection. With the introduction of the Backside Inspection Module (BSIM) as an integral part it is now possible to inspect the backsides of patterned wafers in an automated and nondestructive way. 2. Methodology The first step to implementing backside inspection into a fab is to analyze the surface quality characteristics of the wafer backside and determine the required sensitivity for capturing process tool fmgerprints. In our case, this was done by depositing Polystyrene Latex Spheres (PSLs) onto the backside of a testwafer and adjusting the recipe parameters to achieve at least a 3:1 SignakNoise ratio.[*] This procedure is illustrated in figure 2. Figure 2. Example of sensitivity analysis using various PSL sizes on a polished wafer as measured on sp1 The investigation into the quality of the backside of 300mm wafers was conducted on process wafers before and after lithography steps. The wafer backsides were inspected using a SPImB laser scanning system with the Backside Inspection Module (BSIM). The BSIM enables product (patterned) wafers to be flipped and measured. Double-sided polished wafers can be treated pretty much as hare Si wafers just with a higher defect threshold value. This value is dependent on the desired resolution in order to detect tool fmgerprints and data management limitations. Figure 3 shows the effect of the defect threshold has on the resolution of a wafer handler fmgerprint IEEWSEMI Advanced Manufacturing Conference

3 For this study, the optical configuration used on the SP1 included the oblique incidence mode and P-U-U polarizations. Defect thresholds were between 0.5 and 1.0pm. The next step is to create a database of tool fingerprints from all the process tools: This is usually done during the tool qualification period. With the BSIM option the number of test wafers can be reduced as the same wafers can be used for front (PwP) and backside contamination tests. 0.5pm 0.7p I.Okm Figure 3. Effect of defect threshold on signature resolution. The goal of the 2"d study was to identify the root cause of systematic focus spots detected on the pattemed wafer. This study was conducted on 200" process wafers taken at various stages in the front end of the manufacturing process. The front sides of the product wafers were measured in-line on an AIT-II Double Dark-field Laser Scanning System. The review and characterization of the shape and size of the defects was canied out on a CRS Con-focal microscope. Off-line data analysis such as correlation between front- and backside defects was done using Klarity Defect software. The backsides were measured on an SPlDU with BSIM capability. The SPloLs has the same functionality as the SPl*' for dark field measurements, but provides increased overall sensitivity. For rough 200" wafer backsides, the best results were obtained using S polarization for both the incident light and dual (wide and narrow) collection channels. In order to further suppress background scatter (noise) and enhance the SignabNoise ratio, a 20 or 40 degree aperture was employed. The defect threshold was set between 0.2 and 0.3pm. 3. Results and Discussion 3.1. Characterization of backside properties on 300mm "super flat" wafers. For this purpose, we created one recipe for pre and post Lithography inspections maintaining its sensitivity to typical signatures. Three lots were flagged for inspection at specific critical lithography steps. 100% of the wafers were measured before and after the lithography process on the SPl BSIM using the same recipe. The lot results were mirrored on the tool and sent to the fab-wide defect database in KLA-Results Format. Figure 4. Pre-lithography backside defect counts (adders before lithography green) IEEWSEMI Advanced Manufacturing Conference

4 wafers that were not handled as often (Figure 7, right). Thus, the baseline defectivity is determined and process excursions may he readily detected. Figure 5. Defect added in lithography The data analysis revealed that the backside defect count added 1.0 the wafers between adjacent lithography steps (Figure 4) is considerably higher than the count added during lithography processing itself (Figure 5). Furthermore, we observed that the backside defect count steadily increases throughout the manufacturing process on all lots. It was also found that there is a dependency of the defect density on the wafer position in the lot. The first wafers tend to have a higher backside defect count than the rest, followed by those wafers that are handled more frequently during the process flow. Figure 6. Defect Count by Wafer Position in Lot This tendency (Figure 6) was seen on all lots at each inspection point. It can he interpreted in terms of a cleaning effect that the first wafers in a lot exert to production tools. Overlaying the backside defect maps of all measured wafers (Figure 7, left) shows a considerably higher backside defect count than the stacked defect maps of Figure 7. left: Typical handling wafer; right: normal wafer 3.2 Description of the focus spot problem Systematic focus spots had been identified through patterned-wafer inspection and manual classification. Due to the defect sipature across several layers being in the exact same position and the characteristics of the focus spots it was presumed that backside contamination could be the root cause. Since the focus spots were visible at multiple layers the actual source was not immediately obvious. Thus, a tool commonality study was conducted, hut did not reveal a clear candidate. Finally, a systematic investigation of backside defects, using the SP1 with BSIM, and their correlation to the front side, revealed the root cause of the problem several wafers with the specific signature were identifed at various steps throughout the process. These wafers were then measured on the SP1 with BSIM in the High Sensitivity (HS) mode. The defect result files were mirrored using software on the SPI and transferred to the defect database for analysis. The backside wafer maps all show distinct wafer handler signatures, which could be compared to the fab s previously established database of process tool fingerprints (wafer maps) IEEWSEMI Advanced Manufaciun ng Conference

5 a) b) C) Figure 8. a) SPI map (chuck signatures, cwrdinates mirrored); b) front-side, pattemed-wafer inspection; c) Overlay results of common defects. The patterned-wafer maps were overlaid with the mirrored SPI wafer maps and the common defect identified for further investigation (Figure 8). They show the extraction of the relevant backside defects using the data mirroring and front-to-back overlay process described above. The wafers were then reviewed to determine size, height and type of the defects. It was identified that the common defects were holes caused by damage to the silicon on the backside of the wafers, as shown in figure 9. - ~ Fieiirc 9. Omicdl ICRSJ inuces of rhe backside holes responsible for the front side focus problem I y The defects reviewed were typically several microns in size and depth. It was concluded that this damage was the cause of the focus spots. A comparison of the inspection wafer maps with the process tool finger print catalogue identified the responsible wafer handler type. It was also determined that several handlers of this particular type were damaging the wafers which explained why the tool commonality study was not successful in this case. By studying the defect mechanism it was determined that the defects were also being enlarged through the subsequent process steps, thus increasing the impact of the defects on the devices on the front of the wafer. Once the source was identified and the defect mechanism understood, a simple modification to the wafer handler solved the problem. A yield correlation conducted showed an impact of 1-2% for an affected wafer over a ten-week period until the root cause was futed. 4. Going forward with backside inspection The ideal scenario is to prevent backside contamination from causing a problem in the first place. As we have seen contamination is present at all layers, but that most of the time is not yield relevant, making it difficult to say when to take corrective action and when not. Simply adding a clean can become costly and not all defects can be rem~ved..~ Scratches and pitting can sometimes be made larger by the cleaning process. A good place to start monitoring backside contamination is either at the most critical lithography step or the step that has the most focus spots. As with traditional pattern wafer monitoring only a sample of wafers can be inspected and -a strategy should include control and base line reduction program^.'^' monitoring excursion defectivity IEEWSEMI Advanced Manufacturing Conference

6 4.1 Prevention of Focus Spots Pre-litho - Backside Inspection: The goal here is to determine whether there are large random backside defects on the wafers that could cause a problem during the lithography process and trigger corrective action before the wafers reach the exposure tool. A sample of 5 to 10 wafers is taken per lot depending on defectivity level and variability. Random defectivity should be separated from tool fingerprints signatures and large particles from small particles. A backside scrub would then only be triggered when large, random defectivity goes out of specification to avoid tool abofis and random focus spots. The data is sent to the defect database for further analysis as systematic focus spots may be caused by damage and therefore cannot be removed by a clean. Figure 10 shows the decision flow involved to initiate a backside scrub on contaminated wafers. Post Litho - Front side/backside Inspection: Here, the aim is to identify whether focus spots are generated during the lithography process and to trigger appropriate corrective action such as a chuck clean on exposure tools and rework of the affected wafers. The inspection is carried out on macro or micro inspection tools capable of detecting focus spots using the same wafers as above in order to be able to do pre and post comparisons. The focus spots are separated from other defect types and trigger a backside inspection of affected wafers based on number of focus spots. The data is sent to the defect database to be overlaid with the mirrored backside wafer maps from the pre-litho inspection step I--/ ,.....k ;qqkg....,... Figure 11. Decision flow to initiate corrective actions based on number of focus spots. Figure 10. Decision flow for backside cleaning pre-lithography 4.2 Wafer Backside Signature Analysis We have seen that the particle or defect signatures on the wafer backside are key to identifying the root causes of a particular issue. The next logical step is to automate what is currently being IEEWSEMI Advanced Manufacturing Conference

7 done manually. The difficulty lies in being able to separate the individual signatures from each other and automatically classifying the signatures as such and not just as clustered Investigations are currently being carried out to determine the best methodologies in implementing spatial signal analysis in a production environment. However the signatures alone are not conclusive evidence of yield loss. It is the combination of knowledge gained from in-line pattem wafer inspection, yield analysis and the identification of the tool signatures that determines when to take corrective action. The next, important steps to take in implementing backside inspection into a production environment wil be to automate the spatial signature analysis, front-side to backside correlation and signature to tool correlation. furnace processes and backside contamination by wafer handling. A non-destructive analysis of tool or handler defect signatures on the wafer backsides was facilitated by using the BSIM (Back Side Inspection Module) on the surfscan SPI. A correlation of backside defect data to front side pattemed-wafer inspection revealed that not all defect issues on a wafer backside are relevant to the photolithographic process depending on their position on the wafer, their sue, shape and orientation. The most powerful outcome of backside defect inspection is the identification of spatial defect signatures and their correlation to tool or process fingerprints. The next step is to automate the identification, analysis and correlation of such backside defect signatures to tools and processes. 5. Conclusions Tight depth of focus requirements in high-end semiconductor manufacturing photolithography leaves little or no room for any localized deviation in the wafer uniformity. At feature sizes of llonm and below any contamination or topography variation on a wafer backside causes process difficulties or even yield loss. This is particularly relevant to the super flat 300 wafers which have challenging specifications for wafer surface uniformity. Acknowledgements The authors wish to thank their colleagues at Infiineon Technologies Dresden and F. Rogers, KLA-Tencor Corporation for useful input. References [ 11 ITRS Roadmap [2] Surfscan SPl Online Publications, User Edition Book-on-Board for SW. Version 3.8. [3] The Influence of Hardware and Chemistry on the Removal of Nanoparticles in a Megasonic Cleaning Tank, Focusing on 300 super-flat wafer G. et d, IMEC, 2002 photolithography we identified that the Ostende, 09/02, backside defect count steadily increases throughout the 141 New Single Wafer Processes Offer manufacturing process. There are two Altemative Backside Cleans, M. Lester, major sources of backside defects: Semiconductor International. 01/01. Defect generation by deposition or IEEWSEMI Advanced Manufacturing Conference

8 [5] Reducing Baseline Defect Density Through Modeling Random Defect Limited YielP, L. Milor, Y. Peng, AMD and J. Segal HPL. 01/00. [6] Spatial Signature Analysis of Semiconductor Defects for manufacturing Problem Diagnosis, S. Gleason, K Tobin, T Kamowski ORNL. Solid State Technology 07/96. Further reading Wafer Backside Inspection Applications for Yield Protection and Enhancement Using SPl TBI, L. Cheema, Agere. KLA- Tencor YMS, Semicon Southwest, 10/01. Backside Contamination - some Sufscan views, K. Haller, KLA-Tencor. International Sematech Users Meeting, 02/ IEEWSEMI Advanced Manufacturing Conference