Rivelatori di immagini ad alta velocita per il European X-ray Free Electron Laser. Andrea Castoldi Politecnico di Milano & INFN

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1 Rivelatori di immagini ad alta velocita per il European X-ray Free Electron Laser Andrea Castoldi Politecnico di Milano & INFN

2 MoU signed by: Germany, Italy, France, Greece, Spain, Sweden, Switzerland, UK, Poland, Hungary, Denmark, Russia and China A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 2/27

3 SASE (Self-Amplified Spontaneous Emission) A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 3/27

4 XFEL projects: time schedule comparison EXFEL Preparation Construction Operation LCLS starts operation EXFEL SASE SCSS starts operation 15 july 2006 The European Project Team for the XFEL delivered the TDR R&D until ~2011 A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 4/27

5 What are the challenges for 2D detectors? Time structure of EXFEL: difference with others Electron bunch trains; up to 3000 bunches in 600 µsec, repeated 10 times per second. Producing 100 fsec X-ray pulses (up to bunches per second). 600 µs 100 ms 100 ms 99.4 ms bunches/s but 99.4 % emptiness 200 ns X-ray photons 100 fs FEL process A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 5/27

6 Consequences of time structure Either: < 10Hz or > 1.5 khz; best 5 MHz All photons arrive in 100 fsec integrating detectors. Experiments should profit from high luminosity ( shots/sec) and time structure (200 ns). Every shot is a new experiment but poses technological challenges (jitter, sample destruction, detector charge handling and position resolution) photons per pixel per pulse (i.e e-h pairs per pixel!) A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 6/27

7 A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 7/27

8 Call for EOI 17 th July 2006: 46 pages; covering 5 areas 6 EoIs received; different consortia and technologies 3 EoIs selected to develop full proposal A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 8/27

9 A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 9/27

Large Pixel Detector (LPD) Rutherford Appleton Laboratory (c/o Markus French) Principle: tiled hybrid with 500µm pixels Science and Technology Facilities Council involvement of UK universities 500 µm

10 Large Pixel Detector (LPD) Rutherford Appleton Laboratory (c/o Markus French) Principle: tiled hybrid with 500µm pixels Science and Technology Facilities Council involvement of UK universities 500 µm pixels 5 MHz framing speed Single photon sensitivity 10 5 dynamic range (3 gains in parallel) 512 image storage depth 128 x 32 pixels monolithic tiles Roof tile structure courtesy of H.Graasfma for the European XFEL A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 10/27

pixels 5 MHz framing speed Single photon sensitivity 5 x 10 4 dynamic range, using 3 switched

11 The European X-Ray Laser Project XFEL Analog pipeline Hybrid Pixel Detector (HPAD) DESY PSI/SLS University Bonn University Hamburg Principle: bump-bonded hybrid pixels 100 to 200 µm pixels 5 MHz framing speed Single photon sensitivity 5 x 10 4 dynamic range, using 3 switched gains 400 to 1000 image storage depth 256 x 512 monolithic tiles Flat detector 11 Heinz Graafsma, DESY

Mannheim 5. Un. Bergamo/Pavia 6. Un. Siegen PoliMi & INFN PoliMi & INFN UniBG MPI-HLL Un.

12 The Linear Silicon Drift Detector (LSDD) The Consortium: 1. MPI-HLL (MPI and MPP) 2. Politecnico di Milano & INFN 3. DESY 4. Un. Mannheim 5. Un. Bergamo/Pavia 6. Un. Siegen PoliMi & INFN PoliMi & INFN UniBG MPI-HLL Un. Siegen MPI-HLL DESY DESY MPI-HLL A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 12/27

13 Who we are and what we do (Detector/On-Chip/Analog) Politecnico di Milano and INFN, Sez. di Milano, Italy Detector MPI Halbleiterlabor, München, Germany LSD Detector chip On-chip Electronics Front-end ASICs A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 13/27

14 Detector Structure: multi-column SDDs Bias /Control Logic anodes N-side P-side fast and noiseless electron drift control of lateral broadening of charge cloud limited no. of channels (simplified interconnection issue) Q T d y z x collecting anode and on-chip electronics: -high energy/position res. -speed Applicazione in ambito internazionale di R&D nata in INFN-gr.5 (esp. RIMAX, CODERA, COMPTON) con ruolo di leadership a Milano A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 14/27

15 Working principle in the XFEL facility hv trigger by XFEL (~1ns) 65 T drift ~ L drift /v drift Anode T d -potential [V] current time 1000 drift coordinate [ µ m] lateral coordinate [ µ m] 700 The current shape at the anode mirrors the photon image impinging on the detector A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 15/27

16 Detector topology 128 channels 1 MHz frame 200µm pixel E=2-20 kev 10 3 X-rays/pixel QE>80%@10keV ENC~50 el. Expandable to: 512x512 (monolithic) 1000 ns 1000 ns (?x=200µm,?t=15.6ns) on-chip electr cm (64 pixels) 1.28 cm (64 pixels) on-chip electr. 128 channels V drift 13 µm/ns (i.e. ~3.5V/30µm bias) T drift, max = 1000 ns A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 16/27

17 Analog frontend electronics i(t) Analog FE electronics µm single SDD line i(t) V(t) On-chip electronics Ampl.+buf. stages SDD chip ASIC purpose of the analog FE electronics is to provide an amplification and fast shaping of the SDD current signals the FE electronics is based on the SDD on-chip electronics + custom ASIC A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 17/27

On-chip electronics: input devices On-chip JFETs On-chip DEPMOS

require a feedback preamplifier configuration 2 bonding/channel

18 On-chip electronics: input devices On-chip JFETs On-chip DEPMOS minimization of stray capacitances, low noise Speed issues may require a feedback preamplifier configuration 2 bonding/channel & integrated reset mechanism Input device C FET C stray g m ext. FET 1pF 0.5pF 3mS on-chip JFET 70fF 0 350µS DEPMOS 40fF 0 100µS A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 18/27

On-chip JFETs: esp. INFN-gr.5 COMPTON (2004-2006) 600 Vgs=0 V 1 cm Ids [µa] 400 200-0.5 V -1 V -1.5 V -2 V -2.

04 V 0 100 200 anode # 4 3 2 Vp [V] (@ Idss/1000) g m [µs] 400 300 200 100 g m =350 µs ± 8 µs r 0 =25.6 kw ± 0.

19 On-chip JFETs: esp. INFN-gr.5 COMPTON ( ) 600 Vgs=0 V 1 cm Ids [µa] V -1 V -1.5 V -2 V -2.5 V Vds [V] 240 channels I dss [µa] I dss =620 µs ± 15 µs V P =2.75 V ± 0.04 V anode # Vp [V] (@ Idss/1000) g m [µs] g m =350 µs ± 8 µs r 0 =25.6 kw ± 0.8 kw anode # r 0 [kω] The measured spread of DC parameters on 240 ch. is less than 3% A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 19/27

20 Analog frontend: readout strategies A. Direct reading of the on-chip FET current with external I/V conversion SDD chip Non-linear reset path i(t) FE chip a VLSI transimpedance amplifier operates the I/V conversion of the FET current induced by the SDD current pulse i FET (t) non-linear signal compression implemented directly by an on-chip device in the anode region B. Full transimp. amplifier based on the on-chip FET as input transistor SDD chip i(t) Reset FET 1/α FE chip V(t) closed-loop configuration based on the on-chip FET as input transistor and on a Reset on-chip device to implement the dynamic feedback resistance of a transimpedance amplifier First FET non-linearity for signal compression in the feedback path (e.g. I drain /V GS reset FET) A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 20/27

21 Data Acquisition: Burst write/gap read from ROIC ADC MCC FPGA CWDM TX to Preprocessor Burst write Gap read MEM Strategy Straightforward Solution Digitizer per Drift Path ROIC near Short-distance Highspeed Data Transfer Temporary Data Storage ADC near Flexible & Standardized Readout Field-programmable Devices Data-link Layer? Physical Layer Devices Insensitive & Large Throughput Capacity Digital Optical Transfer Mode Wavelength-Division Multiplexing Challenge 1-M Pixel? 16 k digitizers 1.4-Mb/digitizer? 3 GByte Complexity High Speed & Resolution Bursty Write Access Low-jitter Clock Management Low Area & Power Low Area & Power Dynamic Power Management Small Form Factor Conclusion use high integration density BUT only as high as mandatory (space requirement) use commercial products whenever possible (3 years to prototype) A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 21/27

22 Focal plane layout: 256 x 256 and 1k x 1k Focal plane sub-module (2011): 256 x 256 pixel of 200 microns detector sub-module (256 x 256) detector module (512 x 512) 21 cm PCB connector 256 ch analog FE ASIC LSDD detector Focal plane 1k x 1k (2013) A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 22/27

23 Detector R&D keypoints confining mechanism of charge lateral broadening electron injectors optimization of p+ strips for high drift field back-side junction segmentation and structure guard ring topology (HV ~ 1000 V) timing properties (i.e. position resolution) vs. material properties/strip geometry/operating parameters device integration of detector and on-chip electronics A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 23/27

High charge confining techniques 1. Proper combination of deep n- and p- implants deep p-impl. deep n-impl. collected charge / Q 1.0 0.5 t d =3 µ s T=300 K Q=16000 el 0.

24 High charge confining techniques 1. Proper combination of deep n- and p- implants deep p-impl. deep n-impl. collected charge / Q t d =3 µ s T=300 K Q=16000 el lateral coordinate [um] (only p-type implants) exp. measurements 60µm channels lat. coordinate deep p-impl. deep n-impl. A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 24/27

25 Timing calibration by electron injectors?x= 200µm?t= 15.6ns number of injectors per column to be defined (at least 2, better more) amount of charge injection depends on detector pixel size interconnection: one bonding pad per rowof injectors acquisition of additional calibration images before/after bunch train (in the time gap) with very slowrepetition rate intensity calibration? test structures to be designed and studied to decide topology A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 25/27

26 Detector, OCE & Analog ASIC - Time Scale S+0m S+18m S+48m LSDD- Detector 1.1 cm drift length First prototype of LSDD-Detector with 8 channels fully equipped at least 32 channels 1st detector production: ( ) equiv. pixels, at least 32 channels 256 channels time On-chip electronics 1.28 cm drift length (64 equivalent pixels) at least 32 channels 64 equivalent pixels Final detector production: 256 x 256 pixels monolithic Analog ASIC First prototype of FE chip Second prototype of FE chip - 64 channels Final prototypes of FE chip 64 channels/chip Bread- board Module tested End of Phase I 256x256 module delivery A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 26/27

27 Next steps Valutazione delle proposte (XDAC 8/9 Maggio) intensificare attivita R&D sul rivelatore/keypoints (tempi di progetto e supporto da EXFEL limitati) Link the proposals to the science fields Assign potential users to the detector projects Start projects and Develop real requirements Grazie per la vostra attenzione A.Castoldi - Rivelatori per EXFEL CSN5 22/5/2007 Slide 27/27

X-ray Detectors at DESY

X-ray Detectors at DESY (Contribution given at the FEL2006 meeting in Berlin) DESY The European XFEL Time structure: difference with others Electron bunch trains; up to 3000 bunches in 600 μsec, repeated