EUROFEL-Report-2006-DS EUROPEAN FEL Design Study

Transcription

1 EUROFEL-Report-2006-DS3-034 EUROPEAN FEL Design Study Deliverable N : D 3.8 Deliverable Title: RF Amplitude and Phase Detector Task: Author: DS-3 F.Ludwig, M.Hoffmann, M.Felber, Contract N : P.Strzalkowski, H.Schlarb Project funded by the European Community under the Structuring the European Research Area Specific Programme Research Infrastructures action

2 EUROFEL Deliverable D3.8 Task No.: DS3 Synchronization RF Amplitude and Phase Detector Participant/Participant No.: DESY / Holger Schlarb, Frank Ludwig address of Reporting Person: Frank.Ludwig@desy.de Reporting Period: RF Multichannel downconverter Prototype and Characterization (Delivery report for the EUROFEL DS3 Task, Jan. 16, 2007) F.Ludwig, M.Hoffmann, M.Felber, P.Strzalkowski, H.Schlarb Deutsches Elektronen-Synchrotron (DESY), Notkestrasse 85, Hamburg, Germany 1.1 Description of progress and achievements during the reporting period

3 To synchronize the electron beam and the timing reference, two aspects of the system must be considered. The phase and amplitude stability of the acceleration RF are important because of the energy dependent path length of the electron beam in the bunch compressor chicanes. In addition, the local and master oscillators must be synchronized to ultra-high precision. This is achieved through a laser-based timing system and laser to RF conversion units that provide the local-oscillator signal source. In this report, the progress on phase and amplitude detection stability is discussed Injector - Multi-channel packaging and IO connection Especially within a noisy accelerator environment a carefully design of the DWC, packaging and shielding is indispensable. According to the rf-shielded mechanical design in Figure 2 several items have to take into account. For a low channel crosstalk each channel is located within an rf-shielded subsection. To reduce distortions, the frontend and ADC must have a strong GND connection. To reduce spurious signals, separate the power supplies for analog and digital sections. To reduce the crosstalk RF, LO and digital interconnections should be filtered. The modular design imply an uncomplicated update to future state of the art mixers. The rf-shielded multi-channel DWC, as shown in Figure 2 can be plugged either onto an ATCA standard motherboard or an VME type motherboard having an FPGA for filtering, IQ detection and data preprocessing, which is currently manufactured. Figure 1a shows the first version of the multi-channel DWC. As depicted in Figure 1b an amplitude of 0.005% and a phase stability of for the ADC sampling process is achieved by averaging over 1µs.

4 Figure 1: (a) Multi-channel DWC digital motherboard ACB1.0 (Advanced-Carrier-Board) and the rfshielded analog frontend including analog attenuators, mixer frontend and ADC readout. (b) Setup for averaging the ADC noise using two rf-generators. The blue, respectively red curves shows the direct sampled, respectively averaged amplitude and phase values for an intermediate frequency of 54MHz, sampling frequency of 81MHz by averaging over 1µs. Figure 2 shows the latest version of the ACB2.0 (Advanced-Carrier-Board) board. It has a faster FPGA and DRAM (Dynamic Random Access Memory) for data preprocessing for the support of the Beam Arrival Monitor [1] or high resolution ADC applications. Furthermore a low jitter programmable clock distribution is implemented for each channel. Figure 2: Multi-channel DWC digital motherboard ACB2.0 (Advanced-Carrier-Board) and rfshielded analog frontend including analog attenuators, mixer frontend, 16-bit ADC channel and LOdistribution. The DWC is partly assembled. The production, commissioning, jitter and drift characterization of the multi-channel DWC is shown in Figure 2 and still in progress. The LO-signal mixer frontend amplifier has an additional integrated jitter of about 4fs from 10Hz to 10MHz. It is planned to reduce this jitter contribution by using a separate mixer and LO-amplifier with much lower 1/f-noise contribution. In addition, it is planned to test the multi-channel boards using other mixer structures, e.g. high-level DWCs, where linearization methods and self-calibrating methods have to applied. These structures are more complex and are foreseen for the future Main Linac - Muli-channel packaging and IO connection The requirements of the phase and amplitude stability for the main linac is not so demanding compared to the DWCs located at the injector. To reduce the costs the number of DWC channels per main board should be maximized. One approach is to use an ATCA standard

5 board with an FPGA and ADC s. The DWC channels are located at the ATCA rear panel. This requires a different DWC board design compared to the injector multi-channel DWC, which is planned to designed in the near future in multi layer SMD technology Influence of the regulation system Not only the DWCs noise-performance influences the cavity field-vector stability. The phase noise of the master oscillator, latency of the low level rf-controller, klystron stability, noise seen by the cavity pickup and micro-phonics in the cavity also limit the achievable stability of the accelerating rf-fields. To distinguish noise contributions, a phase-noise analysis is performed [2]. Figure 3a shows the underlying phase-noise model of the regulation system and the measured phase-noise spectra of each component. The effective bandwidth of the DWC, which contributes to the residual jitter between the cavity field and master oscillator, is about 50 khz [2] and given by the cavity s cut-off frequency, multiplied with the close-loop gain. This is much smaller than the DWCs bandwidth and underlying noise-contribution. Figure 3b shows the corresponding contributions to the cavity field jitter. The noise is mainly filtered by the cavity. The DWC output resolution acts as an upper bound for the actual cavity field jitter. It is, therefore, planned to measure the beam induced residual jitter directly. Figure 3: (a) Cavity phase noise model and the noise characterization of each component. (b) Phase noise contribution to the cavity field jitter for each component.

6 Another limitation of the cavity field stability is caused by the measuring of the vector sum of several cavities provided by one klystron in the precense of microphonics or Lorentz force detuning. According to a detailed analysis [Brandt06] this requires for a single DWC an Amplitude and phase calibration better than 0.5%, Field flatness better than 5%, Non-linearity better than 30dB References [Brandt06] A.Brandt, Development of a Final State Machine for the Automated Operation of the LLRF Control at FLASH, DESY, Dissertation in preparation Dissemination of knowledge Papers: [1] F.Löhl, K.Hacker, F.Ludwig, B.Schmidt, H.Schlarb, A.Winter, A Sub 100 fs Electron Bunch Arrival-time Monitor System for FLASH, European Particle Accelerator Conference (EPAC) 2006, Edinburgh, UK, Jun [2] F.Ludwig, M.Hoffmann, H.Schlarb, S.Simrock, Phase Stability of the Next Generation RF Field Control for VUV- and X-ray Free Electron Laser, Paper TUPCH188, European Particle Accelerator Conference (EPAC) 2006, Edinburgh, UK, Jun [3] S.Simrock, M.Hoffmann, F.Ludwig, M.K.Grecki, T.Jezynski, Considerations for the Choice of the Intermediate Frequency and Sampling Rate for Digital RF Control, Paper TUPCH191, European Particle Accelerator Conference (EPAC) 2006, Edinburgh, UK, Jun 2006.