A new restart at DAΦNE collider: challenges and preparation

Transcription

1 A new restart at DAΦNE collider: challenges and preparation Florin Sirghi INFN-LNF on behalf of SIDDHARTA-2 collaboration

2 DAΦNE collider: the evolution and revolution in operation since 1998 and expected to terminate its run in collider mode by 2019 SIDDHARTA run finish on 9 Nov big improvements in the autumn of 2008 new Crab Waist collision scheme delivering luminosity: ~12 pb -1 /day daily record: ~15 pb 1 /day record per hour: ~ 0.6 pb 1 /h peak luminosity: 4.5E+32 cm-2s-1 August 2008 August

3 DAΦNE collider: the evolution and revolution SIDDHARTA run: Operation mode: long costing beams ~ 4-5 injection/2 hours KLOE-2 run Operation mode: topping-up regime Delivered luminosity: ~ 12 pb -1 /day Peak luminosity : ~2.2E+32 cm-2 s-1 3

4 DAΦNE collider: trouble-ticket/faults history VACUUM RADIO PROTECTION RF SYSTEM POWER SUPP&MAGNET OPERATION MAINS LINAC LUMI MONITOR SIDDHARTA KLOE FLUIDS FEEDBACK&DIAG&TIMING DAFNE CRYOGENICS CONTROL SYSTEM KLOE-2 SIDDHARTA

5 SDD X-ray detector Cryogenic target Cooling system Vacuum chamber Veto system Kaon trigger Luminosity monitor Beam pipe Shielding Support frame SIDDHARTA-2 apparatus Service platform C. Capoccia, G. Fuga INFN-LNF 5

6 SDD X-ray detector SDD technology developed at FBK laboratories (Trento, Italy) CMOS Preamplifier CUBE is a charge sensitive preamplifier operating in a pulsed reset regime. the whole preamplifier is connected close to the SDD (and not only the FET) 48 SDD arrays (8 SDD cells/array) total area of 246 cm 2 Old SDD from PNSensor the high transconductance of the input MOS compensates the larger capacitance introduced in the connection SDD-FET the remaining part of the electronics (ASIC) can be placed relatively far from the detector (even cm) 6

7 SDD production facility Fondazione Bruno Kessler FBK, Trento Example of qualification 2x4 SDD array optical inspection electrical qualification diced with a diamond blade

8 SDD assembly and testing facility POLIMI Milano SDD array from FBK Special design SDD ceramics Bonding CUBE preamplifiers on SDD matrix Assembly (M1 screws) SDD and cooling holder Ready for test final SDD detector 8

9 SDD testing facility POLIMI Milano Final SDD detector mounted on test bench After /bonding/gluing /assembling First x-ray spectroscopy test Mn K-alpha line from an 55 Fe source New qualification for each SDD array before to be install in the final setup 9

10 SDD testing facility POLIMI Milano ASIC development SFERA readout chip SFERA Main Features: 16 channels (2 SDD arrays), analog multiplexer readout IX order, time invariant, semi Gaussian pulse shaping amplifier, implemented in single ended topology Six different selectable shaping times (500 ns 6 microsec) Five selectable energy ranges (10 kev 70 kev) 10

11 SDD testing facility SMI Vienna Cooling cycles at cryogenic temperatures with dummy's and real detectors discovering the gluing issues (Kapton bi-adhesive) developing the new design for the ceramic/cooling holder Thermal Simulations with copper block at 50 K 11

12 SDD testing facility LNF Frascati Test bench for single SDD array (8 channels) Test bench for multiple-bus configuration 12

13 SDD testing facility LNF Frascati single SDD array measurements Spectroscopic characterization Controlled cooling temperatures for SDD down to 120 K Calibration using X-ray Tube: 23 10μA and multiple target foils Source: 90 Sr/ 55 Fe Trigger studies for timing measurements using straw tube or plastic scintillators (lab) trigger signal from BTF Linearity Resolution Stability Timing High rate response 13

14 SDD testing facility LNF Frascati Linearity vs High Voltage New SDD 1 high voltage channel 4 low voltage channels for ASIC-chip Calibration using x-ray tube Ti Kα each old detector (6 SDD cells/array) 10 high voltage channels 10 low voltage channels 8 supply voltage for ASIC-chip Fe Kα Cu Kα Br Kα Ti Kβ Fe Kβ Cu Kβ Br Kβ Energy (ADC channels) 14

15 SDD testing facility LNF Frascati Resolution vs High Voltage Resolution vs Temperature (Fe K-alpha line) Fe FWHM ± 0.4 ev SDD_4 SDD_2 SDD_3 15

16 SDD testing facility LNF Frascati Chan nel ΔT SDD [ C] m MAX [adc/ev] m MIN [adc/ev] (Δm/m )/ΔT [ C -1 ] Drift Time vs Temperature (done in BTF) 7 9,6 1,6212 ± 0,0002 1,62047 ± 0, *10-5 Temperature stability 16

17 SIDDHARTA-2 cryogenic target Working temperature: 30 K Working pressure (overp): 0.3 MPa increase the target stopping power almost double gas density with respect to SIDDHARTA (3% LHD) SDDs placed 5 mm from the target wall 130 mm Target cell wall is made of a 2-Kapton layer structure (75 µm + 75 µm + Araldit) 130 mm diameter 90 mm height 17

18 SIDDHARTA-2 cooling add additional cooling power to the SDD and cryogenic target Target + SDD cooling 1 Leybold MD K target cell and SDDs will be cooled via ultra pure aluminum bars T TC = 30 K T SDD = 70 K Line driver boards 4 CryoTiger K Copper - band cooling lines T LD = 120 K Copper band ultra pure Al bars 18

19 SIDDHARTA-2 vacuum chamber New mechanical improvements in order to increase the cooling power for SDD and target in-situ calibration at low rate using two ports for x-ray tubes placed in the bottom part chamber tested He-leak checked ready to install all the others components 19

20 SIDDHARTA-2 Veto system 12 L-shape modules Do to space limitation a special light-guide mirror design Veto system 1 the external components time resolutions of ~ 600 ps FWHM pion detection efficiencies of ~98% (PSI test) Surrounding vacuum chamber barrel of scintillators 20

21 SIDDHARTA-2 Veto system 1 Mechanical structure for the final mounting is under construction For background studies the first detectors to be install in DAΦNE 21

22 SIDDHARTA-2 Veto system 2 Veto system - 2 the internal components BC-408 scintillator tile 45 x 30 x 5 mm3 fast response high light yield SiPM from AdvanSiD, Hamamatsu and Ketek scintillator tiles placed behind each SDD array positional correlation between SDD and the hit in the scintillator tile (SciTile) 4x4 mm2 NUV-SiPM from FBK good timing compactness high photon detection efficiency (PDE) time resolution of 485 ps FWHM (BTF) 22

23 SIDDHARTA-2 Kaon trigger The system is based on 2 pairs of scintillator/pmt s main functionality as trigger check the collider energy tuning to monitor the transverse IP stability Top part 10x 10 cm scintillator - long light guides IP1 Tested in beam at BTF LNF and PSI Bottom part 10x 10 cm scintillator - short light guides 23

24 SIDDHARTA-2 Luminosity monitor Crucial information for machine tuning and fast feedback Coincidence rate: 25.7 % per charged kaon pair single rate at the boost side: 42.7 % single rate at the anti-boost side: 32.3 % With the goal of luminosity L ~ cm-2 s-1 Estimated rates: 37 Hz (coincidence) / 62 Hz (on boost-side) 2 pieces 8 x 4 cm, thickness = 2 mm distance y = ± 4 cm off beam prototype under test at LNF in 5 seconds: 185 counts - 7% / 310 counts (on boost-side) - 5.7% Prototype Univ. Jagellonian, Krakow

25 SIDDHARTA-2 interaction point A new low-beta section has to be build new beam pipe optimized to minimize the showers developed inside by the high flux of collider lost particles KLOE-2 roll-out with internal magnets focusing quadrupole (QF) quadrupole permanent magnet (QD) total length 450 mm internal length mm external carbon fiber jacket ø 66 mm thickness ~ 500 micron flanges removed major source of asynchronous background internal ultra pure aluminum ø 55mm thickness ~ 150 micron 25

26 SIDDHARTA-2 apparatus Support frame Shielding with new support With the new dimensions of the vacuum chamber Siddharta-2 needs more vertical space (target insertion) it s necessary to rebuild the support structure with Bosch aluminum profiles Estimated weight Lead table ~ 500 Kg Two walls ~ 700 Kg 26

27 SIDDHARTA-2 Service platform Refurbish the old elements and update to the new regulations regarding safety (antiearthquake) 27

28 SIDDHARTA-2 data acquisition system DAQ architecture based on National Instruments boards (ADC, FPGA) and LabView software analog readout quality (multiple sampling, cross-talk elimination, stability under rate and temperature fluctuations) digital signal handling with minimum access time and bus conflict solving dataflow up to few hundred MB/s (400 MB/s in our case, for a system of 384 channels), almost one order of magnitude above the capability of the fast VME buses (<80 MB/s) and moreover requiring a Real-Time processing at a level of tens of nanoseconds (commercial RT systems allows at most microsecond-level control) interconnection with external systems: Kaon trigger/ Veto / Luminosity monitor implementation with commercially available hardware for sustainable costs 28

29 DAΦNE time line after KLOE-2 presented at last LNF Scientific Committee 29

30 Gantt chart SIDDHARTA-2 SIDDHARTA-2 assembling plan Cryogenic target cells 48 SDDs bonded and mounted SDD final tests (with SFERA + DAQ) Veto-1 constructed/tested Veto-2 constructed/tested Kaon trigger Luminosity monitor constructed/tested SIDDHARTA beam pipe final mounting, debugging and testing Q4/2016 Q1/2017 Q2/2017 Q3/2017 Q4/2017 Q1/2018 installation at DAΦNE 30

31 Thank you for your attention 31

32 SPARES 32

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35 New SDD technology: CUBE preamplifier BTF test - July Fe spectrum ev FWHM SDD characteristics: area/cell = 64 mm 2 total area = 512 mm 2 T = C drift time < 500 ns 35