MASK COST OF OWNERSHIP OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING

Transcription

1 MASK COST OF OWNERSHIP OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING Presented to The Faculty of the Department of General Engineering San Jose State University In Partial Fulfillment Of the Requirements for the Degree Master of Science in Engineering by ALDRIN UDASCO AHMAD NOWBAKHT December 2009

2 2009 Aldrin Udasco, Ahmad Nowbakht ALL RIGHTS RESERVED ii

3 SAN JOSE STATE UNIVERSITY The Undersigned Project Committee Approves the Project Titled MASK COST OF OWNERSHIP CONSIDERATION OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING by Aldrin Udasco Ahmad Nowbakht APPROVED FOR THE DEPARTMENT OF GENERAL ENGINEERING Dr. Ted Liang Date Industrial Sponsor, Intel Components Research Dr. Melisa Buie Date Technical Advisor, Coherent Inc. / San Jose State University Dr. Leonard Wesley Date Professor, San Jose State University iii

4 ABSTRACT MASK COST OF OWNERSHIP CONSIDERATION OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING by Aldrin Udasco, Ahmad Nowbakht Moore s Law states that the number of transistors on a chip will quadruple and performance will double about every two years. Semiconductor manufacturers and engineers have been able to reduce channel lengths, essentially increasing the number of features and shrinking silicon area, as predicted by Moore s law for the past forty years, making devices faster, smaller and cheaper. With feature sizes approaching one ten thousandth of a human hair, we are now able to place a million times as many devices on a given area of silicon as compared to forty years ago. However, traditional lithography techniques can no longer keep pace with these shrinking geometries. The next generation lithography, and more specifically, its mask Cost of Ownership, is the new focus of the industry. Mask cost is considered to be one-third of the overall cost of manufacturing in modern integrated circuits. In this project report we will consider the mask Cost of Ownership of Extreme Ultraviolet Lithography and 193nm Double Patterning and determine the most cost effective next generation lithography. iv

5 ACKNOWLEDGEMENTS We would like to express our sincere thanks and appreciation to Professor Leonard Wesley, Department of Computer Engineering, San Jose State University for all his suggestions and guidance throughout the course ENGR298 during fall 2009 semester. We would like to thank Dr. Melisa Buie, Professor in the Department of Chemical and Materials Engineering, San Jose State University for her continuous support, encouragement and guidance in completing this project. We would like to thank Dr. Ted Liang, Intel Components Research for all his unwavering support in achieving our goal. We would like to thank to our family members who continuously encouraged us and gave their full support. Aldrin Udasco Ahmad Nowbakht v

6 Table of Contents Chapter 1.0 Introduction Project Background Extreme Ultraviolet Lithography Technology (EUVL) Double Patterning Technology Double Exposure Self-aligner Spacer Double Expose, Double Etch Double Expose, Double Etch (Trenches) Cost of Ownership Benefits Statement of Problem Hypothesis...8 Chapter 2.0 Project Deliverable Plan and Description Project Organization Structure Project Timeline Project Scope Literature Survey Economic Justification Final Project Scope...12 Chapter 3.0 Literature Survey Cost of Ownership Project Assumption Cost of Ownership Model Cost of Ownership Calculation Method Cost of Ownership Model Parameters Viable Option of Future Lithography Process Flow Advantages and Disadvantages of EUVL and DPL Preliminary Cost of Ownership Calculation Procedure...22 Chapter 4.0 Economic Justification Intel Mask Cost of Ownership Executive Summary Problem Statement Solution and Containment Customer Intel Capital Spending Market Share Overall Device Cost Trend Time to Market Cost of Ownership Calculation Procedure Cost of Ownership Calculation Results Recommendations Method of Investigation SWOT Analysis for EUVL EUVL Break Even Analysis...51 vi

7 Chapter 4.0 Economic Justification 4.2 A&A An Independent Company Executive Summary Product Summary and Business Model Product Service and Value Proposition Targeted Customer Targeted Market for the Product Personnel Required Service Cost Summary Break Even Analysis Profit and Loss Mask Cost of Ownership Service SWOT Analysis for A&A Consulting Firm Financial Profile Using Norden Rayleigh Analysis Return of Investment Exit Strategy...63 Chapter 5.0 Conclusion...63 Appendix...64 References...68 vii

8 List of Figures Figure 1. Extreme Ultraviolet Lithography (EUVL)...2 Figure 2. Extreme Ultraviolet Lithography Overview...4 Figure 3. Double Exposure Patterning...5 Figure 4. Self Aligned...5 Figure 5. Double Exposure Double Etch (Mesas)...6 Figure 6. Double Exposure Double Etch ( Trenches)...7 Figure 7. Project Organization Structure...9 Figure 8. Gantt Chart...10 Figure 9. Milestones Chart for the Project...11 Figure 10. Cost of Process...13 Figure 11. Cost of Ownership Model Primary Factors...15 Figure 12. Industry Mask Usage...17 Figure 13. Projected Tool Cost and Historical Trend...18 Figure 14. Candidate s Technologies for 32nm...20 Figure 15. Layout Decomposition for Core Pattern...21 Figure 16. Standard Mask Process...21 Figure 17. EUVL SRAM Cell...22 Figure 18. Process flow of EUVL...23 Figure 19. Non Volatile Memory Market Shares of 2007 and Figure 20. Semiconductor Industry One of Top R&D spenders...27 Figure 21. Intel s Capital Spending...28 Figure 22. Total lithography cost per function for future technologies...30 Figure 23. Contribution to reductions in cost per function...31 Figure 25. Scheduled/Unscheduled Downtime...32 Figure 26. Intel Microprocessor EUVL Break Even Analysis...34 Figure 27. Intel Microprocessor EUVL Implementation Break Even Analysis...52 Figure 28. Break Even Chart of A&A Consulting Firm...53 Figure 29. Profit and Loss A&A consulting Firm...57 Figure 30. Funding Profile Year 2010 and Figure 31. Cumulative Funding Profile Year 2010 and Figure 32. Rate on Return Investment...63 Figure 33. Gantt Chart...65 viii

9 List of Tables Table 1. Parameter of 32nm and 22nm half pitch...19 Table 2. Global microprocessor market share...29 Table 3. Cost of Ownership calculation procedure...33 Table 4. Number of good wafer per year...34 Table 5. Fixed cost...35 Table 6. Recurring cost...36 Table 7. Other cost...37 Table 8. Global parameters...37 Table 9. Overview of lithography calculations, 32nm half pitch...41 Table 10. Details of lithography calculations, 32nm half pitch...42 Table 11.Overview of lithography calculations, 22nm half pitch...45 Table 12 Details of lithography calculations, 22nm half pitch...47 Table 13.Variable and fixed cost Table...56 Table 14.Variable and fixed cost Table...57 Table 15. Profit and loss Table...58 Table 16.SWOT analysis...59 Table 17. Norden Rayleigh calculation for Table 18. Norden Rayleigh calculation for Table 19.Return on investment Table...62 Table 20. Process steps occur how many times for each flow...66 Table 21. EUVL sensitivity analysis...67 ix

10 Chapter 1.0 Introduction Lithography is the technology used to transfer intricate circuit patterns that define electrical circuits from the mask to the wafer. Similar to developing film, light is used to affect the transfer of the pattern onto the wafer surface. Typically today, a circuit pattern on the mask is imaged, with a reduction of 4:1, onto the wafer. For more than forty years, the integrated circuits industry has been very successful in shrinking device geometries. Gordon Moore predicted an exponential growth which predicted that transistor performance would double while the total number of devices on a chip would quadruple every two to three years. With the advances made by the semiconductor industry, Moore s prediction has now become an empirical law. One area where crucial developments are being made is lithography. The semiconductor industry has so far continued to improve the optical projection lithography to be able to print finer features. This has allowed the semiconductor industry to produce more cost effective, small, fast and powerful semiconductor devices for the consumer industry. Extending lithography from the current 45nm technology to 32nm and 22nm half pitch requires the introduction of new advanced next generation lithography (NGL) technologies, such as Extreme Ultraviolet Lithography (EUVL), high index immersion or double patterning [5]. EUVL is a process technology that involves reflective optics such as mirrors with multilayer coating. It utilizes 13.5nm wavelength light to develop the patterns on the mask. 1.1 Project Background The project deliverable is to determine the mask Cost of Ownership (CoO) of EUVL and a selected group of double patterning technology and to compare the most 1

11 cost effective choice as the next generation lithography. Total Cost of Ownership is a simulation tool used to determine the economic value of an investment and therefore it is used to understand the mask cost associated with NGL technologies. In this project report we will give a brief overview of the emerging lithography technologies and the challenges moving forward. We will evaluate the most advantageous NGL for the IC industry. 1.2 Extreme Ultraviolet Lithography Technology Extreme ultraviolet lithography is the continuation of optical lithography and is considered as the next generation lithography for 32nm and beyond. As discussed, in keeping with Moore s law and the industry roadmap the number of transistor on each IC is continuously increasing while the total die size is continuously shrinking. Printing smaller features has become one of the main challenges for the industry. There are various roadblocks in moving from the current lithography technology to the NGL. Current challenges of lithography are reducing the wavelength of the light source, increasing the numerical apertures of the lens and reducing the indicator of lithography quality and complexity, k 1. (See Figure 1) Figure1. Feature size versus lithography wavelength (λ) used to produce minimum feature size [1]. 2

12 where is the indicator of lithography quality and complexity, λ is the light source wavelength and.. is the Numerical Aperture. Finer features can be attained by reducing the wavelength, increasing the lens numerical aperture and reducing. EUV lithography technology operates at 13.5nm light with a numerical aperture of The Optical system is in vacuum and the imaging systems must be completely reflective. To be able to achieve reflectivity optics are mirror coated with multiple layers of molybdenum and silicon. A high-reflectance low stress molybdenum silicon material has excellent functionality in a 13nm wavelength environment. Figure 2 shows the major components of EUVL the projection optics and source collector optics. The major functional blocks of EUV lithography tools are the light source, reticle stage, projection optics, wafer stage, alignment systems and the focus system. Lithography performance is improved by decreasing the exposure wavelength, increasing the exposure numerical aperture, improving photoresist, improving tool stability and instituting resolution enhancement techniques. Figure 1 illustrates the projection optics transferring the reticle pattern on the wafer, while simultaneously reducing the image by four times. The process is similar to a slide projector, however with EUVL the final image is de-magnified. An EUV source uses either Synchrotron, Laser Produced Plasma (LPP) or Discharge Produced Plasma (DPP) which provides light for the micro exposure tool. 3

13 Figure 2. The major components of EUV lithography and the final pattern generated with EUV versus patterns generated with 193nm is likely to be less complex [2]. 1.3 Double Patterning Technology Double Patterning is the name of the feature density enhancement technology currently used in advanced photolithography. The resolution of photoresist patterns are adversely affected beyond the current 45nm technology node and Double Patterning can also be used in the future for 32nm and 22nm nodes. Double patterning is a popular technology due to the fact that it usess tools and technology that is already available. There are several different types of double patterning techniques which will be discussed Double Exposure Double exposure is named so due to the fact that the top photoresist layer is exposed twice with two different photo masks. A layer of photoresist is placed on the wafer. The first mask with the patterns is placed on the wafer and exposed. A second mask, usually with very different patterns, is placed on the wafer and the photoresist is 4

14 exposed again allowing for manufacturing of devices with extremely small features (See Figure 3) Figure 3. The process of double exposure patterning involves double etch and double exposure [15] Self-aligned Spacer A spacer is a film layer that is formed on the sidewall of another feature already present on the wafer. Figure 4. General process flows of self aligned double patterning. A masking material is deposited on top of a processed resist material to form a sidewall [16]. First a film is deposited on the surface of the wafer over the previous pattern. This is followed by an etching step to remove the film from the entire surface except adjacent to 5

15 the existing pattern. Next the original feature is removed leaving only the sidewalls and the spacer between them hence the name self-aligned spacer. This procedure eliminates the need for perfect alignment between several masks and exposures as is required by the double exposure procedure. The spacer approach also enables the formation of extra fine features parallel to one another. The difficulty with using the spacer approach has to do with etching the original features. It is very difficult to etch around the spacers without disturbing the spacer shapes hence one might end up with spacers that have had some underlying material removed during the etch process Double Expose, Double Etch (Mesas) This approach essentially uses the photoresist mask to create features in between the hard mask features. The mesas technology is illustrated in the following illustration: Figure 5. The processes of double exposure double etch illustrated [15]. The wafer is coated with a layer of photoresist. The photoresist is then exposed with a mask that has features in between the hard mask features. The wafer is developed leaving a layer of photoresist and a layer of pattern. The wafer is further developed and 6

16 both the pattern and the photoresist are removed leaving a series of fine patterns. The main concern with this approach is etching rates of photoresist and the pattern Double Expose, Double Etch (Trenches) The trenches technique also involves double exposure, however the wafer is coated with resist and developed and is again covered with resist and developed. This procedure is illustrated in Figure 6. Figure 6. The process of double exposure and double etch with trenches illustrated [15]. The entire wafer is coated with resist. A hard mask is used to create a pattern on the wafer. The resist is exposed and the wafer developed leaving the initial pattern. The wafer is covered with resist a second time and hard mask, similar to the previous one only a very small desired distance away, is used to create trenches when the wafer is developed. The pattern density is increased by interleaving sub patterns. 1.4 Cost of Ownership Benefits Mask costs have been significantly increasing as new technological nodes are developed. CoO is utilized to determine which technology is feasible and provides a path 7

17 to the most cost effective manufacturing process. Implementation of the CoO model can help identify areas that need process improvements. 1.5 Statement of Problem Lithography development and in particular mask costs could hinder the industry s ability to keep pace with the technological roadmap. Although EUV is the most widely supported next generation lithography to succeed the current optical lithography, there are critical issues that must be addressed before it can be implemented by all in the industry. Some of the critical issues that need to be addressed are: defect free masks, improved mask handling techniques to prevent contamination and an ultra flat EUV mask blanks to help eliminate pattern damage. Significant development on each critical issue has been made; however, there is more work to be done. In this project report we will consider EUVL as the next generation lithography and will discuss the advantages, the disadvantages, the challenges going forward and most importantly its mask Cost of Ownership. 1.6 Hypothesis The semiconductor industry is at a crossroad between Extreme Ultraviolet Lithography and Double Patterning as the next generation lithography. The hypothesis of this study will compare EUVL and DPL in solving the semiconductor industries difficulty in achieving the 32nm half pitch node and beyond. It will be shown through mask cost of ownership that EUVL is the industries next viable option. Chapter 2.0 Project Deliverables Plan and Description 8

18 The project deliverable is to assess the emerging next generation lithography and understand EUVL mask CoO. A Cost of Ownership mask model will be used in determining cost effectiveness. 2.1 Project Organization Structure Each team member has the responsibility to research one NGL technology. Every week team members have to meet one of the technical advisors and present a rough draft of each deliverable such as the project scope, literature survey or project justification. A team project structure is illustrated in Figure 7. In this project report a committee has been formed in order to support the development of the project. The committee organization is described below. Mask Cost of Ownership of Extreme Ultraviolet Lithography versus 193nm Double Patterning Team Members Committee Members Ahmad Nowbakht Manager Data Analysis Aldrin Udasco Research & Resource Dr. Ted Liang Industrial Sponsor Intel Components Research Dr. Melisa Buie Technical Advisor Coherent Inc./ San Jose State University Dr. Leonard Wesley MSE Director San Jose State University Figure 7. Project Organization Structure 9

19 2.2 Project Timeline The first part of the project has four major phases, all of which are to be completed the second week of April 2009 as illustrated in Figure 33. Each phase has sub categories that need to be delivered on a specific date. All of the four major deliverables need to be reviewed by the technical advisors to allow the team members to be aligned with the project topic. In the first phase of the project team members are responsiblee for gathering dataa and presenting it in a report format. The second phase of the project involves a more detailed actual calculation of EUVL mask CoO and will start immediately after the final project presentation on ENGR281 and needs to be completed by second week of October Figure 8. As illustrated from the Gantt chart the project has four major phases. 10

20 Figure 9. Milestones chart for the project. Figure 9 is the milestones chart showing the progress of the project base on the Gantt chart. Green color is assigned to tasks that are completed and delivered and blue color is assigned to tasks that are still pending. These charts make the team aware of each deliverables to be submitted ahead of time. 11

21 2.3 Project Scope The project will deal mainly with EUVL mask CoO and will justify its cost effectiveness as the NGL. Implementing mask CoO analysis is valuable in every technology in order to look for areas of improvement and development. 2.4 Literature Survey This section of the project study deals mainly on all literature research on EUVL mask CoO. In this phase, the project scope will be further developed and the team members will have more in depth and thorough understanding about the project scope. All researched literature will be referenced and citations of previous works will be done according to American Psychological Association (APA) format. Literature survey phase has 16 days to be completed. 2.5 Economic Justification Economic justification will include the mask cost, mask usage and the cost impact assessment. This includes all the calculation procedure that will identify cost drivers within EUVL technology. Team members decided to have more time to research and accomplish the deliverables in this phase which has 38 days. 2.6 Final Project Scope Based on the literature review and discussions with the technical advisors it was determined that focus of the research will primarily be on viable options for next generation lithography. Two technologies were considered the EUVL and 193nm double pattering. More detailed calculation of this project to justify its cost effectiveness through mask Cost of Ownership. 12

22 Chapter 3.0 Literature Survey Cost of Ownership (CoO) is a key component in determining in evaluating a new candidate for high volume manufacturing for 32nm and beyond. This survey will consider EUVL and other viable DPL options for next generation lithography to determine the most cost effective solution. CoO measures have to be implemented before new technological processes are rolled out. CoO, by definition, is the cost of equipment employed in manufacturing including the cost associated with consumables, operating and maintaining the system, and the lifetime of the operational use of the system [17]. One of the best applications of CoO is in the semiconductor industry where lifecycle of the semiconductor chips are extensively shrinking, development cost factors need to be accurate and critical items need to be identified for future generation technologies. Figure 10. Shrinking selling price versus increase storage capacity of DRAM products over the last 35 years [17]. 13

23 Figure 10 is an example representing a trend-line of shrinking selling price versus increase storage capacity of DRAM products over the last 35 years. Although, the selling prices have decreased tremendously the cost of process has remained relatively the same. Lowering the cost of process through next generation lithography is the main motivation behind this study. 3.1 Cost of Ownership Project Assumptions In this project study major assumptions are needed to be made in order to provide a relative assessment of viable next generation lithography processes. The main assumptions are that both technologies are equally reliable and support equal yield [18] and that both technologies meet manufacturing requirements. With these assumptions CoO analysis will continue to improve the process models when available and highlight the areas that need to be further developed. 3.2 Cost of Ownership Model There are different types of models for CoO analysis with several parameters of information that need to be gathered. The model has the ability to quickly generate results once there are changes in the process. Gathering different sources of information will require extensive technical and analytical skills. Figure 11 shows the CoO model s primary factors to be considered. In this project study we will primarily consider the CoO of one single critical mask. In order to obtain a preliminary model the sources of information need to be identified and the quality of data needs to be determined [19]. 14

24 Figure 11. Cost of Ownership model s primary factors [19]. 3.3 Cost of Ownership Calculation Method From the literature survey, lithography CoO includes the capital cost of the lithography cell equipment, consumable costs including photoresist, reticle, labor and facilities cost necessary to install and support the equipment [20]. Included in the CoO calculation are lithography process steps, tool cost, throughput time and yield. Our CoO calculation will be based on the model used by the Semiconductor Manufacturing Technology (SEMATECH). Other process costs such as non lithography cost were provided by International SEMATECH Manufacturing Initiative (ISMI). There were two models used to estimate tool prices. First is the historical data of tool price versus information rate and second is the historical data of leading edge tool prices versus time [18]. These models concluded that prices generally agreed. Calculation of CoO for lithography is shown in Equation 3 [21]. The model Equation calculations will depend on all key assumption parameters. Some parameters will significantly affect the CoO output. 15

25 where is the Cost of Ownership ($/wafer), are the fixed costs associated with depreciation of floor space ($/yr), are the recurring costs associated with utilities, consumables, and labor ($/yr), are the materials costs, such as resist ($/wafer), are all other costs ($/wafer). is the throughput (wafer/hr), is the tool utilization (%) and is the yield (%) Cost of Ownership Model Parameters The four principal drivers of CoO include mask usage, mask cost, tool throughput and tool cost. According Muzio [6,22] for manufacturers with low mask usage the masks write step is the biggest driver of mask level CoO, however, manufacturers with high mask usage should concentrate improvement efforts on tool throughput and tool cost. Mask usage consideration of the recent average industry survey, low mask usage is 500 wafers per mask (WPM) and high usage is 800 WPM. International SEMATECH defines mask usage as the number of wafers that are exposed by a single mask during its whole lifetime [22]. 16

26 Figure 12. Figure illustrates that mask cost obtain also impacts final wafer level cost. DRAM and microprocessor manufacturers have high mask usage values as compared to logic and ASIC manufacturers [24]. Mask cost are estimated by modeling the mask making process and assuming a production volume of 100 masks per week of a single mask type [22]. This assumption may not reflect the ideal production environment but is necessary for comparing the two technologies. However, this assumption would not compromise the model s ability to predict mask cost drivers. Tool throughput is another parameter to be considered in CoO model. The most common assumptions made are wafer size, chip size, and field size. The final key cost contributor is tool cost. Tool cost is the capital cost of the tool itself [22, 24]. It is based on historical trends and business information from the semiconductor industry. Figure 13 shows the exponential historical growth of the tool cost from 1975 to The Figure also emphasizes that the projected tool cost on every technological node are all within the historical trend. 17

27 Figure 13. Projected tool cost (all technological nodes) and Historical Trend [22]. As stated in section 3.1 the CoO project assumptions were made that EUVL and Double Patterning Lithography are equally reliable and support equal yield. Although these assumption may not be realistic, they are only used to create a comparative model. There is currently no quantitative basis to justify other assumptions besides those mentioned. The list of parameters used in this study is shown in Table 1 with the comparison of EUVL and DPL under 32nm half pitch. Lithography s main cost drivers such as tool cost, throughput mask cost are determined and in DPL reticle cost are doubled. The reticle cost of High Index immersion lithography at 22nm is also doubled. Tool throughput values will be based on historical extrapolation of previous technological nodes. Both EUVL tool cost and throughput will contribute significantly to the CoO calculations. However, DPL costs more due to the use of two litho and two etch steps as compared to EUVL. 18

28 Table 1. Technological node comparison of EUVL and DPL s four major cost drivers at 32nm and 22nm nodes [18]. 45nm half pitch 32nm half pitch ArFi SE ArFi DPL LELE Freeze Spacer HI ArFi EUVL Tool Cost $40M $49 $49 $49 $50M $54M Throughput/wph Tool Cost/TPT (M$/wph) Reticle cost $200k $600k $600k $500k $400k $180k 45nm half pitch 22nm half pitch ArFi SE ArFi DPL LELE Freeze Spacer HI ArFi EUVL Tool Cost $40M $52M $52M $52M $53M $89M Throughput/wph Tool Cost/TPT (M$/wph) Reticle cost $200k $1200k $1200k $800k $1200k $300k Viable Option of Future Lithography Process Flow To facilitate comparative CoO modeling of the two viable options of next generation lithography, we considered EUVL and DPL for 45nm and beyond. There are three major DPL processes. The first process is defined as litho-etch-litho-etch (LELE). In this process after the initial exposure the mask is develop and the developed image is used to etch the desired pattern into hard mask stack. Finally, the hard mask design is used to transfer the pattern onto the wafer [18]. Another DPL technique is the litho-lithoetch (LLE) in which the first mask is fixed in the photoresist before recoating and the second exposure, thus eliminating an intermediate etching step [21]. In the third DPL technique the spacer mask is exposed only once with the primary pattern after development and etch sidewalls are conformally deposited on all sides of the pattern [18]. 19

29 Moreover, the sidewalls can be used as a mask for subsequent etching. The trim pattern is exposed to remove the line ends as illustrated in Figure 14. In contrast, EUVL has a single exposure and features have simple optical proximity correction (OPC). Figure 14. Next generation lithography process steps [18,21]. 3.4 Advantages and Disadvantages of EUVL and DPL for 32nm half pitch. Each major DPL technique has certain advantages and disadvantages. The main advantage of LELE and LLE DPL has no fundamental limitations on 22nm technology due to better scalability and finer feature in line-edge and line width roughness and critical dimension uniformities as illustrated in Figure 15. The main advantage of this technology for 32nm node is that it builds on the existing platforms and has excellent critical dimension control. LELE approach requires just normal scaling from the approaches for larger nodes [32]. The main overall disadvantage of this technique is that it requires essentially double lithography process which increases the Cost of Ownership and overlay control which requires accurate overlay metrology. As for EUVL the main advantages is the potential extendibility. EUVL technology allows the reduction in 20

30 numerical aperture and a reduction in the lithography quality and complexity, k 1, while maintaining the improved resolution. The higher the k 1 the less proximity effects as illustrated in Figure 17. Also, EUVL uses single exposure technique which reduces the Cost of Ownership. However the major disadvantage is the tools involved in this technology which is very expensive. There are three major concerns on EUVL namely the source power availability of EUV light source with sufficient power for high throughput imaging, mask defect inspection and resist performance [32]. However, there have been significant developments on these areas. (a) First mask (b) Second mask (c) Final mask Figure 15. Layout decomposition for core pattern with aggressive double patterning lithography [23]. (a) (b) Figure 16. Figure 16(a) shows a standard mask process using EUVL having finer features and Figure 16(b) shows a 193nm using optical proximity correction process not having very fine features [29]. 21

31 (a) (b) Figure 17. The printed mask of 193nm DPL and EUVL mask s tight critical layer [13]. Illustrated in Figures 16 and 17 are the printed mask of 193nm DPL and EUVL mask s tight critical layer. EUVL needs less complex OPC as compared to 193nm DPL due to its ability to print finer features. 3.5 Preliminary Cost of Ownership Calculation Procedure Baseline assumptions were given in section 3.1. For these two technologies we need to calculate only one critical layer for comparison to determine which the most cost effective NGL is. In order to establish and calculate the CoO for each process flow we considered a process flow which include litho, deposition, etch, metrology and clean as illustrated in Equation 4. The total CoO is the summation of the process cost multiplied by the number of processs steps. Mask cost is determined in Equation 5. EUV mask cost predicted is twice the data growth and DPL is 2.5 the data growth. Mask yield based on ITRS difficulty, for EUVL it is considered to be 77% and DPL is 63% %. Utilization is fixed at 83% and yield at 98% for all technologies. There are almost 250 total parameters. Σ

32 Another factor to consider in CoO calculation is the process flow. The process flows were used as generic representation for EUVL and DPL. Figure 18 illustrates the process of each three DPL techniques, single exposure applies to EUVL. Figure 18. Process flow of EUVL and DPL (Single exposure applies to EUVL) [ 22, 24]. Other parameters to be considered such as equipment cost, consumable cost, power consumption, throughput time, labor, facilities and utilities cost will be included and discussed during the second phase of the project. The main CoO calculation done in the fall of 2009 to determine which is the most cost effective next generation lithography from 32nm and beyond. Another factor included in the calculation is how many times number of process steps occurs in each process flow as illustrated in Table 20 appendix. 23

33 Chapter 4.0 Economic Justification 4.1 Intel Mask of Cost of Ownership Executive Summary Conventional lithography has been the main tool in wafer processing for the past four decades. However, as device geometries shrink, developers of modern integrated circuit devices are no longer able to use conventional lithography to produce state of the art devices. A next generation lithography techniques needs to emerge to help the industry keep up with Moore s prediction of doubling the number of transistors on devices every two years. Double Pattern Lithography and Extreme Ultra Violet Lithography are two technologies at the forefront of NGL search. Our project used Mask Cost of Ownership to determine which of the two options was most viable for the semiconductor industry. Next generation lithography is in high demand among microprocessor and memory manufacturers as they are at the forefront of semiconductor technology. These two segments are responsible for producing devices for personal computing, mobile devices, telecommunications, automotive and healthcare. Although there are other competitors for next generation lithography the main competitors is DPL technology. However, DPL technology requires double the amount of masks to produce the same results which increases fabrication cost tremendously as will be explained. To bring up a new fab facility incorporating EUVL technology the costs will range anywhere from three to seven billion dollars. Capital and material cost, in general, increase by 120% per node [39]. Our customer Intel will establish a new fabrication facility using EUVL technology which will start producing wafers at the end of As our research indicated, there are approximately 250 million personal computers shipped 24

34 each year. Given these numbers, Intel will break even after shipping a total of 180 million units which will be the first year they incorporate EUVL technology. Intel s revenue using EVUL after three years will be approximately $60 billion Problem Statement Lithography is one of the most costly steps, if not the most costly step, in semiconductor manufacturing and is estimated to be roughly one-third of the total fabrication cost. Conventional lithography has been the main tool in wafer processing for the past four decades. However, as device geometries shrink, developers of modern integrated circuit devices are no longer able to use conventional lithography to produce state of the art devices. A next generation lithography techniques needs to emerge to help the industry keep up with Moore s prediction of doubling the number of transistors on devices every two years. Double Pattern Lithography and Extreme Ultra Violet Lithography are two technologies at the forefront of this search. Our project used Mask Cost of Ownership to determine which of the two options was most viable for the semiconductor industry Solution and Containment The manufacturing cost in this model is difficult to establish. CoO calculation is based on the relative commercial price of a high end mask for 65nm half pitch node at $120,000 [39]. Capital and material cost, in general, increase by 120% per node [39]. High end mask layers in lithography represent 15-20% of the entire device fabrication cost. Our model identifies EUVL and double patterning technical specifications such as the throughput and yield and as for the economic specifications we consider capital, maintenance labor and clean room cost. CoO model system utilizes the mask 25

35 manufacturing toolset as a single factory unit. The major advantage of this model is the ability to quickly generate results once changes are made. The approach of the model is an alternative method to derive mask cost within a shorter period of time. Based on this model and parameters we can determine the mask cost for the new given technology Customers The main demand of NGL is mainly for microprocessor and flash memory. The main customers for this segment of the semiconductor industry include personal computing, mobile devices, telecommunications, automotive and healthcare. There are several types microprocessors in the market customized for the need and the type of usage. Flash memory is categorized by volatile and non volatile. There are different ways to view non volatile market share. Figure 19 shows that the market revenues grew by 18% driven once again by growth in Figure 19. Illustrate the make-up of the non volatile memory market in both 2007 and 2008 [40]. 26

36 The costs associated with a modern integrated circuit manufacturing facility have been growing exponentially [38]. Rapid technological changes and the need to stay competitive have forced the top manufacturers to spend enormous money in research and development. Figure 19 shows the history of global semiconductor research and development plotted over a period of close to 30 years [40]. Semiconductor industry is the second top research and development spender for technological product development behind the pharmaceutical and biotech industry. Figure 20. Semiconductor industry is the second leading R&D spender behind Pharmaceuticals and biotech [43] Intel s Capital Spending The dynamics of the microprocessor market drives intense competition, making it impossible for any competitor to monopolize the market. Figure 20 shows Intel s capital 27

37 spending on research and development and that they are keen to win customer s business not just on microprocessor prices, but all aspects of its product including quality, performance and reliability [44]. Intel s capital spending enable it to be two technological generations ahead of their main rival and competitor Advanced Micro Devices (AMD). Figure. 21. Intel s capital spending trend over the last two decades shows a continuous commitment to spend on developing new technology and staying ahead of its competitors [44] Market Share Since the inception of EVUL there have been numerous technical hurdles facing this technology. At times EUVL technical hurdles have been looked at as insurmountable but there have been gradual advances and it has gained enormous momentum in being the leading candidate for next generation lithography. This technology will be able to print finer features and will enable the manufacturing of faster and power efficient microprocessors. There are only two major companies competing for global microprocessor unit market share namely, Intel and AMD. Intel has maintained a 28

38 large market share in microprocessor space. Table 2 represents overall microprocessor market share. Table 2. Global microprocessor market share [47]. Personal desktop computers shipments were 69.9 million units, up 12.1% increase as compared last year, mostly due to a very strong notebook sector, 30% growth. There were approximately 250 million personal computers shipped in 2007 and This trend is expected to hold steady for 2009 and increase in 2010 and beyond with the worldwide demand of personal computers. With 80% market share, Intel has been shipping roughly 200 million microprocessors. This number will be very useful in calculating the break even analysis. The increase in demand allowed both Intel and AMD to maintain its prices [47] Overall Device Cost Trend One of the reasons for the application of CoO to implementation of any new technology is that lifecycle of semiconductor products is constantly shrinking and cost factors for future generation need to be very accurate [17]. There is a reduction of cost per function of 30-35% per year, and this reduction is typically from device improvements, better yield, miniaturization and productivity gains [5]. 29

39 To illustrate further, a Dynamic Random Access Memory (DRAM) device is set as an example. This device has roughly 22 layers, five critical and seven middle layers. At 32nm technology node the manufacturing cost is higher using EUVL technology as opposed to using DPL technologies. At 22nm technology node the manufacturing cost using EUVL will be less than using DPL technologies, as illustrated Figure 22, due to the maturation of the EUVL technology and being fully developed. Figure 22. Total lithography cost per function for future technologies at 20,000 wafers/mask [25]. Based on McClean [40] report 2009 edition, the semiconductor industry has been one of the fastest growing industries becausee it has always offered a significantly lower price per function such as price per bit of memory or price per transistor to the electronic system producer [40]. Figure 23 shows the percentage of greatest contribution in reducing cost. Reducing the feature size will continue to be the largest contributor in cost reduction and ncreasing equipment productivity of processing equipment is another cost reduction contributor. 30

40 Figure 23. Contribution to reductions in cost per function [46] Time to Market Introducing a new technology to market is a process that begins when resources are assigned to assess the product feasibility and ends when customer orders are placed for the production unit. The manufacturer or organization that introduces a product or service first to the market will usually reap the rewards that come with being first to market. Intel is the first semiconductor company to fully developed EUVL technology and is about to introduce a new device to the market using EUVL technology. Intel s ticktock model delivers new silicon process technology, dramatically increasing transistor density while enhancing performance and energy efficiency within smaller and more refined existing micro architecture. While the tock model represents entirely new processor architecture to optimize the value of the increased number of transistors [41-42]. This model has been developed and successfully alternated and delivered the next generation silicon technology as well as new processor micro architecture year after year [41]. The benefit of being first to introduce a new product to consumers is always associated to business gain or profit. An example is illustrated in Figure 24 where 31

41 company A started developing a product and subsequently introduced that product to the market at the right time, while company B started developing at a later time hence introducing the product late to market. Figure 24. Advantage of first to market [17,25]. By introducing the product at time equals to zero, company A receives the highest price for its product. As it ramps production, the cost obtained for the product decreases. The overall impact is that revenue grows but the cost per product decreases. While company B receives a lower introductory price based on market availability but as full production of the product is realized company B is then able charge for a higher price. Intel s cycle time, the tick-tock model, has been the basis in developing new product architecture at Intel. Moreover, Intel has a unique in-house research, development and manufacturing capability that enable it to successfully develop leading edge technologies. By this model, Intel is leading two technological generations against its rival competitor 32

42 AMD. Fast cycle time will definitely improve customer satisfaction and internal operations of a company Cost of Ownership Calculation Procedure Lists of primary factors given in Figure 11 were considered in calculating the mask Cost of Ownership. Also to make the calculation more reliable, Cost of Ownership is simply described as the ratio of cost to produce wafers over the number of wafers produced. This section illustrates all the parameters involved in the calculation to determine the most effective next generation lithography. Table 3. Cost of Ownership calculation procedure 1 Calculate fixed cost (C fixed ) and recurring cost ( C recurring ) per year 2 Calculate numbers of good wafers per year N gwpy 3 Calculate cost per good wafer for fixed and recurring cost by dividing annual fixed and recurring cost by the number of good wafer per year 4 Add other cost per wafer Number of good wafer per year is determined by the throughput, utilization and yield of the tool as illustrated in Table 4, while fixed cost and recurring cost are calculated on annual basis over the number of good wafers per year. Tables 4, 5, 6 and 7 are defined parameters used in the calculation of mask Cost of Ownership. The Tables illustrate more details on the each calculation procedure and final values are illustrated in Tables 9 and 10. Another section of the report shows the more details and broken down calculation procedure on each next generation lithography process. 33

43 Table 4. Number of good wafer per year Description Parameter Input Parameter Calculation Procedure Number of good wafers per year Utilization U (%) Gross troughput N gwpy [wafer/yr] Gross Throughput Tp gross [wafer/h] T gross [wafer/h] Utilization U[%] Yied [%] E_10 Eng [10%]: Engineering time, standby time, schedule downtime. E_10 Down[%]: Unscheduled downtime, unschedule time. N gwpy [wafer/yr]= Tpgross [wafer/h] * U [%] * Y [%] * 24*365 [hr/yr] U [5%] = 100% - E10_Eng_Down[%} TP gross [wafer/h] = Raw Throughput, TP raw [wafer/h] 3600/(3600/TPraw [wafer/h] + T cascade [sec] Lot cascading time T cascade = 0 sec Note: For T cascade = 0 sec, TP gross = TPraw Number of wafers per lot N wp [wafer] E10_Down and E10_Eng are defined as the tool utilization for unscheduled maintenance and scheduled downtime for engineering tool time for process improvement. A more detailed representation is in Figure 25. Figure 25. The graph shows the definition of E10_Down and E10_Eng which are used in the calculation of tool utilization [21,24]. 34

44 Availability of toolsets will greatly impact the number of throughput produced in a given day. Through literature survey on lithography toolsets the tool utilization has been established and fixed at 83 percent as previously stated. Table 5 list are the major contributing factors considered when calculating fixed cost. Fixed cost includes the depreciation, installation and floor space and it was determined using the formula given in Table 5. Other fixed and recurring costs are not included such as system qualification and training under equipment description. Also not included are supplies such as bulk gases, waste disposal, scrap and support services in which their contribution is assumed to be negligible. Fixed and recurring cost are calculated on annual basis then divided by the number of good wafer per year. Table 5. Fixed cost is calculated on annual basis then divided by number of good wafer year. Description Cost Parameter Input Parameters Calculation Procedure Equipment Cost Parameter Depreciation C depr,equip [$/yr] Capital cost C capital [$] Cdepr,equip [$/yr] = Ccapital [$] / η T depr,equip [yr] Depreciation period, η Tdepr,equip [yr] Installation C depr,equip [$/yr] Installation cost, C install [$] C depr,equip [$/yr] = Cinstall [$] / η Tdepr,equip [yr] Floor Space C space [$/yr] Depreciation period, η Tdepr,equip [yr] Tool foot print A tool [ft 2 ] : Add to foot print 1/2 yard on each side to account for ailes. With 1/2 yard from neighboring tool, that gives yard in between (sematech 2008) Floor space rate a space [$/ft 2 /yr] Clean room construction cost a constr ($/ft 2 ) Depreciation period, η Tdepr,[yr] C install [$/yr] = a install [%] * C equip [$/yr], with a install [%] a factor depending tool type Cspace [$/yr] = ( a space [s/ft 2 ] / η T depr, constr [yr] ) * Atool [ft2] 35

45 Table 6. Recurring cost is also calculated on annual basis then divided by the number of good wafer per year. Description Cost Parameter Input Parameters Calculation Procedure Materials Utilities Electricity C el [$/yr] Power consumption, P[kW] C el [$/yr] = P[kW]* 24 * 365 h/yr * a el [$/kwhr] Consumables Litho Tool C consum, litho [$/yr] Average laser/source pulse count, N source [B pulse/yr ] C consum, litho [$/yr] = Nsource [Bpulse/yr]* C consum,stepper [$/B pulse ] + Nsource [Bpulse/yr]* C consume,source [$/Bpulse] + C replacement [$/yr] Stepper consumable cost, C consume,stepper [$/Bpulse] Stepper consumable cost, C consume,source [$/Bpulse] Other replacement C replace [$/yr] Other tools C consum, [$/yr] Maintenance Service Contracts C contract, [$/yr] Labor C labor,operator [$/yr] = Operation C labor,operation [$/yr] Number of opeators per system, N operator N operator * a labor,operator [$/h] * 24 * 365 h/yr Operator labor rate, a labor,operator [$/h] Equipment Specialist C labor,equipment [$/yr] Equipment specialist labor rate a labor,operator [$/hr] C labor, equipment [$/yr] = N operator * a labor,equipment [$/h] * 24 * 365 h/yr Supervision Engineering Number of supervisors per system, C support,supervision [$/yr] N supervisor C support,engineering [$/yr] C support,sepervision [$/yr] = N supervisor * a support, supervisor [$/yr] Supervisor labor rate, a support,supervisor [$/hr] Number of engineers per system C support,engineering [$/yr] = N eng N eng * a support, eng [$/yr] Engineering labor rate, a support,eng [$/yr] 36

46 Table 7. Other Cost calculated per wafer. Description Cost Parameter Input Parameters Calculation Procedure Other Reticle C reticle,wafer [$/wafer] Reticle cost, C reticle [$] Number of wafers per reticle, N wpr C reticle,wafer [$/wafer] = C reticle [$] / N wpr Resist C resist [$/wafer] Resist cost, C resist [$/gallon] C resist [$/wafer] = (C resist [$/gallon] /3785 * V resist [ml/wafer Resist usage per wafer, V resist [ml/wafer] 3785 = ml/gallon BARC, Top coat C ARC [$/wafer] Analogous to resist Analogous to resist Standard rates based on SEMATECH (2007) Depreciation Values Life of Equipment (yr) 7 Depreciation Life (yr) 5 Salvage Value of Equipment $0.00 Clean room, buildings (yr) 25 Depreciation Schedule straight line Labor and Overhead Engineering $ Supervisor $ Operator $33.06 Maintenance/hour $39.67 Productivity 80.00% Fab Space Rates ( $/sqft/yr) Class 100 $ Class 10 $ Class 1 $ Installation Cost as % Equipment Cost Lithography 8.00% Metrology 5.00% Other 12.00% Scheduled Production Hours/week/shift 42 Shift/week 4 Hours/day 24 days/year 365 suppliers shifts/weeks 4 Table 8. Global Parameters Inflation rate Year ( % % % % % Construction rates ($/sqft) Clean room $4, Non Clean room $ Non Manufacturing $

47 Cost of Ownership Calculation Results The next list of tables contains an overview and the result of cost ownership calculations between EUVL and different options of 193nm double patterning. Table 9 below is an overview of lithography calculations for 32nm pitch process. It compares the current 45nm process with some viable next generation replacements. Included in the comparison are: Single Exposure, Double Patterning and Extreme Ultra Violet technologies. Each cost parameter will be broken down in more detail in subsequent Tables. Cost of Ownership 32nm half pitch lithography calculations results. Table 9. Overview lithography calculations at 32nm half pitch process. Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE Good wafers/year Raw Throughput (wafers/h) Gross Throughput (wafers/h) Utilitzation (%) 83% 83% 83% 83% 83% 83% Yield (%) 98% 98% 98% 98% 98% 98% Good Throughput (wafers/h) Good wafers/year (wafers/year) 855,046 1,245,213 1,245,213 1,245, , ,325 Tool equipment Cost Total annual equipment cost ($/yr) $8,080,000 $9,520,000 $9,520,000 $9,520,000 $9,840,000 $10,800,000 Consumables, Replacement Parts Cost Total annual consumables ($/yr) $3,459,100 $4,598,350 $4,598,350 $4,598,350 $3,773,800 $3,649,400 32nm EUVL Utilities Cost Total annual utilities cost ($/yr) $23,792 $23,792 $23,792 $23,792 $23,792 $128,772 Facilities Cost Total annual facilities cost ($/yr) $372,321 $372,321 $372,321 $372,321 $372,321 $349,827 Labor Cost Total annual labor cost ($/yr) $404,700 $404,700 $404,700 $404,700 $404,700 $404,700 Reticle Cost Total reticle cost ($/wafer) $10.00 $30.00 $30.00 $25.00 $20.00 $9.00 Materials Cost Total materials cost ($/wafer) $2.75 $2.75 $2.75 $2.75 $2.75 $

48 Table 10 summarizes some of the detailed calculations of lithography process cost. The overview parameters in Table 9 are a direct result of the more detailed calculations done to achieve Table 10. The parameters and values highlighted in blue are ones that are assumed. The parameter and values highlighted in black are ones that are calculated Half-pitch and Process Table 10. Details lithography calculations at 32nm half pitch process. 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Good wafers/year Raw Throughput (wafers/hour) Wafers nunber/lot (wafers/lot) Lot cascading time (sec) Gross Throughput (wafers/hour) Stepper uptime 93% 93% 93% 93% 93% 93% Track uptime 92% 92% 92% 92% 92% 92% Standby, engineering time 20% 20% 20% 20% 20% 15% E_10_ENG(Engineering time, Standby time, Scheduled downtime) % 2% 2% 2% 2% 2% 2% E_10_DOWN(Unscheduled downtime, Unscheduled time) % 15% 15% 15% 15% 15% 15% Utilization( U= 1 - E_10_Eng - E_10_down ) ( %) 83% 83% 83% 83% 83% 83% Utilization 66% 66% 66% 66% 66% 71% Net Throughput (wafers/hr) Yield (%) 98% 98% 98% 98% 98% 98% Good Throughput (wafers/hour) Good wafers/day (wafers/day) Good wafers/year (wafers/year) 855,046 1,245,213 1,245,213 1,245, , ,325 Total Equipment Cost Stepper price ($) $40,000,000 $49,000,000 $49,000,000 $49,000,000 $50,000,000 $55,000,000 Stepper installation cost ($) $3,200,000 $3,900,000 $3,900,000 $3,900,000 $3,900,000 $4,500,000 Annual stepper depreciation ($/yr) $6,400,000 $7,840,000 $7,840,000 $7,840,000 $8,000,000 $8,800,000 Annual stepper service contract ($/y) $300,000 $300,000 $300,000 $300,000 $300,000 $300,000 Track price ($) $8,000,000 $8,000,000 $8,000,000 $8,000,000 $9,000,000 $10,000,000 Track installation cost ($) $400,000 $400,000 $400,000 $400,000 $400,000 $450,000 Annual track depreciation ($/yr) $1,280,000 $1,280,000 $1,280,000 $1,280,000 $1,440,000 $1,600,000 Annual track service contract ($/yr) $100,000 $100,000 $100,000 $100,000 $100,000 $100,000 Total annual equipment cost ($/yr) $8,080,000 $9,520,000 $9,520,000 $9,520,000 $9,840,000 $10,800,000 Table 10 shows the itemized calculation results of good wafer per year, gross throughput per year, utilization of equipment and the total equipment cost on each technology. Scheduled tool downtime and engineering tool time usage is define in Figure

49 Table 10. Details lithography calculations at 32nm half pitch process (continued). Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Consumables, Replacement Parts Cost Average laser pulse count (billion pulse/yr) Stepper consumable cost (billion pulse/yr) $34,900 $34,900 $34,900 $34,900 $45,600 $27,200 Annual stepper consumable cost ($/yr) $1,486,740 $1,999,770 $1,999,770 $1,999,770 $1,869,600 $1,414,400 Laser consumable cost ($/yr) $42,600 $42,600 $42,600 $42,600 $42,600 $40,000 Annual laser/source consumble cost ($/yr) $1,814,760 $2,440,980 $2,440,980 $2,440,980 $1,746,600 $2,080,000 Annual other replacement parts cost ($/yr) $115,000 $115,000 $115,000 $115,000 $115,000 $115,000 Total annual consumables ($/yr) $3,459,100 $4,598,350 $4,598,350 $4,598,350 $3,773,800 $3,649,400 Utilities Cost Stepper electrical power (kw) Track electrical power (kw) Electricity cost ($/kwh) $0.07 $0.07 $0.07 $0.07 $0.07 $0.07 Annual electricity cost ($/yr) $23,792 $23,792 $23,792 $23,792 $23,792 $128,772 Total annual utilities cost ($/yr) $23,792 $23,792 $23,792 $23,792 $23,792 $128,772 Facilities Cost Exposure tool foot print (ft^2) Exposure tool foot print including aisles, etc. (ft^2) Track foot print Track tool foot print including aisles, etc. (ft^2) Litho cell main floor foot print (ft^2) Annual cleanroom depreciation ($/yr) $96,528 $96,528 $96,528 $96,528 $96,528 $90,696 Annual cleanroom maintenance cost ($/yr) $275,793 $275,793 $275,793 $275,793 $275,793 $259,131 Total annual facilities $372,321 $372,321 $372,321 $372,321 $372,321 $349,827 Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Labor Cost Engineer annual cost ($/yr) $145,000 $145,000 $145,000 $145,000 $145,000 $145,000 Average number of engineers/tool ($/yr) Total annual engineers cost/tool ($/yr) $29,000 $29,000 $29,000 $29,000 $29,000 $29,000 Total annual engineer cost/tool(litho/cell) ($/yr) $58,000 $58,000 $58,000 $58,000 $58,000 $58,000 Supervisor annual cost ($/yr) $145,000 $145,000 $145,000 $145,000 $145,000 $145,000 Average number of supervisor/tool Total annual supervisor cost/tool ($/yr) $4,350 $4,350 $4,350 $4,350 $4,350 $4,350 Total annual supervisor cost (litho/cell) ($/yr) $8,700 $8,700 $8,700 $8,700 $8,700 $8,700 Operator annual cost($/yr) $300,000 $300,000 $300,000 $300,000 $300,000 $300,000 Average number of operators/tool ($/yr) Total annual operator cost /tool ($/yr) $99,000 $99,000 $99,000 $99,000 $99,000 $99,000 Total annual operator cost (litho/cell) ($/yr) $198,000 $198,000 $198,000 $198,000 $198,000 $198,000 Equipment specialist cost/tool ($/yr) $350,000 $350,000 $350,000 $350,000 $350,000 $350,000 Average number of equipment specialist/tool Total annual equipment specialist/tool ($/yr) $70,000 $70,000 $70,000 $70,000 $70,000 $70,000 Total annual equipment specialist cost/(litho/cell) ($/yr) $140,000 $140,000 $140,000 $140,000 $140,000 $140,000 Total annual labor cost $404,700 $404,700 $404,700 $404,700 $404,700 $404,700 Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Reticle Cost Reticle cost 1 ($/reticle) $200,000 $300,000 $300,000 $250,000 $400,000 $180,000 Reticle cost 2 (DPL) ($/reticle) $0 $300,000 $300,000 $250,000 $0 $0 Number of wafers/reticle (wafers/reticle) 20,000 20,000 20,000 20,000 20,000 20,000 Reticle cost 1 ($/wafer) $10.00 $15.00 $15.00 $12.50 $20.00 $9.00 Reticle 2 cost (DPL) ($/wafer) $0.00 $15.00 $15.00 $12.50 $0.00 $0.00 Total reticle cost ($/wafer) $10.00 $30.00 $30.00 $25.00 $20.00 $

50 Table 10. Details lithography calculations at 32nm half pitch process (continued). Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Material Cost Resist cost ($/gallon) $4,000 $4,000 $4,000 $4,000 $4,000 $5,000 Resist usage (ml/wafer) Total resist cost ($/wafer) $1.69 $1.69 $1.69 $1.69 $1.69 $2.11 Top coat cost ($/gallon) $2,500 $2,500 $2,500 $2,500 $2,500 $0 Top coat usage (ml/wafer) Total top coat cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $1.06 $0.00 BARC cost ($/gallon) $2,500 $2,500 $2,500 $2,500 $2,500 $0 BARC usage (ml/wafer) Total BARC cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $1.06 $0.00 Total material cost $2.75 $2.75 $2.75 $2.75 $2.75 $2.11 Half-pitch and Process 45nm ArFi SE 32nm ArFi DPL LELE 32nm ArFi DPL Freeze 32nm ArFi DPL Spacer 32nm HI ArF SE 32nm EUVL Cost of Ownership Equipment cost $9.45 $7.65 $7.65 $7.65 $11.74 $30.57 Stepper depreciation ($/wafer) $7.48 $6.30 $6.30 $6.30 $9.54 $24.91 Stepper service contract ($/wafer) $0.35 $0.24 $0.24 $0.24 $0.36 $0.85 Track depreciation ($/wafer) $1.50 $1.03 $1.03 $1.03 $1.72 $4.53 Track service contract ($/wafer) $0.12 $0.08 $0.08 $0.08 $0.12 $0.28 Consumables, Replacements Parts Cost ($/wafer) $4.00 $3.66 $3.66 $3.66 $4.45 $10.22 Stepper consumables cost ($/wafer) $1.74 $1.61 $1.61 $1.61 $2.23 $4.00 Laser/source consumable cost ($/wafer) $2.12 $1.96 $1.96 $1.96 $2.08 $5.89 Other replacement parts ($/wafer) $0.13 $0.09 $0.09 $0.09 $0.14 $0.33 Material Cost $2.75 $2.75 $2.75 $2.75 $2.75 $2.11 Resist Cost ($/wafer) $1.69 $1.69 $1.69 $1.69 $1.69 $2.11 BARC/underlayer cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $1.06 $0.00 Utilities Cost $0.03 $0.02 $0.02 $0.02 $0.03 $0.36 Electricity cost ($/wafer) $0.03 $0.02 $0.02 $0.02 $0.03 $0.36 Facilities Cost $0.44 $0.30 $0.30 $0.30 $0.44 $0.99 Cleanroom construction depreciation ($/wafer) $0.11 $0.08 $0.08 $0.08 $0.12 $0.26 Annual cleanroom maintenance cost ($/wafer) $0.32 $0.22 $0.22 $0.22 $0.33 $0.73 Labor Cost ($/wafer) $0.47 $0.33 $0.33 $0.33 $0.48 $1.15 Engineer labor cost ($/wafer) $0.07 $0.05 $0.05 $0.05 $0.07 $0.16 Supervisor labor cost ($/wafer) $0.01 $0.01 $0.01 $0.01 $0.01 $0.02 Operator labor cost ($/wafer) $0.23 $0.16 $0.16 $0.16 $0.24 $0.56 Equipment specialist cost ($/wafer) $0.16 $0.11 $0.11 $0.11 $0.17 $0.40 Reticle cost ($/wafer) $10.00 $30.00 $30.00 $25.00 $20.00 $9.00 Reticle 1 Cost ($/wafer) $10.00 $15.00 $15.00 $12.50 $20.00 $9.00 Reticle 2 Cost ($/wafer) $0.00 $15.00 $15.00 $12.50 $0.00 $0.00 Cumulative cost of ownership $27.13 $44.69 $44.69 $39.69 $39.89 $54.40 From Table 10 the Cost of Ownership in the 32nm process increases with the next generation options. It is specifically higher for the extreme ultra violet lithography technology, almost double the current 45nm technology. If EUVL is to replace the current lithography technology cost is one parameter that has to be addressed. For the 32nm process equipment and parts are the parameters that are driving the cost up. We will further consider the next node after 32nm, which is 22nm, to evaluate further if 44

51 EUVL will be more competitive with other next generation lithography technologies. Table 11 summarizes the lithography costs for the 22nm process. It compares several double patterning technologies as opposed to extreme ultra violet lithography. Single exposure is no longer viable at this node since the features are very small and unachievable with single exposure technology. Cost of Ownership at 22nm half pitch lithography calculation results: Table 11. Overview lithography calculations at 22nm half pitch process. Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Good wafers/year Raw Throughput (wafers/h) Gross Throughput (wafers/h) Utilitzation (%) 83% 83% 83% 83% 83% Yield (%) 98% 98% 98% 98% 98% Good Throughput (wafers/h) Good wafers/year (wafers/year) 1,379,107 1,379,107 1,379, , ,857 Tool equipment Cost Total annual equipment cost ($/yr) $10,000,000 $10,000,000 $10,000,000 $10,000,000 $16,240,000 Consumables, Replacement Parts Cost Total annual consumables ($/yr) $5,094,350 $5,094,350 $5,094,350 $4,214,800 $6,710,885 Utilities Cost Total annual utilities cost ($/yr) $23,792 $23,792 $23,792 $23,792 $128,772 Facilities Cost Total annual facilities cost ($/yr) $372,321 $372,321 $372,321 $372,321 $349,827 Labor Cost Total annual labor cost ($/yr) $404,700 $404,700 $404,700 $404,700 $404,700 Reticle Cost Total reticle cost ($/wafer) $60.00 $60.00 $40.00 $60.00 $15.00 Materials Cost Total materials cost ($/wafer) $2.75 $2.75 $2.75 $2.75 $

52 Table 11. Details lithography calculations at 22nm half pitch process (continued) Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Good wafers/year Raw Throughput (wafers/hour) Wafers nunber/lot (wafers/lot) Lot cascading time (sec) Gross Throughput (wafers/hour) Stepper uptime 93% 93% 93% 93% 93% Track uptime 92% 92% 92% 92% 92% Standby, engineering time 20% 20% 20% 20% 15% E_10_ENG(Engineering time, Standby time, Scheduled downtime) % 2% 2% 2% 2% 2% E_10_DOWN(Unscheduled downtime, Unscheduled time) % 15% 15% 15% 15% 15% Utilization( U= 1 - E_10_Eng - E_10_down ) ( %) 83% 83% 83% 83% 83% Utilization 66% 66% 66% 66% 71% Net Throughput (wafers/hr) Yield (%) 98% 98% 98% 98% 98% Good Throughput (wafers/hour) Good wafers/day (wafers/day) Good wafers/year (wafers/year) 1,379,107 1,379,107 1,379, , ,857 Total Equipment Cost Stepper price ($) $52,000,000 $52,000,000 $52,000,000 $52,000,000 $89,000,000 Stepper installation cost ($) $4,160,000 $4,160,000 $4,160,000 $4,240,000 $7,120,000 Annual stepper depreciation ($/yr) $8,320,000 $8,320,000 $8,320,000 $8,320,000 $14,240,000 Annual stepper service contract ($/y) $300,000 $300,000 $300,000 $300,000 $300,000 Track price ($) $8,000,000 $8,000,000 $8,000,000 $8,000,000 $10,000,000 Track installation cost ($) $400,000 $400,000 $400,000 $400,000 $450,000 Annual track depreciation ($/yr) $1,280,000 $1,280,000 $1,280,000 $1,280,000 $1,600,000 Annual track service contract ($/yr) $100,000 $100,000 $100,000 $100,000 $100,000 Total annual equipment cost ($/yr) $10,000,000 $10,000,000 $10,000,000 $10,000,000 $16,240,000 Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Consumables, Replacement Parts Cost Average laser pulse count (billion pulse/yr) Stepper consumable cost (billion pulse/yr) $34,900 $34,900 $34,900 $45,600 $27,200 Annual stepper consumable cost ($/yr) $2,223,130 $2,223,130 $2,223,130 $2,097,600 $2,828,800 Laser consumable cost ($/yr) $42,600 $42,600 $42,600 $42,600 $35,877 Annual laser/source consumble cost ($/yr) $2,713,620 $2,713,620 $2,713,620 $1,959,600 $3,731,208 Annual other replacement parts cost ($/yr) $115,000 $115,000 $115,000 $115,000 $115,000 Total annual consumables ($/yr) $5,094,350 $5,094,350 $5,094,350 $4,214,800 $6,710,885 Utilities Cost Stepper electrical power (kw) Track electrical power (kw) Electricity cost ($/kwh) $0.07 $0.07 $0.07 $0.07 $0.07 Annual electricity cost ($/yr) $23,792 $23,792 $23,792 $23,792 $128,772 Total annual utilities cost ($/yr) $23,792 $23,792 $23,792 $23,792 $128,772 Facilities Cost Exposure tool foot print (ft^2) Exposure tool foot print including aisles, etc. (ft^2) Track foot print (ft^2) Track tool foot print including aisles, etc. (ft^2) Litho cell main floor foot print (ft^2) Annual cleanroom depreciation ($/yr) $96,528 $96,528 $96,528 $96,528 $90,696 Annual cleanroom maintenance cost ($/yr) $275,793 $275,793 $275,793 $275,793 $259,131 Total annual facilities $372,321 $372,321 $372,321 $372,321 $349,827 46

53 Table 12. Details lithography calculations at 22nm half pitch process (continued) Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Labor Cost Engineer annual cost ($/yr) $145,000 $145,000 $145,000 $145,000 $145,000 Average number of engineers/tool ($/yr) Total annual engineers cost/tool ($/yr) $29,000 $29,000 $29,000 $29,000 $29,000 Total annual engineer cost/tool(litho/cell) ($/yr) $58,000 $58,000 $58,000 $58,000 $58,000 Supervisor annual cost ($/yr) $145,000 $145,000 $145,000 $145,000 $145,000 Average number of supervisor/tool Total annual supervisor cost/tool ($/yr) $4,350 $4,350 $4,350 $4,350 $4,350 Total annual supervisor cost (litho/cell) ($/yr) $8,700 $8,700 $8,700 $8,700 $8,700 Operator annual cost($/yr) $300,000 $300,000 $300,000 $300,000 $300,000 Average number of operators/tool ($/yr) Total annual operator cost /tool ($/yr) $99,000 $99,000 $99,000 $99,000 $99,000 Total annual operator cost (litho/cell) ($/yr) $198,000 $198,000 $198,000 $198,000 $198,000 Equipment specialist cost/tool ($/yr) $350,000 $350,000 $350,000 $350,000 $350,000 Average number of equipment specialist/tool Total annual equipment specialist/tool ($/yr) $70,000 $70,000 $70,000 $70,000 $70,000 Total annual equipment specialist cost/(litho/cell) ($/yr) $140,000 $140,000 $140,000 $140,000 $140,000 Total annual labor cost $404,700 $404,700 $404,700 $404,700 $404,700 Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Reticle Cost Reticle cost 1 ($/reticle) $600,000 $600,000 $400,000 $600,000 $300,000 Reticle cost 2 (DPL) ($/reticle) $600,000 $600,000 $400,000 $600,000 $0 Number of wafers/reticle (wafers/reticle) 20,000 20,000 20,000 20,000 20,000 Reticle cost 1 ($/wafer) $30.00 $30.00 $20.00 $30.00 $15.00 Reticle 2 cost (DPL) ($/wafer) $30.00 $30.00 $20.00 $30.00 $0.00 Total reticle cost ($/wafer) $60.00 $60.00 $40.00 $60.00 $15.00 Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Material Cost Resist cost ($/gallon) $4,000 $4,000 $4,000 $4,000 $6,000 Resist usage (ml/wafer) Total resist cost ($/wafer) $1.69 $1.69 $1.69 $1.69 $2.54 Top coat cost ($/gallon) $2,500 $2,500 $2,500 $2,500 $0 Top coat usage (ml/wafer) Total top coat cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $0.00 BARC cost $2,500 $2,500 $2,500 $2,500 $0 BARC usage (ml/wafer) Total BARC cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $0.00 Total material cost $2.75 $2.75 $2.75 $2.75 $

54 Table 12. Details lithography calculations at 22nm half pitch process (continued) Half-pitch and Process 22 nm AiFi DPL LELE 22 nm AiFi DPL Freeze 22 nm AiFi DPL Spacer 22 nm Hi AiFi DPL LELE 22 nm EUVL Cost of Ownership Equipment cost $7.25 $7.25 $7.25 $10.62 $23.17 Stepper depreciation ($/wafer) $6.03 $6.03 $6.03 $8.84 $20.32 Stepper service contract ($/wafer) $0.22 $0.22 $0.22 $0.32 $0.43 Track depreciation ($/wafer) $0.93 $0.93 $0.93 $1.36 $2.28 Track service contract ($/wafer) $0.07 $0.07 $0.07 $0.11 $0.14 Consumables, Replacements Parts Cost ($/wafer) $3.66 $3.66 $3.66 $4.43 $9.52 Stepper consumables cost ($/wafer) $1.61 $1.61 $1.61 $2.23 $4.04 Laser/source consumable cost ($/wafer) $1.97 $1.97 $1.97 $2.08 $5.32 Other replacement parts ($/wafer) $0.08 $0.08 $0.08 $0.12 $0.16 Material Cost ($/wafer) $2.75 $2.75 $2.75 $2.75 $2.54 Resist Cost ($/wafer) $1.69 $1.69 $1.69 $1.69 $2.54 BARC/underlayer cost ($/wafer) $1.06 $1.06 $1.06 $1.06 $0.00 Utilities Cost ($/wafer) $0.02 $0.02 $0.02 $0.03 $0.18 Electricity cost ($/wafer) $0.02 $0.02 $0.02 $0.03 $0.18 Facilities Cost ($/wafer) $0.27 $0.27 $0.27 $0.40 $0.50 Cleanroom construction depreciation ($/wafer) $0.07 $0.07 $0.07 $0.10 $0.13 Annual cleanroom maintenance cost ($/wafer) $0.20 $0.20 $0.20 $0.29 $0.37 Labor Cost $0.29 $0.29 $0.29 $0.43 $0.58 Engineer labor cost ($/wafer) $0.04 $0.04 $0.04 $0.06 $0.08 Supervisor labor cost ($/wafer) $0.01 $0.01 $0.01 $0.01 $0.01 Operator labor cost ($/wafer) $0.14 $0.14 $0.14 $0.21 $0.28 Equipment specialist cost ($/wafer) $0.10 $0.10 $0.10 $0.15 $0.20 Reticle cost ($/wafer) $60.00 $60.00 $40.00 $60.00 $15.00 Reticle 1 Cost ($/wafer) $30.00 $30.00 $20.00 $30.00 $15.00 Reticle 2 Cost ($/wafer) $30.00 $30.00 $20.00 $30.00 $0.00 Cumulative cost of ownership $74.24 $74.24 $54.24 $78.65 $51.49 After calculating the Cost of Ownership for the 22nm node we see from the Table above that the Cost of Ownership for Extreme Ultra Violet Lithography is significantly less than the double patterning options. We realize that the equipment and parts costs still remain high however the material and reticle costs are significantly lower. This in turn lowers the Cost of Ownership for Extreme Ultra Violet Lithography for the 22nm node making it the best option for the next generation lithography. 48

55 Recommendation Based on our literature survey, mask cost of ownership is a valuable tool to analyze and identify cost reduction in deciding the next generation lithography. Mask cost is a contributing factor but often not considered from the business case perspective. Baseline assumption and current estimate indicate that mask cost, tool cost and tool throughput continue to be the major areas of high concern to the industry. Considering a mask fabrication with a low mask usage the single extensive cost driver is the mask write step. As for high mask usage manufacturers tool throughput and tool cost should be the major focus of improvement. Areas that need cost reduction should use CoO analysis that will meet the business challenges as well as future technical requirements. In support of our literature survey, Tables 9 to 12 are presented on all different mask technological processes in calculating mask Cost of Ownership concludes that at 22nm half pitch technological node, EUVL has a significant cost advantage over next generation technology such as double patterning under certain mask cost assumptions such as tool throughput and tool cost. Results show that EUVL throughput produce less than 30 wafers per hour then litho-etch-litho-etch double patterning have roughly the same cost of ownership under this assumption Method of Investigation The method we used in EUVL mask cost analysis and effectiveness involved extensive literature survey and continuous communication with our technical advisers. Technical information such as EUVL throughput, DPL processes and assumption on cost analysis was gathered through various semiconductor industries. Statistical methods such 49

56 as sampling procedure, measures of variability and graphical inspection, cost estimation analysis and applications of normal distribution were used in this study SWOT Analysis for EUVL Introducing a new technological product needs strategic decision making and analysis of the company s internal capabilities. One framework that can be used to conduct an internal analysis is called SWOT analysis. SWOT is an acronym that stands for the internal strengths and weakness of a company and the environmental opportunities and threats the company faces. The analysis provides a structured way to analyze internal capabilities and introduces objectivity into strategic decision making. EUVL main strength is to print finer feature and consider expanding the empirical law of Gordon Moore in to new technological node. Moreover as EUVL technology matures the rate of return of investment will gain revenue. However, the tradeoff of this type of lithography is the source power which likely delivers a required 180 watts of power in the system. Also mask defect inspection tools for EUVL which the source brightness is needed to compensate for the tools limited access to source power falls in the weakness category. Opportunities of EUVL technology can print complex feature and extend to next technological node. As for the threat analysis, EUVL needs to address the containment of protecting the mask through particles and the availability of defect free mask. Although there are hurdles in this technology solutions were devised and promising solutions are develop and presented. EUVL technology will be available for 32nm high volume manufacturing. 50

57 EUVL Break Even Analysis Business models are an important planning tool because they help us focus the attention of management on key profit drivers, help identify obstacles and thereby help refine strategies, also facilitate testing alternative strategies before resources are committed and lastly they can be used to test the reasonableness of goals [45]. One important tool in determining economic feasibility of a product or a process is the break-even analysis. At the break-even point total revenue equals total cost hence the break-even point. The break-even point is determined by total units sold or the total amount of sales in dollars graphed against total cost, fixed and variable. The point at which these two lines cross signifies the number below which the product or process in question will result in a total net loss and above which the product or process in question will result in a net profit. Fixed costs are costs that do not change with output such as overhead, equipment, and capital costs. Variable costs change with output which means that there is cost associate with producing additional products with the same fixed costs. Below is the break-even analysis for Intel Micro-processors using EUVL. The numbers are based on Intel earnings, capital cost estimations, and research. 51

58 Figure 26. Intel s Microprocessor EUVL Break-Even Analysis All values were extrapolated from different journals such as isuppli, SEMATECH and solid state journal in determining the break-even point [41-45]. From our survey and research it has been determined that the fixed costs associated with upgrading an Intel fab to use EUVL would be around $3 billion. This cost is for all the equipment necessary to bring up a state of the art fab to be able to develop mask using EUVL. Microprocessors range in cost from $100-$800. The high end is targeted for gaming or server markets and majority of the PCs shipped will incorporate the low end microprocessors. For our calculations it is assumed that microprocessors are valued at $120 each. Each microprocessor is calculated to cost around $80 which is 50% margin. As illustrated from the graph that the break- even point when total cost equals the total revenue. This point is determined to be at 180 million processors needed to be sold. In 2007 and 2008 there were 250 million PCs shipped worldwide. This number is expected to hold steady for 2009 as well. Intel Corporation has roughly 80% of the market share which amounts to 200 million processors shipped in each of the last three years. This 52

59 trend indicates that by employing the EUVL technology Intel Corporation will definitely hit the break-even point and become profitable in the first year EUVL is implemented. Figure 27. Intel s Microprocessor EUVL Break-Even Analysis Total units shipped versus number of years. All values were extrapolated from different journals such as isuppli, SEMATECH and solid state journal in determining the break-even point [41-45]. Figure 27 illustrates the break even analysis done over a five year period. Based on our research and calculations we expect Intel to ship more processors each year. The fixed costs will start immediately after EUVL process implementation this year and the first microprocessors developed with this technology will not hit the market until next year. The number of processors shipped will start with 100 million units, indicating that Intel will slowly introduce the products made with this technology and will slowly phase out the current technology once EUVL technology has reached maturity. 53

60 4.2. A&A Independent Consulting Firm Executive Summary Faster, smaller and cheaper are the key terms used for most manufacturing industries. The semiconductor industry is especially driven by this demand, where consumers are expecting next generation device to be smaller, have more features, have more computing power, have lower energy consumption and cost less. The semiconductor industries has been able to quench this thirst for the past four decades, but are now facing challenges as the current lithography methodologies are unable to produce functional devices having millions of working transistors. As design feature increasingly become smaller the ability to print a microchip on a silicon wafer is becoming more expensive. Lithography cost is considered to be one third the total cost of manufacturing IC s and a major portion of this cost is attributed to mask cost. The analysis performed by our consulting firm will enable manufacturers to minimize cost and anticipate the best business decisions and realize a faster time to market. The analysis takes into consideration the current lithography technology at 45nm versus the next generation 32nm node and the generation after that which is the 22nm node. The calculations performed to realize the next generation lithography technology has taken the mask Cost of Ownership into account Product Summary and Business Model Mask Cost of Ownership has been a metric in determining the most cost effective next generation lithography as mask designs have been more complex and more expensive. Also mask CoO analysis are excellent and valuable way for guiding lithography technology developers. Different lithography techniques are emerging and 54

61 needs to evaluate the feasibility in business needs. A&A consulting offers mask Cost of Ownership calculation to justify a viable option for next generation lithography Product Service and Value Proposition A&A Consulting Inc. is an independent consulting firm offering consulting services to semiconductor manufacturers in the area of lithography. A&A consulting firm committed in helping our clients make substantial performance and cost saving improvements. A&A engage to reduce waste, compress cycle times and improve yields, increase productivity and lower cost of manufacturing integrated circuit Targeted Customer Currently A&A Consulting Inc., is working with Intel Corporation to help improve their lithography technology and steer the company in the direction of the next best lithography technology. The targeted customer for A&A Consulting services will be all semiconductor manufacturing companies such as Intel, IBM, AMD, DNP, Infineon, Samsung, Toshiba, TSMC, and UMC Targeted Market for the Product Costs of ownership models have different applications in the semiconductor industry. Moreover, this model can be applied in the automobile industries to determine not only the price paid per car but includes the maintenance, repair and other recurring cost. Aerospace, biotech and pharmaceutical manufacturing can use CoO to determine the cost effectiveness of a product. The main introductory concept in calculating cost effectiveness is to use a basic model and progressively improve the model, including all substantial parameters involved. 55

62 4.2.6 Personnel required A&A independent consulting firm consist of two personnel to develop CoO using advanced software and mathematical models Service Cost Summary A&A Consulting has set an initial service fee of $10,000. The company has defined the variable service cost at 40% of the fixed service cost. Table 13 shows the itemized values for service costs and fixed cost. Fixed cost is are cost that are considered as independent to the level of production while variable cost are directly related to the production that could change in the volume of output. Table13. Variable service cost and Fixed cost Table Variable service cost Service cost Fixed cost $4,000 $10,000 $14, Break-Even Analysis Break Even analysis divides cost into their fixed and variable components to estimate the production levels needed for profitable operation [51]. Unit sale price for analyzing mask CoO of next generation lithography is $20,000. A&A consulting will make a profit after the completion of the first project. Profits on succeeding months will be determined by the number of project completed. Fixed cost is business cost not directly related to output or production. Rent, depreciation, administrative, research and development cost are all included in our fixed cost. Variable cost is defined cost not directly or indirectly related to production or output. Whether direct or indirect these costs vary with output. 56

63 Table14. Variable service cost and Fixed cost Table Fixed Cost $14,000 Variable Cost $4,0000 Number of Units 1 Unit Price $20,000 Figure 28. Break Even chart of A&AA Consulting Firm The project team decidedd to charge $ 20,000 for each project acquired to compare a product or technology to be the most cost effective in order minimize cost and increase profit. 57

64 4.2.9 Profit and loss of mask Cost of Ownership analysis service Profit and loss is considered an organizational business performance metrics in which is tracked and measured on how much it makes relative to its expenses. A&A consulting will have a profit after the completion of the first project acquired and it will be self sustaining and generate income from the beginning $120,000 $100,000 Profit Chart Total revenue $80,000 $60,000 Total revenue Profit/Loss $40,000 $20,000 $0 Profit/Loss Total cost Total revenue Total cost Total cost Profit/Loss Figure 29. Profit and loss Chart of A&A consulting firm. Table 15 shows A&A consulting firm has profit on the first project. Variable cost includes the purchase of computer software s to analyze and mask CoO. Table 15. A&A consulting firm profit and loss. Year Number of projects Fees per project $20,000 $20,000 $20,000 Fixed costs $14,000 $14,000 $14,000 Variable costs $4,000 $12,000 $20,000 Total costs $18,000 $26,000 $34,000 Total revenue $20,000 $60,000 $100,000 Profit/Loss $2,000 $34,000 $66,000 58

65 Strengths, Weakness, Opportunities and Threats Analysis for A&A consulting firm. One tool used to conduct internal analysis of A&A consulting firm is called the strength and weaknesses of a firm and the environmental opportunities and threats (SWOT) the firm faces. The analysis provides a structured way to analyze internal capabilities and introduces objectivity into strategic decision making. One of the vulnerabilities of A&A consulting firm is the lack of operational capacity and efficiency in terms of member of personnel to finish a required project. Also insufficient resources in gathering information in analyzing data can be vulnerability. Mask cost of ownership could help semiconductor industries identify the parameters for cost effective lithography at 32nm and beyond, Therefore, there is tremendous opportunities for our business given the number of manufacturers and the size of industry. Table 16. A&A consulting firm SWOT analysis Strength Weakness Technology/Skills: Expert staff and resourcesoperational Efficiency: Lack of access in place to various information for the model Product and Quality: New, innovative production model/service Opportunities Threats Technology:Emerging technologies which Operational Capacity : Not enough make better and efficient modern integrated circuits personnel to complete the project ahead of time 59

66 Financial profile using Norden Rayleigh analysis Cost estimation models are categorized in linear, multiplicative, analytic, tabular and composite models. The most effective way of cost estimating is by using composite models wherein the model is generic and applicable to most situations. Composite methods mathematical parameters are simple to implement on computer software. According to Society of Cost Estimating and Analysis (SCEA, 2004), Norden Raleigh curve model is defined as the model time phasing expenditure for the development programs and is used in order to analyze and assess the cumulative and funding profile. Cumulative funding and funding profile is given in Equations 6 and where is the total effort expended, is the scale factor of the distribution and is the shape parameter. Using Equation 6 Equation 7 our three year cash flow in Table 15 and assume a, the shape parameter of 0.2 due to the less risk involved in mask CoO, we arrive Tables 17 and 18. The results are graphed and we arrive at Figure 30 which is the funding profile and Figure 31 is the cumulative funding profile. 60

67 Table 17. Norden Rayleigh calculation for year 2010 with a= 0.2 a(shape parameter) d(scale factor) Time(month) Funding Profile Cummulative Funding Table 18. Norden Rayleigh calculation for year 2011 with a= 0.2 a(shape parameter) d(scale factor) Time(month) Funding Profile Cummulative Funding Funding Profile Over Time 0 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Figure 30. Funding profile for the year 2010 &

68 Cummulative Funding Over Time Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Figure 31. Cumulative funding profile for the year 2010 & Return on Investment (ROI) Return on investment in one business metric used to determine the efficiency of an investment. ROI is calculated from the return of an investment divided by the total cost of the investment or simply the ratio of profit over loss and the result is expressed in terms of percentage. ROI of A&A consulting is shown in Table 19. The ROI for 2009 is -44.4% while for the year 2010 is expected to increase to 15.4 due to the expected increase in number of projects. Table 19. Return on investment Table Year Total Cost Total Revenue ROI 2009 $18,000 $10, % 2010 $26,000 $30, % 2011 $34,000 $50, % The advantages of calculating the ROI are to encourage business owners to have details on the relationships among sales, operating expenses and investment. Figure 32 illustrate 62

69 the ROI chart for the next three years. Increasing profits for the firm willl be achieved by reducing operating cost and increasing service feee for each project. ROI Chart $60, % $50,000 $40,000 $30,000 $30,000 $26, % $50, % $34, % 60.0% 40.0% 20.0% $20,000 $10,000 $18,000 $10, % 0.0% 20.0% 40.0% $ % Total Cost Total Revenue ROI Figure 32. Return on investment chart Exit Strategy Cost of Ownership has various implementations not only in the semiconductor industries and can be used in automotive and pharmaceutical industries. It is applicable to most manufacturing industries to determine technology. the cost effectiveness of a product or 63