Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI s Using Universal Rad-SPICE MOSFET Model

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1 J Electron Test (2017) 33:37 51 DOI /s Rdition-Induced Fult Simultion of SOI/SOS CMOS LSI s Using Universl Rd-SPICE MOSFET Model Konstntin O. Petrosynts 1,2 & Lev M. Smursky 1,2 & Igor A. Khritonov 1 & Boris G. Lvov 1 Received: 13 July 2016 /Accepted: 21 Decemer 2016 /Pulished online: 10 Jnury 2017 # Springer Science+Business Medi New York 2017 Astrct The methodology of modeling nd simultion of environmentlly induced fults in rdition hrdened SOI/SOS CMOS IC s is presented. It is relized t three levels: CMOS devices typicl nlog or digitl circuit frgments complete IC s. For this purpose, universl compct SOI/SOS MOSFET model for SPICE simultion softwre with ccount for TID, dose rte nd single event effects is developed. The model prmeters extrction procedure is descried in gret depth tking into considertion rdition effects nd peculirities of novel rdition-hrdened (RH) SOI/SOS MOS structures. Exmples of rdition-induced fult simultion in nlog nd digitl SOI/SOS CMOS LSI s re presented for different types of rdition influence. The simultion results show the difference with experimentl dt not lrger thn 10 20% for ll types of rdition. Keywords SOI CMOS circuits. Fult modeling nd simultion. Rdition hrdness. TID. Dose rte. Single Responsile Editor: L. M. Bolzni Pöhls * Konstntin O. Petrosynts kpetrosynts@hse.ru 1 2 Deprtment of Electronics Engineering, Moscow Institute of Electronics nd Mthemtics, Ntionl Reserch University Higher School of Economics, Moscow, Russi Deprtment of Anlog Circuits Design Automtion, Institute for Design Prolems in Microelectronics, Russin Acdemy of Sciences, Moscow, Russi events. Compct SPICE models. Novel RH SOI MOS structures. Model prmeter extrction 1 Introduction Silicon-on-Insultor (SOI) technology hs over mny yers generted gret interest for rdition-hrdened integrted circuits (RH IC) pplictions [4, 5, 24]. SOI circuits re tolernt to rdition-induced ltch-up nd less prone to single-event upset (SEU) phenomen, in comprison to ulk technologies. However, SOI technologies show totl-dose vulnerility since most of rdition-induced defects re ccumulted in the thick uried oxide lyers of BOX nd shllow-trench isoltion (STI). Therefore, totl-dose nd single event effects in SOI MOSFETs eing under different types of irrdition (gmm nd X-rys, neutrons, protons, hevy ions) hve een of much interest. RH IC s re fricted y modified processes nd contin CMOS trnsistors with novel structures to provide dditionl rdition tolernce, in comprison with stndrd CMOS circuits. For RH IC s so-clledbrd-hrd y Design^ (RHBD) methodology is used. Environmentlly induced filures in CMOS VLSI s re generlly cused y three types of ltertions mde in MOSFET s electricl chrcteristics: 1) threshold voltge shift nd lekge current increse due to totl ionizing dose (TID), 2) photocurrents due to dose rte, 3) trnsient currents due to single events. It ws shown tht filures in CMOS circuits could e determined nd forecsted through SPICE simultion [8]. To otin the stisfctory results of high reliility, it is necessry to ccount for rdition effects y using design flow tht spns the following levels: 1) CMOS devices; 2) typicl nlog/ digitl cells nd/or sucircuits s integrl prts of the IC under

2 38 J Electron Test (2017) 33:37 51 test; 3) complete IC. Unfortuntely, there re few pulictions [21, 25], where the prolem of interconnection etween the design levels ws discussed. The key point of the multilevel strtegy re compct SPICE SOI MOSFET models tking into ccount TID, dose rte nd single event effects. Severl compct rd-spice MOSFET models were developed in the lst yers [1, 2, 6, 8, 9, 11, 15, 16, 18, 22, 23, 26 28]. In [28] compct model TDESim for sumicron devices ws proposed to ccount for rditioninduced sidewll sttic lekge currents in Bird s ek^ LOCOS corners. Pper [1] introduced compct model with ccount for single events nd totl dose effects on threshold voltge nd moility. The model does not ccount for uried oxide rdition-induced effects nd the rising lekge currents. Pper [2] presented mcromodel with simple polynomil-sed ccount for threshold voltge, moility, nd sidewll lekge currents with vrying ody contct voltge. Article [23] detils physics-sed compct model with ccount for TID nd ging effects in devices sed on surfce potentil clcultions. The models for SET simultion were proposed in [1, 26, 27]. In [1] the physicl-sed model for trnsient current generted y n ionized prticle in the MOSFET structure ws developed nd then included in the SPICE simultor s Verilog-A module. On the contrry, in [27] simple model descried the ehvior of the ionizing prticle strike phenomenon t the logic level ws proposed. In [9] more ccurte compct model for SEU simultion including deposited chrge recomintion nd chrge decresing y trnsistor current ws proposed. However, in this model the mjor prmeter (current gin) of prsitic ipolr trnsistor influence on the induced current ws not written in detil. Articles [15, 16, 18, 22] present SOI/SOS-MIEM nd BSIMSOI-RAD compct models for SOI/SOS MOSFETs with ccount for vrious rdition effects, however prmeter extrction procedure ws not developed sufficiently. SPICE modeling of pulsed ionizing rdition influence ws ddressed in [6, 11]. The model [11] ccounts for the difference in drin nd source photocurrents, forwrd ising of drin junction. [6] presents method to chrcterize ipolr mplifiction. However, summrizing the results presented in these works, we re forced to consider tht the model prmeters extrction procedure ws not crried out completely, especilly for novel rd-hrd SOI CMOS trnsistor structures. This fct cretes numerous prolems for RH CMOS IC s design. In the presented work, uthors hve solved this prolem. The most dvnced for tody compct SPICE model for rd-hrd SOI MOSFETs tking into ccount TID, dose rte, nd single event effects [19] ws considered. The conventionl methodology of model prmeters extrction understndle for device nd circuit designers ws proposed. Then the universl rd-spice MOSFET model ws used in consecutive order for fult simultion t three levels: CMOS devices typicl prtil nlog or digitl sucircuits complete IC. The exmples of fult simultion of nlog nd digitl RH SOI/ SOS CMOS circuits demonstrte the efficiency of using the proposed universl model in rd-hrd IC design strtegy. 2 Rd-Hrd Device Structures In ddition to conventionl SOI MOSFET s with two-edged liner lyout (see Fig. 1) the rdition-hrd SOI MOS trnsistors: e. g. with nnulr gte (or enclosed lyout type, ELT, Fig. 1), H-type gte (Fig. 1c), ringed source (Fig. 1d) nd doule ody tied to source structure (DBTS) (Fig. 1e) re essentilly needed oth in digitl nd nlog design to exclude or suppress the rdition-induced effects of trpped oxide chrge nd excess chrge collection to enhnce the device rdition hrdness. In these structures, lterl rditioninduced lekge currents re effectively suppressed or their ctive silicon res hve no lterl sides t ll [3, 12, 14]. Figures 2 nd 3 exhiit the difference in IV-chrcteristics of rd-hrd nd non-rd-hrd SOI MOSFET s. Figure 2 presents comprison of mesured I D -V G curves with ccount for totl doses (300 krd nd 1.5 Mrd) induced y X-rys for two types of SOI MOSFET structures with W / L = 2/ 0.35 μm: conventionl two-edged (full symols) nd H-type gte (open symols). TID-induced effects re oserved on the drin current curves: while the front chnnel threshold voltge shift is lmost negligile in the 0.35 μm technology node nd the ottom lekge finds itself in oth structure types, the conventionl two-edged structure experiences lterl lekge (mnifested s n dditionl hump on the curves) tht is sent in the H-type gte structure, in which the gte shpe prevents inversion under the gte polysilicon overlpping the field oxide nd thus suppresses lekge current. Figure 3 presents comprison of mesured I D -V G curves with ccount for totl doses ( krd) induced y gmm-rys Co 60 for conventionl nd DBTS MOSFET structures with L = 0.5 μm. In this cse, source/drin implnts re rought to the uried oxide (BOX) interfce. To connect the ody node to the ssocited source node, ody-tied-to-source strps re used. For n- chnnel MOSFET, the ody tie is p + source-drin diffusion tht contcts the p + ody region. So the p + BTS diffusion overlps the prsitic lekge chnnel for drin current (see Fig. 1e). Additionl detils on TID edge effects in SOI MOSFET s with different lyouts cn e found in [12]. Two versions of MOSFET structures (Fig. 1 e) re used in prcticl IC design: without ody contct (floting ody) nd with contct to ody. Using the MOSFET s with contct to ody, on one hnd, results in the increse of the device re, ut, on the other hnd, in improvement of rdition hrdness to TID nd SE (see Fig. 21).

3 J Electron Test (2017) 33: Fig. 1 Lyouts for conventionl () nd rdition hrdened MOSFET structures: with nnulr gte (), H-type gte (c), ringed source (d) nd doule ody-tiedto-source (DBTS) (e) c d e Conventionl two-edged type Annulr gte type H-gte type Ringed-source type doule ody-tiedto-source 3 Rd-Hrd SPICE SOI MOSFET Mcromodel The lst version of the most dvnced compct SPICE model for SOI MOSFET with ccount for totl ionizing dose induced effects (TID), pulsed rdition effects nd single events is presented in Fig. 4 [19]. The equivlent circuit of the model consists of two prts: 1) Core model sed on stndrd BSIMSOI [17] or EKV-SOI [18] pltforms for sumicron min trnsistor M front (front Si SiO 2 interfce) with prmeters dependent on TID. The type of model pltform is selected y designer. 2) Additionl sucircuits tking into ccount rditioninduced effects. Prsitic ipolr horizontl trnsistor Q lt is uilt into the ctive MOSFET structure nd mplifies TIDnd SE-induced component of drin current. Prsitic trnsistors M otm nd M side re used for the ckgte nd sidewll lekge currents in MOSFET structure (see Fig. 5). Model prmeters of the min M front nd prsitic trnsistors M side nd M otm stnding for threshold voltge V T, moility μ eff nd suthreshold slope S re rdition-dependent nd re descried with mthemticl equtions. Current sources I PSI, I PDI represent the currents induced y pulsed irrdition; current source I SET represents the current induced y ion strike; I lsph nd R sph represent stedy-stte rdition-induced lekge current long the insulting spphire sustrte nd susurfce trnsient ionizing rdition-induced lekge current, correspondingly, for the cse of SOS MOSFETs. 3.1 Totl-Dose Effects In BSIMSOI, rdition-dependent prmeters re prmeters for threshold voltge (VTH0 with fctors K1, K2 etc.), moility (U0 with fctors UA, UB etc.), nd suthreshold slope (CIT nd VOFF); in EKV-SOI, these re VTO, GAMMA, KP, nd E0; in prsitic trnsistors: VTO, THETA, UO, NFS. The dependence of the nmed prmeters on totl dose D is expressed in the following wy: & Asolute shift of prmeters VTH0, VTO nd fctors K1, K2, THETA etc., prmeters VOFF, GAMMA: VTH0(D) VTH0(0) etc. is given in the form with sturtion plteu for high doses: P i ðdþ P i ð0þ ¼ 1i ð1 exp ½ 2i D Þ; wherep i VTH0; VTO; K1; K2 ð1þ or in the form of polynomil. Fig. 2 Mesured front chnnel I D -V G curves with ccount for TID induced y X-rys for 0.35 μm SOI MOSFET s with different lyouts: conventionl two-edged (open symols nd stright lines) nd H-type gte (full symols nd dshed line) Fig. 3 Mesured front chnnel I D -V G curves with ccount for TID induced y gmm-rys Co 60 in 0.5 μm SOI MOSFET s with conventionl two-edged (open symols)

4 40 J Electron Test (2017) 33:37 51 I SET (t) I SET (t) Drin Gte Body I SET (t)=k I SET / (t) Source Drin I prtic (t) C I rec (t) I SET /(t) Body Source Gte Fig. 6 SPICE-modeling of SET in SOI MOSFET: ) simple model with doule-exponentil current source (), improved model () with sucircuit connected to MOSFET R In (1) nd(2) 1i, 2i, 1j, 2j re fitting fctors relted to ioniztion dose nd electricl is during irrdition. Fitting fctors in these expressions constitute the set of sttic rdition prmeters of the mcromodel. Fig. 4 Equivlent circuits of the BSIMSOI-RAD nd EKV-RAD mcromodels for SOI/SOS MOSFET: core front MOSFET M front with rdition dependent prmeters; sucircuit for rditioninduced sttic nd dynmic lekge currents & Reltive shift of prmeters U0, UO, E0 nd fctors UA, UB, KP etc., prmeters CIT, NFS: [U0(D) U0(0)] / U0(0), etc. is given in the similr form: P j ðdþ P j ð0þ =P j ð0þ ¼ 1 j 1 exp 2 j D ; wherep j U0; UO; E0 ð2þ 3.2 Single Events Two models were used for single event trnsients modeling: trditionl simple version with doule-exponentil current source (Fig. 6) nd the improved version with connected sucircuits (Fig. 6). The improved modeling pproch for single event trnsient (SET) is sed on [9]. In Fig. 6 current source I prtic is descried s the sic time-current profile of the trnsient prticle -induced current, e. g. doule exponent. It represents the time-current profile for depositing the trck chrge to the SOI MOSFET structure. The integrted vlue of this source is the totl mount of chrge deposited in the device structure. The Fig. 5 Loction of prsitic chnnels for lekge currents in SOI MOSFET structure: sidewll (LOCOS) () nd ck (BOX) () chnnels

5 J Electron Test (2017) 33: cpcitor C does not represent physicl cpcitnce nd it is used to ensure chrge conservtion; its voltge is proportionl to the chrge tht hs een induced y ion (I prtic ). But for prcticl pplictions the vlue of the cpcitnce cn e estimted s the sum of ll prsitic cpcitnces lumped t the node, including interconnect, drin junction nd cpcitive loding to the logic gtes driven y the struck node [7]. The dependent current source I rec is the recomintion current. Its vlue is relted to the minority crrier lifetimes in the device. The comintion of two Bmirroring^ current sources I SET nd I SET / is used to exclude, on the one hnd, undesired influences of MOSFET drin current onto trck chrge relxtion process nd, on the other hnd, chrge recomintion current onto MOSFET drin current. The externl current source I SET / depends on voltge cross C nd is not directly connected to the trnsistor to isolte the clcultion portion of the model from trnsistor ehvior influence. The internl current source I SET represents the rdition-induced current t the drin p-njunction nd it is proportionl to the I SET / y the prsitic ipolr trnsistor mplifiction fctor k(x). The ipolr mplifiction fctor (BAF k(x)) is function of ion strike loction long the source/drin xis in Fig. 7. The results of TCAD simultion re presented for ipolr gin (BAF) (see Fig. 7). The strikes on the ion with LET = 21 MeV cm 2 /mg perpendiculr to the surfce of 0.25 μm SOI MOSFET structure were modeled. The points of ion strikes re mrked on the device lyout in Fig. 7. Itisseenthtthe ipolr gin reches its mximum vlue (of 2.5) when the ion strikes occur in the most sensitive res (i. e. the ody region close to the drin junction) (see point 5 in Fig. 7). Our results re in good greement with experimentl dt presented in [7]. Note tht ipolr junction trnsistor (BJT) presented in Fig. 6 is included in the stndrd version of BSIMSOI model. But if EKV-SOI model is used, the BJT must e connected to the equivlent circuit (Fig. 6) s n externl component. 3.3 Dose Rte Effects Fig μm SOI MOSFET lyout with the indiction of ion strike points () nd TCAD simulted prsitic BJT current gin () Dose rte modeling follows the pproch of [11]withcurrent sources I PDI, I PSI (see Fig. 8), diode to ccount for forwrd ising the drin junction, nd prsitic BJT. Given tht the nlyzed MOFETs re situted on the insulting sustrte nd hve thin ctive lyer, trnsient photocurrents include only the prompt components nd re descried y the well-known equtions [13]: I PDI ¼ qg 0 γðþ V t col ðv DS Þ ð3þ where q is the elementry chrge; g 0 is the genertion rte in silicon = (electron-hole pirs rd -1 cm -3 ); γ(t) is the dose rte (rd(si)/s); V col (V DS ) is the function descriing the effective collection volume (cm 3 ) which is drin voltge V DS dependent. Moreover, R sph resistor ccounts for spphire conductnce during trnsient ionizing rdition pulse:. R sph ðþ¼k t sph L ðwdγðþ t Þ ð4þ where K sph = (Ohm cm rd/s); LndWre trnsistor gte length nd width; d is thickness of conductive region of spphire under trnsistor. 4 Mcromodel Prmeter Mesurement nd Extrction Strtegy 4.1 Modified Procedure for MOSFET Chrcteristic Mesurement Fig. 8 SPICE-modeling of dose rte effects: ) rdition pulse exemplry shpe, ) sucircuit connected to MOSFET The modified electricl mesurement procedure [20] is formed on top of the stndrd one tht is lunched severl

6 42 J Electron Test (2017) 33:37 51 c d Fig. 9 Simulted (lines) nd mesured [10] (symols) SOI MOSFET trnsfer IV-curves (W/L =8/0.25μm) times during the whole process. The modifiction is necessry to seprtely chrcterize the prsitic components of the mcromodel tht replces stndrd SPICE model to ccount for rdition-induced lekge currents. Irrdited MOSFETs electricl chrcteristics dt my come from rel test structures mesurements, or from device simultion with TCAD ([20] presents the corresponding dtflow within the specilized hrdwre-softwre system). The prmeter extrction procedure is utomted with industry extrction tool IC-CAP, which simplifies dt exchnge nd processing nd lowers the humn error proility. The input dt re the sets of I-V nd C-V curves of the stndrd SOI/SOS MOSFET structures t different vlues of totl dose. These sets re trnsferred to IC-CAP using n inhouse progrm interfce. V.u. The Stndrd Procedure In the course of the stndrd mesurement procedure, numer of stndrd electricl chrcteristic curves of numer of length- nd width-vried MOSFET devices under test re mesured under the control of IC-CAP nd processed therein: BId-Vg^ nd BId-Vd^ curves t vrious ody voltges V B ; input nd output curves for prsitic ipolr trnsistor The Modified Procedure with n Account for Totl Ionizing Dose 1) The unirrdited front MOSFET model is fully mesured with the stndrd procedure, with prsitic MOSFETs eing switched off. 2) A shortened (minimum, see elow) set of electricl curves is mesured on the devices under test fter ech of the scheduled rdition exposure levels the device hs undergone. All the three interfces (front, ottom, nd sidewll) re ctivted sequentilly with the help of specil test structures, so tht the rdition-induced lekge currents re seprted: Fig. 10 Model prmeters dependencies on dose for the min M front trnsistor: ΔVOFF (), U0(D)/U0(0) (), ΔVTH0 (c) c & & A specil rd-hrd MOSFET structure (with nnulr gte, H-type gte or ringed source) with lmost no lterl lekge, is used for seprte mesurement of I-V curves of the front MOSFET for different vlues of totl dose t voltge V G < 0 on the ck gte, which excludes the effect of M otm. The sme structure type is used for seprte mesurement of I-V curves of the ottom prsitic MOSFET for severl vlues of totl dose t voltge V Gf < 0 on the front gte, which excludes the effect of M front.

7 J Electron Test (2017) 33: Fig. 11 Memory cell write unit circuit digrm s prt of the SRAM lock rchitecture & A conventionl two-edged structure with oth ottom nd lterl lekge is used for seprte mesurement of I-V curves of the lterl prsitic MOSFET s t voltge V G < 0 on the ck gte to exclude the effect of M otm. Fig. 12 Memory cell write unit trnsient response simulted in the rnge of rdition dose vlues up to 150 krd

8 44 J Electron Test (2017) 33:37 51 Fig. 13 Simulted (lines) nd mesured (circles) voltge trnsfer nd supply current chrcteristics for SOS CMOS inverter with L = 3 μm, t Si =0.6μm For every single dose level, shortened set of electricl curves is mesured for the front, sidewll, nd ottom MOSFETs: BId-Vg^ nd BId-Vd^ curves t few drin voltges nd fixed ody voltge. In our experiments, we used 5 10 steps of dose increse within the required totl dose rnge. The initil dose steps were smll enough to register initil MOSFET chrcteristics degrdtion, nd in the lst steps dose increses were lrger ecuse of MOSFET chrcteristics sturtion t lrge doses. To void detrimentl selfnneling processes during mesurement, time intervls etween irrdition steps were fixed shortest possile, or lterntively, mesurements were done without interruption of irrdition. time, ns time, ns Fig. 14 Timing prmeters with ccount for TID effects for SOS CMOS NAND2 logic gte () nd FDC flip-flop () with L =3μm, t Si =0.6μm: mesured (symols) vs. simulted (lines) Automtion of MOSFET Curve Mesurement Automtion of curve mesurement nd dt processing is highly desirle to reduce time of opertion nd humn error. A mesurement dt cquisition nd formtting suite ws developed y tying up of IC-CAP nd LView tools with instrumenttion. All the curve mesurements of single trnsistor re crried out without re-connection of the device under test, which further reduces risks of humn error nd device dmge. 4.2 Strtegy for SPICE Model Rdition Prmeter Extrction At the mesurement stge, set of chrcteristic curves is mesured for every component of the mcromodel. It is therefore possile to identify the model for ech component seprtely, nd then comine the resulting models into single mcromodel crd. Mcromodel prmeter extrction procedure with ccount for totl dose effects is ccomplished with the help of modified workflow [17, 22] sed on test structures mesurement. Modifiction of the extrction procedure is necessry given tht for the irrdited devices: 1) mesurement results dtse significntly grows in size nd vries in structure; 2) the set of test structures enlrges; 3) quntity of model prmeters increses; 4) the extrction procedure incorportes new step of pproximtion of experimentl dependencies of model prmeters on dose to known physicl function. The following strtegy is developed: 1) The full set of mcromodel prmeters is t first extrcted for the unirrdited device. The stndrd extrction flow inside IC-CAP sequentilly invokes mesurement dt to identify the whole set of device model prmeters group y group. 2) Among ll the model prmeters for MOSFET sucomponents limited numer of rdition-dependent prmeters is selected: threshold voltge, moility, suthreshold slope nd their fctors (depending on the selected models). 3) For ech rdition dose D i IC-CAP is used for extrction of the set of model prmeters for V T (D i ), μ(d i ), S(D i ). This procedure is repeted for ll the doses D i : i =1,n. 4) The tle functions for V T (D i ), μ(d i ), S(D i ) re pproximted with nlyticl functions of the type: 1 (1 exp[ 2 D]). 5) The determined functions re emedded into the MOSFET SPICE mcromodel crd tht is further included into the SPICE model lirry. Automtion of the prmeter extrction procedure with IC- CAP simplifies dt exchnge nd processing nd lowers the humn error proility.

9 J Electron Test (2017) 33: Fig it SOS CMOS reversile counter: symol (), simulted trnsients for the cse efore irrdition (), fter irrdition with dose 300 krd (c) (no filure) nd 400 krd (d) (filure) c d Durtion of the prmeter extrction procedure on the exmple of set of 16 test trnsistors with different W/Lsizes nd 6 doses of rdition for the cse of BSIMSOI-RAD estimtes to 166 minutes, while for EKV-RAD this figure is 123 minutes. The extrction strtegy is illustrted on the exmple of SOI MOSFET with gte dimensions W/L = 8/0.25 μm. Seprte experimentl chrcteristic curves for the min trnsistor M front (Fig. 9) nd prsitic ottom (Fig. 9d), sidewll (Fig. 9c) trnsistors were otined [10]. The totl SOI MOSFET current (Fig. 9) is the Kirchhoff sum of prtil currents (Fig. 9,c,d). The set of mcromodel prmeters ws determined y mens of the descried extrction strtegy. The dependencies of prmeters on dose D were pproximted with nlyticl functions of type 1 (1 exp[ 2 D]) (see Fig. 10). The error etween mesured nd simulted I-Vchrcteristics is 10 15%. f, Hz Fig. 16 Opertionl mplifier A v frequency response: simultion (solid lines), experiment (points) Comprison of Time Expenses for Circuit Simultion Severl computer experiments were performed to estimte time expenditures for simultion of SOI/SOS circuits of vrious type nd complexity (see Tle 1). The tests were: ) IV curves (10,000 points) of -single SOS MOSFET, ) the ginfrequency curve (800 points) of SOS CMOS opertionl mplifier (contining 45 SOS MOSFETs), c) trnsient process (1800 points) in digitl SOS CMOS 4-it counter circuit (contining 250 SOS MOSFETs). The electricl schemtics of SOS CMOS opmp nd 4-it counter re presented in [19]. Two vrints of either mcromodel were used for ody-tied prtilly-depleted trnsistors: ) core EKV-SOI/ BSIMSOI model; ) EKV-RAD/ BSIMSOI-RAD mcromodel. The lst vrint ws simulted with the ccount for 1 Mrd totl dose. Vlues of Btotl CPU time^ (provided y the simultor progrm) for popultion of 10 redings were recorded for every test nd then verged. A computer with Intel i M 2.4 GHz, 4 GB RAM ws used; the simultor ws HSpice A The presented dt suggest tht models with ccount for rdition effects provide reltively longer circuit simultion time: from 10 to 35% for BSIMSOI-RAD (depending on circuit type) nd from 10 to 100% for EKV-RAD (depending on circuit type). This fct is resonly explined y compliction of the equivlent circuits (3 trnsistors insted of 1 in the stndrd models; dditionl circuit components) nd introduction of dditionl nlyticl functions descriing rditiondependent prmeters.

10 46 J Electron Test (2017) 33:37 51 Fig. 17 SOI CMOS Bril-to-ril^ comprtor with differentil outputs (49 MOSFETs, L = 0.5 μm): symol (), simulted trnsient response efore irrdition (), fter 500krd (c) (no filure), fter 1 Mrd (d) (filure); in ll cses commonmode input voltge V cm =4V c d 5 Fult Simultion in RH SOI/SOS CMOS Circuits for Spce Electronics Vlidtion of the proposed model s cpility to predict circuit filure if fced with vrious rdition effects is demonstrted on the exmples of set of specilized digitl nd nlog circuits. It is difficult prolem to find the source of the rditioninduced fult in complete IC, nd then determine its reson. The effective wy to simplify the solution of this prolem is using of the three-level strtegy of fult detection: complete IC typicl circuit frgments CMOS devices/mosfet s. The IC s electricl schemtic is divided into set of not complicted typicl circuit frgments or sucircuits. Then rdition sensitivity of ech sucircuit cn e nlyzed y SPICE simultion using the developed models descried ove. As result, the Bpoor^ device or prt of circuit cn e discovered nd improved if it is possile. 5.1 Totl-Dose Effects TID cuses the threshold voltge shift nd lekge current increse in SOI/SOS MOSFET s. Both effects hve significnt impct upon nlog nd digitl circuit opertion. Digitl Circuits For exmple, in Fig. 11 the electricl schemtic of 512-kit SRAM with clock frequency 16 MHz produced in 0.5 μm SOI CMOS technology (chip size is 10x9.7 mm 2 ) is presented. The typicl I-V-chrcteristics of Fig. 18 6T CMOS memory cell schemtic representtion for circuit fult simultion Fig. 19 Mixed-mode SPICE-TCAD simultion vs. SPICE-only simultion (simple nd improved model) of SET in 6T CMOS memory cell (Fig. 18)

11 J Electron Test (2017) 33: Fig. 20 Fult simultion of SEU in 6T CMOS memory cell (Fig. 18) with different vlues of liner energy trnsfer (LET): opertion succeeded (), opertion filed () gmm-rys-irrdited 0.5 μm SOI MOSFET s re given in Fig. 3. To exmine the rdition hrdness of the SRAM chip fter gmm-rys irrdition, the descried ove methodology ws pplied. It ws found tht the poorest element ws the write unit circuit in the control signl lock (indicted y dshed line in Fig. 11). The trnsient response for this element simulted with rd-spice MOSFET models, pre-clirted in the rnge of rdition doses up to 1600 krd, is presented in Fig. 12. It is seen tht the criticl rdition dose level fter which the filure occurs, is out krd. The circuitry of this poor element ws improved, nd fter tht, SRAM circuit (Fig. 11) demonstrted filure-less ehvior in the rnge of 300 krd. These results for the initil nd improved SRAM versions were confirmed y experimentl dt. Silicon-on-spphire CMOS technology is trditionlly used for rdition hrdened IC s nd VLSI s friction.the Rd-SPICE MOSFET models were developed y the uthors for different genertions of SOS CMOS technology with nodes from 3.0 μm to 0.5 μm. In Fig. 13 mesured nd simulted voltge trnsfer nd supply current chrcteristics re shown for SOS CMOS inverter. It ws found tht for totl dose greter thn 1 Mrd the filure occurs. Figure 14 depicts simulted nd mesured dely time vlues for n SOS CMOS NAND2 gte nd FDC flip-flop (48 MOSFET s). For these circuits the mximl dely time is estlished s 50 ns, so the mximl llowed totl dose is out 450 krd. Bsed on the set of logic gtes nd flip-flops (Figs. 13 nd 14) nd other digitl elements, the IC chip of 4- it reversile counter ws produced in 3.0 μm SOS CMOS technology (the electricl schemtic consists of 250 MOSFET s nd ws presented in [19]). The results of rdition hrdness simultion with SPICE for the counter IC chip fter gmm rys irrdition with different TID s re presented in Fig. 15. It is seen tht the criticl totl dose is out 300 krd. The simulted results re in good greement with mesured dt. The IC chip stisfies the electricl nd reliility requirements. Anlog Circuits For exmple, Fig. 16 presents mesured nd simulted t vrious vlues of totl dose frequency response for SOI CMOS opertionl mplifier (opmp) (35 MOSFETs) fricted in XFAB 1 μm technology. The compct SPICE models of 1 μm SOI MOSFET s tkingintoccount TID effects were developed [18]. Anlyzing the results of opmp circuit SPICE simultion, it ws indicted tht opmp performnce ws degrded y TID effects, especilly when the rdition dose ws lrger thn 250 krd. The DC gin degrdtion ws significntly lrge with loss of 50%. In the next exmple (Fig. 17) the rdition hrdness of SOI CMOS ril-to-ril comprtor is investigted fter gmmrys irrdition. The comprtor ws uilt of ril-to-ril opmp circuitry with locl feedck to improve the dynmic chrcteristics. It consists of μm SOI MOSFET s with I-V-chrcteristics presented in Fig. 3. The compct SPICE SOI MOSFET model ws developed tking into ccount TID effects. The trnsient responses of the comprtor circuit were simulted for different doses (in ll cses common-mode input voltge V cm = 4 Vnd differentil input voltge V diff = 0.5 mv). It is seen in Fig. 17,c tht the comprtor keeps the cpility of stle work up to 500 krds. This fct ws confirmed y experimentl dt. In the presented exmples, mesurement nd simultion were done y the uthors; the simultion error is 10 15% for sttic nd 15 20% for dynmic chrcteristics. Mesurement dt were otined from Co krd/h source. 5.2 Single Events Fig. 21 Simultion of SET-induced fults in 6T CMOS memory cell (Fig. 18) with() nd without () ody contct in trnsistor structure: opertion succeeded (), opertion filed () Firstly, the vlidtion of the SPICE SET model presented in item 3.2 is discussed. For this purpose, the results of two vrints of SPICE simultion (idel doule exponentil current source nd the proposed model) were compred with mixed-mode TCAD-SPICE simultion results. Figure 19 shows simultion results for drin voltge nd drin current

12 48 J Electron Test (2017) 33:37 51 Tle 1 Totl simultion time for CMOS circuits (in seconds) Model vrint BSIMSOI EKV- SOI BSIMSOI- RAD EKV-RAD Dose, rd Sttic IV curves (Single MOSFET, points) Opertionl mplifier frequency response ( MOSFET's, 800 points) 4-it counter trnsient (250 MOSFET's, 1800 points) of the MPA trnsistor in cell Fig. 18 fter ion impct into the order etween gte nd drin regions. It is seen tht the simultion results of the simpler doule exponentil model (Fig. 6) grossly overestimte current nd voltge spikes in the impcted MOSFET tht re cused y prsitic ipolr mplifiction. The error is more thn 20%. The proposed improved model with connected sucircuit (Fig. 6) provides the results which re very close to the reference TCAD-SPICE simultion results. Secondly we conducted SPICE circuit simultion with the improved model (Fig. 6) for the cse of single event trnsients (SET) fter n ion strike on 6T CMOS memory cell (Fig. 18). MOSFET structure prmeters were the following: W/L = 1.4/0.5 μm, uried oxide thickness 150 nm, ctive Si lyer thickness 190 nm, gte oxide thickness 11.5 nm; in Fig. 3 the typicl I-V-chrcteristics re given. Figure 20 presents trnsient chrcteristics of the cell modeled for ion with different vlues of liner energy trnsfer (LET). It is seen tht opertion filed when ions hd LET lrger thn 20 MeV cm 2 / mg. Thirdly, we investigted the effect of MOSFET ody contct presence on filure level of the sme cell. Trnsient chrcteristics were modeled for ion with LET =21 MeV cm 2 /mg (equivlent to Fe ion with 16 MeV energy), which impcts the trnsistor lyout t n ngle of 30 degrees to the surfce. Figure 21 presents trnsient chrcteristics of the cell modeled with two lyout versions of MOSFET s: with nd without specil contct to trnsistor ody. I D curve shows the impcted MOSFET (MPA) drin current; the moment of its pulse onset is the time of prticle impct. In the cse where there is no ody contct, the circuit fils oth nodes A nd B chnge their sttes, while in the cse where the ody contct is present, the circuit successfully opertes nodes A nd B only experience glitches, ut eventully return to the initil sttes. So, the dditionl contct to trnsistor ody increses rdition hrdness. 5.3 Dose Rte Effects The vlidtion of the dose rte model presented in Fig. 8 ws crried out on two exmples of photocurrent simultion: for single SOS CMOS inverter fricted in 2 μm SOS technology (in-house mesurements) nd for rry of SOI MOSFET s fricted in Honeywell 0.15 μm SOI technology [11]. Figure 22 shows tht SOS CMOS devices with thinner Silicon lyer t Si = 0.3 μm hve smller effective collection volume V col (see (3)) nd s result, they re more resistnt to pulse irrdition. However, the pulse with dose rte rd/s does not cuse filure in n SOS CMOS inverter with two vlues of Silicon lyer thickness of 0.6 nd 0.3 μm. Figure 23 presents rdition-induced lekge currents dt per single trnsistor for n rry of 80,000 n-chnnel SOI MOSFETs with W/L = 0.4/0.15 μm. The rdition pulse hd oth rising nd flling edges of 10 ns nd width of 13 ns with vrying dose rte. Negligile prsitic ipolr effect ws found. The simultion results re in good greement with experimentl dt [11]. For the digitl IC chip of 4-it reversile counter (Fig. 15) the rection on rdition dose rte influence ws investigted using SPICE circuit simultion. The counter IC ws fricted in SOS CMOS technology (250 MOSFET s with L =2μm, t Si =0.3μm). The Fig. 22 Simultion of output voltge trnsients fter pulsed irrdition for SOS CMOS inverter with L =2μm, t Si = 0.3 nd 0.6 μm Fig. 23 Mesured (squres) [11] nd simulted (lines) pulsed irrdition induced SOI MOSFET photo current per one trnsistor

13 J Electron Test (2017) 33: Y Y Fig it SOS CMOS reversile counter: simulted trnsients for the cses fter irrdition pulse with dose rte rd/s () (no filure) nd rd/s () (filure); in oth cses n rrow indictes the time point of the pulse onset digitl circuit consists of inverters (see Fig. 22), logic gtes nd flip-flops. The timing digrms for the 4-it counter IC re presented in Fig. 24). It is seen tht the criticl dose rte vlue which provides filure-less circuit ehvior, is rd/s (Si). The simulted results re confirmed y experimentl results in Fig. 25, where supply current trnsients generted y dose rte pulse re shown. It is seen tht for low dose rte 10 7 rd/s, the current pek vlues re not criticl, ut for high vlues more thn 10 9 rd/s they exceed the limit of 2 ma, fter which the filures occur. 6 Conclusion Modeling nd simultion of rdition-induced fults in SOI/ SOS CMOS LSI s using RAD-SPICE compct model for SOI/SOS MOSFET s is n effective design technique for improving IC rdition hrdness, cutting down the numer of expensive friction runs. The effective wy to simplify the solution of this prolem is using of the multi-level strtegy of fult detection. The IC s electricl schemtic is divided into set of not complicted typicl circuit frgments or sucircuits. Then rdition sensitivity of ech sucircuit cn e nlyzed y SPICE simultion using the developed MOSFET models. As result, the Bpoor^ device or prt of circuit cn e discovered nd improved if it is possile. For this purpose the dvnced universl compct SOI/SOS MOSFET model tking into ccount TID, dose rte, single event effects nd peculirities of novel rd-hrd SOI/SOS MOS structures ws developed nd implemented in commercil circuit simultors HSpice, Spectre, Eldo nd others nd extensively pplied to fult simultion of rd-hrd nlog, digitl, nd mixed-signl rd-hrd SOI/SOS CMOS IC s. The conventionl methodology of model prmeters extrction from experimentl dt understndle for device nd circuit designers ws proposed. Modeling error of 10 15% for sttic nd 15 20% for dynmic chrcteristics of SOI/ SOS MOSFET s ws chieved using the developed SPICE prmeter extrction procedure. The exmples of rdition induced prmeter degrdtion nd fult simultion of nlog nd digitl rd-hrd SOI/SOS CMOS IC s demonstrte the efficiency of using RH BD strtegy. Acknowledgments This work ws supported in prt y the Acdemic Fund Progrm t the Ntionl Reserch University Higher School of Economics in 2015, grnt No , nd Russin Foundtion for Bsic Reserch, grnt No References Fig. 25 Oscilloscope pictures of 4-it counter SOS CMOS IC supply currents fter rdition pulse influence with different dose rtes 1. Alvrdo J, Boufouss E, Kilchytsk V, Flndre D (2010) Compct model for single event trnsients nd totl dose effects t high tempertures for prtilly depleted SOI MOSFETs. Microelectron Reli 50:

14 50 J Electron Test (2017) 33: Bu J, Bi J, Liu M, Hn Z (2011) A totl dose rdition model for deep sumicron PDSOI NMOS. J Semi 32(1): Cristolovenu S, Li S (1995). Electricl chrcteriztion of siliconon-insultor mterils nd devices (Vol. 305). Springer Science & Business Medi 4. Dodd PE, Shneyfelt MR, Schwnk JR, Felix JA (2010) Current nd future chllenges in rdition effects on CMOS electronics. IEEE T Nucl Sci 57(4): Fruk MG, Wilkins R, Dwivedi RC, Klri D, Ptel M, Binzid S, Atti JO (2012) Proton nd neutron rdition effects studies of MOSFET trnsistors for potentil deep-spce mission pplictions. Aerosp Conf Proc: Ferlet-Cvrois V, Mrcndell C, Girud G, Gsiot G, Colldnt I, Musseu O, Fenouillet C, du Port de Ponchrr J (2002) Chrcteriztion of the prsitic ipolr mplifiction in SOI technologies sumitted to trnsient irrdition. IEEE T Nucl Sci 49(3): Ferlet-Cvrois V, Pillet P, Gillrdin M, Lmert D, Bggio J, Schwnk JR, Fynot O (2006) Sttisticl nlysis of the chrge collected in SOI nd ulk devices under hevy lon nd proton irrdition Implictions for digitl SETs. IEEE T Nucl Sci 53(6): Hung X, Frncis AM, Lostetter AB, Mntooth HA (2004) Compct modeling of environmentlly induced rdition effects on electricl devices. Aerosp Conf Proc 4: Kuppil JS, Sternerg AL, Alles ML et l (2009) A isdependent single-event compct model implemented into BSIM4 nd 90 nm CMOS Process Design Kit. IEEE T Nucl Sci 56(6): Li Y, Niu G, Cressler JD, Ptel J, Mrshll CJ, Mrshll PW, Plmer MJ (2001) Anomlous rdition effects in fully depleted SOI MOSFETs fricted on SIMOX. IEEE T Nucl Sci 48(6): Liu HY, Golke KW, Liu ST (2015) A new dose rte model for SOI MOSFET nd its implementtion in SPICE. IEEE Int SOI Conf: Liu J, Zhou J, Luo H, Kong X, En Y, Shi Q, He Y (2010) Totldose-induced edge effect in SOI NMOS trnsistors with different lyouts. Microelectron Reli 50(1): Mssengill LW, Diehl-Ngle SE (1984) Trnsient rdition upset simultions of CMOS memory circuits. IEEE T Nucl Sci NS-31: Nowlin N, Biley J, Turfler B, Alexnder D (2004) A totl-dose hrdening-y-design pproch for high-speed mixed-signl CMOS integrted circuits. Int J High Speed Electron 14(2): Petrosjnc KO, Adonin AS, Khritonov IA, Sichev MV (1994) SOI device prmeter investigtion nd extrction for VLSI rdition hrdness modeling with SPICE. Proc IEEE Intl Conf Microelectron Test Struct 7: Petrosjnc KO, Khritonov IA (1993) VLSI device prmeters extrction for rdition hrdness modeling with SPICE. Proc IEEE Int Conf Microelectron Test Struct: Petrosynts KO, Khritonov IA, Orekhov EV, Smursky LM, Ytmnov AP (2009) Simultion of Rdition Effects in SOI CMOS Circuits with BSIMSOI-RAD mcromodel. Proc 7th IEEE Est-West Design Test Int Symp (EWDTS) Petrosynts KO, Khritonov IA, Smursky LM, Bogtyrev VN, Povrnitcyn ZM, Drozdenko ES (2012) Simultion of totl dose influence on nlog-digitl SOI/SOS CMOS circuits with EKV- RAD mcromodel. Proc. 10th IEEE Est-West Design & Test Int. Symp. (EWDTS) Petrosynts KO, Khritonov IA, Smursky LM, Mokeev AS (2015) Rd-hrd versions of SPICE MOSFET models for effective simultion of SOI/SOS CMOS circuits tking into ccount rdition effects. Proc. Int Conf Rdit Effects Component Syst (RADECS-2015) Petrosynts KO, Khritonov IA, Smursky LM (2013) Hrdwresoftwre susystem for MOSFETs chrcteristic mesurement nd prmeter extrction with ccount for rdition effects. Adv Mt Res : Petrosynts KO, Smursky LM, Khritonov IA, Lvov BG (2016) Fult simultion in rdition-hrdened SOI CMOS VLSIs using universl compct MOSFET model th Ltin-Americn Test Symposium (LATS): Petrosynts KO, Smursky LM, Khritonov IA, Ytmnov AP (2011) SOI/SOS MOSFET compct mcromodel tking into ccount rdition effects. Russin Microelectron 40(7): Snchez Esqued I, Brny HJ, King MP (2015) Compct modeling of totl ionizing dose nd ging effects in MOS technologies. IEEE T Nucl Sci 62(4): Schwnk JR, Ferlet-Cvrois V, Shneyfelt MR, Pillet P, Dodd PE (2003) Rdition effects in SOI technologies. IEEE T Nucl Sci 50(3): Sexton FW, Schwnk JR (1985) Correltion of rdition effects in trnsistors nd integrted circuits. IEEE T Nucl Sci 32(6): Sterpone L (2013) SEL-UP: CAD tool for the sensitivity nlysis of rdition-induced single event ltch-up. Microelectron Reli 53(9): Wirth GI, Vieir MG, Kstensmidt FGL (2007) Accurte nd computer efficient modelling of single event trnsients in CMOS circuits. IET Circ Device Syst 1(2): Zerev GI, Gorunov MS (2009) Modeling of rdition-induced lekge nd low dose-rte effects in thick edge isoltion of modern MOSFETs. IEEE T Nucl Sci 56(4): Konstntin O. Petrosynts received his Ph.D. degree for the work on semiconductor devices nd circuit modeling in 1974 nd Doctor of Eng.Sc. Degree for the work on TCAD modeling of VLSI elements in 1985, oth t Moscow Institute of Electronics nd Mthemtics. In 1998 he ws wrded the Government Awrd of Russin Federtion in Science nd Engineering. At present, he is Tenured Professor t Ntionl Reserch University BHigher School of Economics^ (Moscow Institute of Electronics nd Mthemtics). He lso holds position of Chief Scientist in Institute for Design Prolems in Microelectronics, Russin Acdemy of Sciences. He is uthor or couthor of more thn 300 scientific ppers, couthor of 4 monogrphs nd 4 textooks. His re of interests is modeling of semiconductor devices nd VLSI circuits with ccount for therml nd rdition effects. Lev M. Smursky received his Ph.D. degree for the work on compct modelling of SOI/SOS CMOS devices with ccount for rdition effects in 2014 conjointly t Ntionl Reserch University BHigher School of Economics^ (Moscow Institute of Electronics nd Mthemtics) nd Institute for Design Prolems in Microelectronics, Russin Acdemy of Sciences. He is currently employed s n Associte Professor t HSE nd Reserch Fellow in IPPM RAS. He is uthor or couthor of more thn 80 scientific ppers. His primry reserch interests include modeling of semiconductor devices nd VLSI circuits with ccount for therml nd rdition effects. Igor A. Khritonov received his Ph.D. degree for the work on semiconductor devices nd circuit modeling in 1998 t Moscow Institute of Electronics nd Mthemtics. He is with Ntionl Reserch University BHigher School of Economics^ (Moscow Institute of Electronics nd Mthemtics), where he is Professor. He is uthor or couthor of more thn 150 scientific ppers. His ctivities focus on modeling of semiconductor devices nd VLSI circuits with ccount for therml nd rdition effects.

15 J Electron Test (2017) 33: Boris G. Lvov received his Ph.D. degree in 1980 nd Doctor of Eng. Sc. Degree in 2001 for the works on semiconductor mterils nd devices, oth t Moscow Institute of Electronics nd Mthemtics. In 1984 he ws wrded the USSR Stte Prize in Science nd Engineering nd in 2003 the Prize of the Russin Federtion President in Eduction. He holds the position of Full Professor t Ntionl Reserch University BHigher School of Economics^ (Moscow Institute of Electronics nd Mthemtics). He is uthor or couthor of more thn 230 scientific ppers, couthor of 3 monogrphs nd 1 textook. His current reserch interests include qulity mngement in electronics nd nnoelectronics engineering.