Solid-State Electronics

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1 Solid-Stte Electronics 5 (9) 8 9 Contents lists ville t ScienceDirect Solid-Stte Electronics journl homepge: PSP-SOI: An dvnced surfce potentil sed compct of prtilly depleted SOI MOSFETs for circuit simultions W. Wu, *,X.Li, G. Gildenlt, G.O. Workmn, S. Veerrghvn, C.C. McAndrew c, R. vn Lngevelde d, G.D.J. Smit e, A.J. Scholten e, D.B.M. Klssen e, J. Wtts f Deprtment of Electricl Engineering, Arizon Stte University, GWC B, 65 E. Tyler Mll, Tempe, AZ , USA Freescle Semiconductor Inc., 5 Ed Bluestein Boulevrd, Austin, TX 787, USA c Freescle Semiconductor Inc., Tempe, AZ 8584, USA d Philips Reserch Lortories, 5656 AE Eindhoven, The Netherlnds e NXP Corporte Reserch, 5656 AE Eindhoven, The Netherlnds f IBM Microelectronics Center, Essex JunctionT 545, USA rticle info strct Article history: Received My 8 Received in revised form July 8 Accepted 8 Septemer 8 Aville online 7 Novemer 8 The review of this pper ws rrnged y Prof. S. Cristolovenu Keywords: Prtilly depleted SOI MOSFETs Compct Surfce potentil History effect Tunneling current Self-heting Body resistnce Hrmonic lnce This pper reports recent progress in prtilly depleted (PD) SOI MOSFET ing using surfce potentil sed pproch. The new is formulted within the frmework of the ltest industry stndrd ulk MOSFET PSP. In ddition to its physics-sed formultion nd sclility inherited from PSP, PSP-SOI cptures SOI specific effects y including floting ody simultion cpility, prsitic ody currents nd cpcitnces. A nonliner ody resistnce is included for ccurte chrcteriztion nd simultion of ody-contcted SOI devices. The PSP-SOI hs een verified using test dt from 9 nm to 65 nm PD/SOI processes. Ó 8 Elsevier Ltd. All rights reserved.. Introduction In recent yers prtilly-depleted SOI technology hs ecome the minstrem technology for low-power, high performnce CMOS ULSI pplictions [,]. Successful use of SOI technologies requires physics-sed SOI MOSFET compct to serve s the ridge etween the mnufcturing process nd circuit design. Such must fithfully reproduce the device chrcteristics responsile for the dvntges provided y SOI technology, such s reduced junction cpcitnce, elimintion of the ody effect in stcked devices (e.g., nmos trnsistors in NAND gtes), dynmic threshold voltge shifts ssocited with the floting ody effect (FBE), nd the corresponding increse of the I on =I off rtio which is eneficil for low-power CMOS pplictions. In ddition to the trditionl requirements imposed on SOI compct s, ggressive scling of the gte oxide thickness to * Corresponding uthor. Tel.: ; fx: E-mil ddress: weimin.wu@su.edu (W. Wu). nm nd elow introduces gte-tunneling current components tht cuse device performnce degrdtions []. The importnce of gte-tunneling currents is common to oth ulk nd SOI devices. However, the presence of floting ody in SOI devices requires physicl ing of electron tunneling from vlence nd (EVB), which is usully not criticl for ulk MOSFET s. For oth ulk nd SOI CMOS technologies, the reduction of power supply voltge to out V mens tht the moderte inversion region ecomes frctionlly lrger prt of the overll voltge swing [4] nd needs to e ed ccurtely using either inversion chrge sed [5,6] or surfce potentil sed [7 ] compct s. The ltter re lso cple of physics-sed description of ccumultion region ehvior nd overlp cpcitnces, which is importnt for ccurte simultions of dvnced CMOS circuit performnce []. Consequently, one of the dvnced surfce potentil sed s (PSP) hs een dopted s the new industry stndrd [] for ulk MOSFETs. Both threshold voltge sed [] nd surfce potentil sed SOI s hve een pulished [4 6]. Reflecting the stte-of-the-rt of ulk CMOS ing in 8-/$ - see front mtter Ó 8 Elsevier Ltd. All rights reserved. doi:.6/j.sse.8.9.9

2 W. Wu et l. / Solid-Stte Electronics 5 (9) the previous decde, s summrized in [7], the PSP-SOI rings into the SOI relm the dvntges of recent work on the development [,8] nd verifiction [9] of surfce potentil sed ulk MOSFET s. This pper ddresses exclusively the ing of prtilly-depleted SOI devices. With the reduction of silicon film thickness one my encounter trnsition to full depletion (FD) mode of opertion t lest for some terminl voltges. The dynmic depletion descriing this ehvior will e presented seprtely. Experimentl dt used in the present study do not exhiit this ehvior. PSP-SOI shres the non-itertive lgorithm for the surfce potentil clcultions used in PSP nd is vlid for high forwrd is of source/drin junctions tht cn e encountered in the floting ody SOI devices. It lso shres PSP s physics-sed formultion nd descriptions of smll geometry effects, which cme from merging the est fetures of SP [7] nd MM []. In prticulr, this ssures complete Gummel symmetry, including the recent requirements imposed on compct s in the presence of tunneling nd impct ioniztion currents []. PSP-SOI [] differs from SP-SOI [6] in severl criticl spects. In prticulr, while the moility description remins the sme, the velocity sturtion is chnged to tht of PSP nd llows ing of higher-order derivtives t zero drin-to-source is (V DS ¼ ) [9]. The sme pplies to quntum-mechnicl corrections, chnnel length modultion nd severl other short-chnnel effects which re ed following the PSP pproch. The EVB tunneling of PSP-SOI is further dvnce s is the much more extensive comprison with experimentl dt. PSP-SOI lso contins detiled surfce potentil sed nonliner ody resistnce. The new PSP-SOI is implemented in Verilog- A nd hs een verified y fitting dt from 9 nm to 65 nm PD/SOI processes. Simultion results re lso presented to illustrte convergence nd specific fetures of the using prmeter sets representing the 9 nm nd 65 nm technologies. This pper proceeds s follows: Section descries the ing of vrious ody current components tht re importnt in cpturing the floting ody effect of SOI devices. Self-heting is nlyzed in Section nd is followed y presenttion of nonliner ody resistnce in Section 4. The noise ing of PD/SOI MOSFETs is presented in Section 5. In Section 6, typicl fitting results on shortchnnel floting ody PD/SOI devices re presented.. Modeling the floting ody effect Fig. shows the equivlent circuit digrm of PSP-SOI. For the floting ody configurtion there re four externl nodes: source (S), drin (D), gte (G) nd sustrte/ck-gte (E). For DC simultions, the ody potentil V BS is determined y the lnce of ody currents from source nd drin junction lekge (genertion/ recomintion), impct ioniztion current, gte-induced drin/ source lekge (GIDL/GISL) nd gte-to-ody tunneling current (which flows etween the gte nd the ody). For trnsient nd AC simultions, in ddition to the DC ody currents BS is influenced y the cpcitive coupling of the ody to the drin, source, gte nd sustrte terminls. For the ody-contcted configurtion, n externl ody contct node (BC) connects to the internl ody node (B) through resistive pth (ody resistnce R B ). In this configurtion, the lnce of currents from the externl ody contct node, cpcitive coupling (displcement currents), nd ovementioned DC pths determines the ody potentil... Junction current In PD/SOI technologies, the junction diode chrcteristics re highly non-idel, from oth chnnel engineering (e.g., hlo doping) Fig.. Circuit representtion of PSP-SOI. I DS intrinsic drin current, I BJT prsitic ipolr current, I ii impct ioniztion current, I GIDL=I GISL gte induced drin (source) lekge. I BS=I BD is source/drin junction current. I GS=I GD; I GB is gte to source/drin/ody tunneling current. Q S, Q D, Q G nd Q E re source, drin, gte nd ck-gte chrges. For ody-contcted SOI, n extr node (BC) is provided to control the internl ody node (B) voltge through ody resistnce R B. nd source engineering (e.g., Ge implnttion). Therefore, physicl nd ccurte junction is crucil in ing the floting ody effects in PD/SOI devices nd circuits, such s the kink effect nd the history dependence of propgtion delys []. PSP-SOI uses the most dvnced junction JUNCAP [4], which includes idel drift nd diffusion current, Shockley Red Hll recomintion nd genertion current, trp-ssisted tunneling current, nd nd-to-nd tunneling current. In PSP-SOI the idel drift nd diffusion current is given y I idel ¼ I DSAT exp V B;S=D : ðþ / T Here I DSAT is the idel sturtion current density B;S=D is the pplied is etween the ody nd the source/drin, / T is the therml voltge. The recomintion nd genertion current nd trp-ssisted tunneling current re given y I SRH ¼ C SRH exp V B;S=D w SRH W dep ðþ / T nd I TAT ¼ C TAT exp V B;S=D C SRH W TAT ; / T respectively. Here C SRH nd C TAT re fitting prmeters, W dep is the depletion-region width. Detiled expressions for w SRH, C TAT nd W TAT re given in [4]. The nd-to-nd tunneling current is given y I BBT ¼ C BBT V B;S=D F mx exp F ; ð4þ F mx where C BBT nd F re lso prmeters. F mx is the mximum electrosttic field in the depletion region of junctions [4]. The totl junction current is given y I B;S=D ¼ I idel þ I SRH þ I TAT þ I BBT : Temperture dependence of junction current is lso physiclly ccounted for in JUNCAP. This is importnt ecuse when the device locl temperture is incresed y self-heting, the lekge current increses nd the ody potentil ecomes lower, resulting in ðþ ð5þ

3 W. Wu et l. / Solid-Stte Electronics 5 (9) 8 9 less pronounced kink effect in floting ody PD/SOI output chrcteristics. As shown in Fig., the JUNCAP cn fit well junction lekge current of ody-contcted PD/SOI MOSFET (source is tied to drin) t three different mient tempertures for oth forwrd nd reverse ised regions... Impct ioniztion current The impct ioniztion current induced t the drin side flows into the ody region nd rises the ody potentil. This gives rise to the kink effect oserved in the output chrcteristics of PD/ SOI devices. PSP-SOI uses the sme impct ioniztion s PSP [5,6]. It includes ccurte descriptions of the suthreshold region nd the effect of ody is V BS I ii ¼ A DV SAT;ii exp ; ð6þ I DS DV SAT;ii DV SAT;ii ¼ V DS A Dw; ð7þ ¼ A T ja h KD T þ A p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi p / 4 B V BS ffiffiffiffiffi i / B : ð8þ KR Here A, A, A nd A 4 re prmeters, Dw ¼ w sd w ss, w ss nd w sd re the surfce potentils t the source nd drin ends of the chnnel, respectively, nd / B ¼ / T lnðn A =n i Þ is the Fermi potentil, where N A is the sustrte doping density nd n i is the intrinsic crrier density of silicon. In SOI MOSFETs, the impct ioniztion current is enhnced due to self-heting [7]. This temperture dependence of I ii is ccounted for y introducing the temperture dependence prmeter j A of impct ioniztion exponent. T KD, T KR re the device nd reference tempertures, respectively. Selfheting effect is discussed in Section. Fig. shows the fits the sustrte current of shortchnnel SOI device very well, including the low drin nd low gte is regions. This is importnt to cpture the experimentlly oserved grdul turn-on of kink effect... Gte-induced drin lekge current High electricl field my e induced in the gte-to-drin (source) overlp regions when the MOSFET is in off-stte (gte is V GS 6 ) nd cuses significnt lekge current flow etween the Body current (A) o C Drin voltge (V) symols: lines: Fig.. Model fit of junction lekge current. The source nd drin terminls of the ody-contcted n-chnnel SOI device re tied together. V GS ¼ V. W=L ¼ =:65 lm. Sustrte current, ma drin (source) nd the ody [8]. For floting ody PD/SOI MOS- FETs, this current cn rise the ody potentil if the device is ised into ccumultion region nd my ffect the hysteresis ehviors [9]. In PSP-SOI, this is ed y [,5] I GIDL ¼ A GIDL V DB V tov V ov exp B GIDL ; ð9þ V tov qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V tov ¼ V ov þðc GIDL V DB Þ ; ðþ where A GIDL / W L OV, W is the chnnel width nd L OV is the overlp length of the gte-to-drin (source) overlp region. V DB is the drinto-ody is ov is the voltge cross the overlp region. V tov is proportionl to the mximum electricl field t the Si=SiO interfce in the overlp region. B GIDL nd C GIDL re prmeters..4. Gte-to-ody tunneling current As the gte oxide thickness t ox scles to. nm, the oxide tunneling current increses drmticlly. Gte-to-ody tunneling includes severl components: ECB (electron tunneling from conduction nd), HVB (hole tunneling from vlence nd) nd EVB (electron tunneling from vlence nd) []. In ulk MOSFETs EVB tunneling genertes the sustrte current, which is much less thn the gte-to-chnnel tunneling current (ECB or HVB) nd therefore cn e neglected. However, in SOI MOSFETs the EVB tunneling current chrges nd dischrges the ody, nd consequently ffects the threshold voltge V T y ltering the ody potentil. The impct of gte-to-ody tunneling current on PD/SOI CMOS circuits cn e found in [,]. In PSP-SOI, the EVB is developed from surfce potentil sed pproch. In the Tsu Eski formultion [], the tunneling current density hs the form J EVB ¼ 4pqm h.5 V DS Z qvox E g DðE x ÞðqV ox E g E x ÞdE x ;.5 V DS Fig.. Modeled (lines) nd mesured (symols) sustrte current for odycontcted SOI t 5 C. W=L ¼ =:65 lm. ðþ where q is the mgnitude of electron chrge, m is the effective electron mss in the vlence nd of silicon, E g is the energy gp nd V ox is the voltge cross the oxide. DðE x Þ is the tunneling trnsmission coefficient which comes from WKB pproximtion ( Z sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ) tox m DðE x Þ¼exp ox ½E h C ðxþþe x Šdx ; ðþ where E C ðxþ is the conduction nd energy in the oxide nd m ox is the effective mss of electrons in SiO. Assuming tht the EVB Sustrte current, ma

4 W. Wu et l. / Solid-Stte Electronics 5 (9) 8 9 tunneling current is minly from electrons hving energy E x ¼ in the vlence nd (mono-energetic pproximtion) gives [6] J EVB ðyþ ¼J DðyÞF s ðyþ; where J ¼ q m =ðph Þ; F s ðyþ ¼ðV ox E g =qþ HðV ox E g =qþ ðþ ð4þ ð5þ is the effective supply function. The Heviside step function H mkes J EVB ðyþ ¼ for V ox E g =q <, nd DðyÞ ¼exp B þ G z g þ G z g ð6þ is the trnsmission coefficient, where B ¼ 4t pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ox m ðv ox B þ E gþ h ð7þ nd z g ¼ qv ox =ðe g þ v B Þ ox is the oxide voltge, v B is the conduction nd offset t the Si=SiO interfce. J, G nd G re introduced s fitting prmeters to compenste for the inccurcy of our pproximtions. To void using the Heviside step function, (5) is smoothed s follows F s ðyþ ¼ n EVB / T ln þ exp V ox ne g =q : ð8þ n EVB / T Here n EVB (= y defult) nd n (= y defult) re introduced s tuning prmeters for flexiility. The totl EVB tunneling current is otined y integrting long the chnnel I EVB ¼ W Z L J EVB ðyþdy: Using the symmetric lineriztion method [] gives I EVB ¼ WL HDw Z Dw Dw J EVB ðuþðh uþdu; ð9þ ðþ where u ¼ w s w m, q im is the inversion chrge t the surfce potentil midpoint w m ¼ðw sd þ w ss Þ= nd m is lineriztion coefficient. In simplest cse H ¼ q im = m þ / T when velocity sturtion is negligile []. When velocity sturtion is tken into ccount, H depends on the detils of the velocity sturtion [7,8] H ¼ q im ; m G vst where ðþ " m ¼ m þ # h st Dw ; ðþ G vst q im ¼ q im þ m / T ; ðþ G vst ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi þ þ ðh st DwÞ : ð4þ For n-chnnel trnsistors h st ¼ l eff v st L nd for p-chnnel trnsistors h st ¼ l eff v c L ð5þ r ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : ð6þ þ Dw l eff v cl Here v st denotes the sturtion velocity, v c is prmeter corresponding to the velocity of the longitudinl coustic phonons nd l eff is the effective moility. To otin n nlyticl expression of I EVB, the surfce potentil dependence of trnsmission coefficient is pproximted s [4] DðuÞ ¼D m exp u ; ð7þ u D where v u D ¼ B þ E g qðg þ G z gm Þ ; ð8þ z gm ¼ qv oxm =ðv B þ E g Þ nd V oxm ¼ V GB V FB w m is the oxide voltge t the surfce potentil midpoint. Here V GB is the gte-to-ody voltge nd V FB is the flt-nd voltge. The effective supply function is pproximted y F s ðuþ ¼F sm exp u u F ; ð9þ where F sm ¼ F ss exp Dw ; ðþ u F F ss ¼ ½n EVB / T lnð þ D si ÞŠ ; ðþ D si ¼ exp V oxs ne g =q ; ðþ n EVB / T u F ¼ n EVB / T lnðe þ D si Þ ðþ nd V oxs ¼ V GB V FB w ss is the oxide voltge t the source end. The totl EVB tunneling current is pproximted y I EVB ¼ WLJ Z Dw HDw D mf sm exp u ðh uþdu; ð4þ Dw u where u ¼ u D þ u F : Integrting (4) gives the totl EVB tunneling current I EVB ¼ WLJ D m F sm h ; where h ¼ð Þ sinhðxþ þ coshðxþ x ð5þ ð6þ ð7þ nd x ¼ Dw=ðu Þ, ¼ u =H. As Fig. 4 shows, the drin current I DS is incresed due to higher ody potentil induced y the EVB tunneling. The ccurtely reproduces the liner kink effect induced y the EVB tunneling current [5,6], s oserved in the trnsconductnce g m prticulrly t low V DS. Fig. 5 shows trnsmission-gte multiplexer implementing the Boolen function F ¼ A S þ B S. If initilly the inputs A, B re High (V A;B ¼ V DD ) nd control signl S is Low, the input of the inverter is settled t High. Under this scenrio the pre-switch ody potentil of nmos (N) is determined y the EVB tunneling current nd two forwrd ised junction currents. The ody potentil of pmos (P) is determined y the lnce of ck-to-ck junction lekge currents. The EVB tunneling current hs little impct on the ody potentil of P. Consequently, the initil input-fll dely t plh is lrger nd the input-rise dely t phl is smller ecuse N is stronger ( lower V T ) in the presence of EVB tunneling current. In the trnsient stedy stte, the ody potentils re determined y oth the cpcitive coupling nd DC currents (junction lekge, impct ioniztion current nd EVB tunneling). These re illustrte in Figs. 6 nd 7. Also, the nmos (N) of the top

5 W. Wu et l. / Solid-Stte Electronics 5 (9) with EVB without EVB.8.7 solid lines: with EVB dshed lines: without EVB I DS, ma.5 V BS (N).6.5 T=5 o C 55 o C 85 o C o C.5 V GS () Drincurrent 5 5 Time, ns Fig. 6. Body potentil of nmos (N) efore the input flling trnsition solid lines: with EVB dshed lines: without EVB g m, ms.5 t plh, ps T=5 o C 85 o C 55 o C o C.5 V GS () Trnsconductnce Fig. 4. Impct of gte-to-ody tunneling current (EVB) on the DC trnsfer chrcteristics of floting ody SOI MOSFETs. V DS ¼ :5; :; :6; :; :V, W=L ¼ =: lm Time, ns () Input-fll dely T=5 o C 85 o C t phl, ps o C 5 o C 6.4 solid lines: with EVB dshed lines: without EVB Time, ns ( )Input-rise dely. Fig. 7. Impct of EVB tunneling current on the dely times of trnsmission-gte multiplexer with initil High condition. Simultions re done t severl mient tempertures. The prmeter sets used in simultions re representing typicl 65 nm PD/SOI technology. Fig. 5. () Circuit digrm of trnsmission-gte multiplexer; () input signl wveforms used in simultions. Signl A hs period of ns nd slew time of ps. trnsmission-gte ecomes slightly stronger during input-rise trnsitions due to the EVB tunneling current. This mkes the input-rise dely even fster.

6 W. Wu et l. / Solid-Stte Electronics 5 (9) 8 9 As temperture increses, the junction lekge current ecome lrger nd the mount of ody potentil increse cused y the EVB tunneling, which is less temperture sensitive, ecomes smller. The impct of EVB tunneling current on circuit dely times ecomes less significnt. This is lso illustrted in Figs. 6 nd 7. IN C N P OUT.5. Prsitic ipolr current C The prsitic ipolr trnsistor, which is in prllel with the intrinsic MOSFET, my e ctivted during trnsient switching if there is lrge voltge cross the ody-to-source junction. This ipolr current my cuse extr power consumption, degrde noise mrgins in sttic CMOS configurtions, or led to logicl stte errors in some dynmic circuits [7]. In PSP-SOI, this effect is ed y dding prsitic BJT current element (simplified version of the Gummel Poon [8,9]) I BJT ¼ I S exp V BS q B / T exp V BD / T ; ð8þ V IN V Bn.5.5 where I S is the sturtion current, the normlized se chrge q B includes high-level injection nd Erly effect q B ¼ q rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi þ q þ q ; ð9þ q ¼ þ V BS þ V BD ; ð4þ V A q ¼ I S exp V BS þ I S exp V BD ; ð4þ I K / T I K / T where V A is the Erly voltge of the prsitic ipolr trnsistor, I K is the knee current. The recomintion current in the neutrl ody is lso included. Thus, the totl junction lekge current consists of the recomintion genertion current in the junction depletion regions, hole nd electron diffusion currents nd the recomintion current in the neutrl ody region. For completeness, the diffusion cpcitnce is included s well y introducing trnsit time coefficient s t. Fig. 8 shows Gummel plot mesured on ody-contcted SOI nmosfet, which cn e used to extrct prsitic ipolr current prmeters. A mximum ipolr gin of is oserved for this device. At lrge forwrd V BS, the ipolr gin ecomes smller due to high-level injection nd series resistnce. I BJT, ma Time, ns Fig. 9. () Circuit digrm of sic pss-gte logic; () wveforms of input signl V IN, ody potentil V Bn nd prsitic ipolr current I BJT in nmos. The prmeters re extrcted from typicl 65 nm PD/SOI technology; W=L ¼ =:65 lm. Fig. 9 shows simultion of pss-gte logic with the PSP-SOI. Initilly, the control signl C nd the input signl IN re High (V DD ). With oth the nmos nd pmos turned on, the drin node nd internl ody potentils settle to V DD. If the source node (IN) is pulled down fter switching the control signl C to Low, lrge ody-to-source voltge is creted. This turns on the prsitic npn BJT nd cuses trnsient ipolr current I BJT to flow. Once the ody is dischrged, this current disppers.. Self-heting effect Current, ma I D The self-heting effect (SHE) in SOI devices nd circuits hs een extensively studied [4,4]. The het generted in the chnnel rises the locl temperture due to the low therml conductivity of the uried SiO (two orders of mgnitude smller thn silicon). In PSP-SOI, the self-heting effect is ed y dding stndrd uxiliry R th C th sucircuit [4,] shown in Fig., where R th nd C th re therml resistnce nd cpcitnce, respectively. Multifinger SOI devices re lso considered in the. For exmple, R th is given y [4] RTHW R th ¼ NF ðwþwthþ ; ð4þ I B.5 V BS Fig. 8. Gummel plot of prsitic BJT in ody-contcted SOI (nmos). The gte nd source re grounded nd V DB ¼ while sweeping V BS. W=L ¼ =:55 lm. where RTHW is the normlized therml resistnce, WTH is the width offset, nd NF is the numer of fingers. This is importnt for low-power RF pplictions. To ccurtely the impct of locl device temperture rise on the device chrcteristics, the temperture dependence of prmeters should e lso included. In PSP nd PSP-SOI, the temperture dependence of flt-nd voltge V FB is ccounted for y V FB ¼ V FB þ j VFB ðt KD T KR Þ: ð4þ

7 4 W. Wu et l. / Solid-Stte Electronics 5 (9) with self-heting without self-heting 4 I DS, ma Fig.. Auxiliry self-heting network. P diss ¼ I DS V DS. The therml node T sh is ccessile y the user to monitor the device temperture in Spice simultions. Here V FB is the flt-nd voltge t the reference temperture, nd j VFB is the temperture coefficient of V FB. The temperture dependence of moility, crrier sturtion velocity nd series resistnce re ed y the following empiricl eqution.5 V DS Fig.. Mesured nd ed output chrcteristics of floting ody SOI nmosfet. W=L ¼ =:65 lm. jp T KR P ¼ P ; ð44þ T KD where P is the corresponding prmeter, P is the vlue of P t the reference temperture, nd j P is its temperture coefficient. The implementtion of self-heting sucircuit in SOI compct should e suject to the following enchmrk test. At fixed drin nd gte ises, the therml resistnce is swept with selfheting enled. The simulted chnnel temperture nd drin current re denoted s T ch nd I DS. Next, under the sme ising condition ut with self-heting disled, the simulted the drin current t the mient temperture T m ¼ T ch is I DS. Then, idelly I DS ¼ I DS. Fig. shows the enchmrk test results of self-heting implementtion in PSP-SOI. Fig. shows the mesured nd simulted sttic output chrcteristics of floting ody SOI device. Simultions for high gte nd drin is without self-heting predict lrger drin current I DS thn when self-heting is included. The rise of device temperture is out 6 K. In most digitl logic pplictions, self-heting is negligile since the power consumption per device under switching condition is Frequency, GHz Temperture rise, K with self-heting without self-heting 5 Temperture, o C 4. x - I ' DS I DS 5 Time, ns Fig.. () Simulted 5 stge ring oscilltor oscilltion frequency t different mient tempertures. Model prmeters re extrcted from 65 nm PD/SOI technology dt; () simulted device temperture rise in nmos t 5 C. Drin current, A Chnnel temperture, o C Fig.. Benchmrk test results of self-heting implementtion in PSP-SOI. W=L ¼ =:65 lm GS ¼ V DS=. V. low [44]. Further, the therml time constnt (. ls) is lrger thn the switching clock rte nd self-heting is therefore effective suppressed. Fig. shows the frequency of 5 stge ring oscilltor simulted t different mient tempertures with self-heting effect turned on nd off. The ctul temperture rise, s simultion predicts (Fig. ), is smll, which suggests tht it is sfe to turn off the self-heting in most digitl circuit simultions. However, selfheting should e tken into ccount in prmeter extrction. The dt re usully tken from sttic s where selfheting effect is significnt. Recently new methodology to derive self-heting free dt (for oth drin nd sustrte currents) hs een proposed to reduce the itertion loops in prmeter extrction process [45].

8 W. Wu et l. / Solid-Stte Electronics 5 (9) Body resistnce In some criticl circuits, like sense mplifiers, where slow vritions of threshold voltge re uncceptle, ody contcts re used to suppress the floting ody effect. A common configurtion is the T gte structure shown in Fig. 4. The ody resistnce depends strongly on the doping profile nd chnnel silicon film thickness. A simple ut inccurte liner often used to estimte the ody resistnce is R B ¼ R sh W L ; ð45þ where R sh is the ody sheet resistnce nd W nd L re the width nd length of the device. In prcticl pplictions the ody resistnce is highly is-dependent. In some cses, the silicon film cn ecome fully depleted nd the resistnce of the ody region ecomes so high tht the ody terminl is effectively disconnected from the internl ody of the device. In PSP-SOI, is-dependent ody resistnce su- is provided to cpture the vrition of R B with the terminl voltges W R B ¼ ; l B Q nr ð46þ where l B is the moility of mjority crrier in the ody (holes in nmosfets) nd Q nr ¼ qn EFF t SI WL Q B ð47þ is the totl moile mjority chrge in the neutrl ody region. Here N EFF is the effective chnnel doping including the effect of hlo implnts, nd t SI is the chnnel silicon film thickness. The totl ulk chrge Q B includes the (front) gte-induced ulk chrge Q f B, the junction depletion chrges Q j;s=d nd the ck-gte induced ulk chrge, s illustrted in Fig. 5. Fig. 6 shows typicl plot of the is dependence of ody resistnce. The ody resistnce vries significntly with the externl ody is V BS even when the device is off (V GS ¼ :V;V DS ¼ V). Fig. 7 shows the mesured nd ed ody resistnce under vrying DC is for n H-gte device. Source W XB Body Contct Extrinsic Gte Gte L Drin L XB W S B BC M M M M4 M5 G D Fig. 4. () Typicl structure of T-gte SOI device. For n H-gte SOI device, nother ody contct is ptterned t the other end of the gte; () schemtic representtion of the T-gte SOI sucircuit used in simultions. Fig. 5. Illustrtion of the clcultion of moile chrge Q nr in the neutrl ody region. Body resistnce, MΩ V BS Depending on the is conditions, R B my vry y orders of mgnitude. This shows tht proper ing of ody resistnce is crucil to ing of the trnsient ehvior of ody-contcted SOI devices. Floting ody relted effects re usully chrcterized from s on ody-contcted devices cross wide rnge of is. The is dependence of R B should e tken into ccount during the prmeter extrction process. The effect of ody resistnce is distriuted in nture [46]. In our simultions, the wide ody-contcted SOI device is prtitioned into severl smller segments (e.g., 5) long the width direction nd they re cscded together with proper hndling of nrrow-width effects. The numer of segmenttion is selected y the user sed on the desired ccurcy. For prmeter extrctions, the ody resistnce is effective to leed off vrious ody currents without cusing noticele voltge drop long the ody resistnce. FBE, moility, etc will not e ffected under dc conditions. Thus, it is not necessry to segment during the prmeter extrction steps. 5. Noise ing V ES = V - nonliner RB Fig. 6. Mesured nd ed ody resistnce of ody-contcted SOI device (Hgte). V GS ¼ :V DS ¼ V, ck-gte is V ES ¼ ; V. W=L ¼ =:65 lm. The extrcted film thickness t SI ¼ 45 nm nd uried oxide thickness t BOX ¼ 8 nm. The sudden drop of R B ner V BS ¼ :8 V is cused y junction currents. Silicon-on-Insultor technology hs ecome vile option for RF pplictions nd RF systems-on-chip. Consequently, ccurte noise description in PD/SOI MOSFETs ecomes essentil. The two min noise sources in MOSFETs re the low frequency noise (lso clled /f noise) nd the therml noise. In PSP-SOI, these noise sources, together with the chnnel induced gte noise re ed physiclly following the description developed for the

9 6 W. Wu et l. / Solid-Stte Electronics 5 (9) nonliner RB V GS =.V iclly from the chnnel therml noise using surfce potentil sed formultion. Severl other noise sources common to PSP nd PSP- SOI re lso included, such s shot noises ssocited with gte-tunneling current, junction lekge current nd impct ioniztion.. Body resistnce, kω V DS I DS, ma Body resistnce, kω nonliner RB V DS =.V..5.5 V DS V GS Fig. 7. Mesured nd ed ody resistnce of n H-gte SOI structure under vrying DC is condition. W=L ¼ 4= lm. g DS, ms V DS Drin noise voltge spectrl density,v /Hz -9 - V DS =.6,.7,.8,.9V c g DS, ms/v Frequency, Hz Fig. 8. Simulted equivlent drin output noise spectrl density; V GS ¼ :8 V. W=L ¼ =:65 lm. Sme set of prmeters s in Figs. 9 nd re used in simultion V DS ulk PSP Model including velocity sturtion effects [47,]. In prticulr, the shot noise in suthreshold region is recovered utomt- Fig. 9. Output chrcteristics of short-chnnel floting ody nmosfet. () Drin current; () conductnce g DS ; (c) higher-order conductnce g DS. W=L ¼ =:55 lm. V GS ¼ :; :4; :6; :8::; :V.

10 W. Wu et l. / Solid-Stte Electronics 5 (9) PSP-SOI includes three dditionl noise sources reltive to the ulk PSP : shot noise ssocited with the EVB tunneling current with the spectrl density [48] S IEVB ðg; BÞ ¼qI EVB ð48þ Accurte simultion of simple pssive mixers cn e surprisingly difficult due to the singulr ehvior of some compct s t V DS ¼ [5 55]. This prolem ws solved in [54] for the cse of ulk MOSFETs. The difficulty stems from the sensitivity of this nlysis to the fct tht the second derivtive d I DS =dv DS does nd the shot noise ssocited with the prsitic BJT [49] S IBJT ðd; SÞ ¼qI BJT : ð49þ For ody-contcted SOI device, the therml noise generted in the ody resistnce [5] is S V;RB ðb; BCÞ ¼4k B TR B ; ð5þ where the ody resistnce R B is given y (46). For floting ody PD/SOI MOSFET, experimentl dt indicte the presence of excess Lorentzin-like noise overshoot in the low-frequency rnge [5,5,49]. The frequency dependence of the excess noise spectrl density hs een found to e S f ¼ S þ ðf =f c Þ ; ð5þ where S corresponds to the low-frequency plteu nd f c is the corner frequency, which is determined y the smll signl impednce of the ody node nd hence strongly depends on the drin is through impct ioniztion current. The excess noise in the drin current is cused y the floting ody effect which mplifies the shot noises ssocited with the ody-source junction current [5], impct ioniztion current, gte-to-ody tunneling current, nd for ody-contcted SOI, the therml noise of the ody resistnce. Since the prsitic ody currents nd the ssocited shot noises re physiclly ed in PSP-SOI, the excess noise t low frequency with the spectrl density (5) comes out utomticlly. The simulted equivlent drin output noise is shown in Fig. 8, demonstrting the qulittive greement of simultion results with experimentl oservtions [5]. 6. Model verifiction PSP-SOI hs een verified ginst severl PD/SOI processes, including 9 nm nd 65 nm nodes. Figs. 9 nd show typicl fitting results on n n-chnnel floting ody SOI MOSFET with chnnel length L ¼ 55 nm. In the prmeter extrction routine, we first extrct the prmeters on ody-contcted n-chnnel MOSFET with the sme chnnel length. Prsitic current components which control the floting ody effect (s discussed in Section ), such s impct ioniztion, junction lekge, etc., re extrcted from seprte dc s. As we cn see, not only the drin current is ccurtely reproduced y the PSP-SOI, the conductnce (Fig. 9) nd trnsconductnce (Fig. ) re lso reproduced y the. This demonstrtes tht PSP-SOI is suitle for oth digitl nd nlog pplictions. In order to simulte the signl distortion ssocited with the nonlinerities of PD/SOI MOSFETs, the compct used in circuit design should lso e le to reproduce the higher-order conductnce nd trnsconductnce, defined s g DSi ¼ oi I DS ; ð5þ ov i DS g mi ¼ oi I DS ; ð5þ ov i GS i ¼ ;. As shown in Figs. 9c nd c, g DS nd g m re lso fithfully reproduced y PSP-SOI. I DS, ma c g m, ms/v g m, ms V GS.5 V GS.5 V GS Fig.. Trnsfer chrcteristics of short-chnnel floting ody nmosfet. () Drin current; () trnsconductnce g m ; (c) higher-order trnsconductnce g m. W=L ¼ =:55 lm. V DS ¼ :5; :; :4; :6; :8::; :V.

11 8 W. Wu et l. / Solid-Stte Electronics 5 (9) 8 9 V IN V G simultions were performed to illustrte the vlidity of PSP-SOI s n essentil tool for simulting PD/SOI circuits. PSP-SOI hs een tested for severl PD/SOI technology processes, including 9 nm nd 65 nm nodes. Acknowledgements -5 - n = This work is supported in prt y the Semiconductor Reserch Corportion nd IBM fculty wrd. The new enchmrk test for the self-heting hs een suggested y Q. Chen. We re grteful to L. Lemitre nd G. Corm for their help with the Verilog-A implementtion, nd to B. Mulvney for the use of the Mic Ó simultor. References I D,dB PSP-SOI simultion Theoreticl slope V IN,dB not exist for V DS ¼ in other MOSFET compct s (oth ulk nd SOI s). This prolem hs een trced in [5,54] to the use of source-referenced threshold voltge nd singulr velocityfield dependence. The non-singulr nture of PSP-SOI llows ccurte simultion of pssive mixers using SOI devices. Typicl results shown in Fig. illustrte the correct slopes for the hrmonic components. As in the cse of ulk PSP, this requires the condition [9] AX > n ; ð54þ where n is the order of hrmonic component, prmeter AX is used to clculte the effective drin voltge V DS;eff in the PSP nd PSP-SOI s V DS V DS;eff ¼ : ð55þ AX j þ V AX DSj V DSAT Since AX is sclle nd needs to ensure tht (55) holds for ll relevnt chnnel lengths [,9]. 7. Conclusions 4 Fig.. () Circuit digrm for hrmonic lnce simultion; () single tone hrmonic lnce simultion result for PSP-SOI; V g ¼ :8 V, W=L ¼ =:55 lm, fundmentl frequency is MHz. A comprehensive surfce-potentil-sed compct of prtilly-depleted SOI MOSFETs is presented in this study. The new, PSP-SOI, is formulted within the frmework of the ltest industry stndrd MOSFET ulk PSP. It cptures the floting ody effect in PD/SOI MOSFETs nd circuits y physiclly incorporting ll relevnt prsitic currents nd cpcitnces. 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