Design for Manufacture Methodology for SiP A Two Year IeMRC Supported Project

Transcription

1 LANCASTER U N I V E R S I T Y Centre for Microsystems Engineering Faculty of Applied Sciences Design for Manufacture Methodology for SiP A Two Year IeMRC Supported Project Stacked Structures Side-by-Side Structures Embedded Structures

2 SiP-Design Two Year Funded Project January 2006 December 2007 Funding 200,000K : Supports RA s at Greenwich and Lancaster Additional financial support from FP6 NoE in Design for Micro & Nano manufacture (PATENT-DfMM)

3 SiP-Design : Industrial Support NXP Wafer Level SiP Producer Selex Avionics Systems Flomerics Thermal/Electrical Design Solutions Coventor SiP Design Tools and Design for Manufacture Methodology

4 Objectives Realise algorithms and associated code to generate an integral thermal map across a behavioural model of an SiP function. Realise algorithms and associated code to model and couple electromagnetic and electrostatic fields into functional devices and materials within an SiP structure. Realise a method of injecting defects and degradation into behavioural SiP models. Address the Test Issue. Demonstrate the above advances in an industrial Virtual Prototype environment.

5 Key Challenges addressed Thrmo-mechanical modelling of Assembly and interconnect Stress and electromagnetic contamination monitoring within SiP packages Embedded Test

6 Lancaster University Centre for Microsystems Engineering 4 academic staff, 5 RA s, 4 PhD s Delivered against 3.4M in grant income over the past 10 years Leads the European Design for Micro & Nano manufacture community through the FP6 Network of Excellence (PATENT-DfMM)

7 Centre for Microsystems Engineering - Mission Research, training and industrial services in the Engineering Science associated with Design for Manufacture Technology for Micro & Nano Technology based Products Key Skills Design methodology, modelling & simulation of MNT based structures and systems. Fault tolerant design, design for test, condition monitoring and test engineering for MNT based systems. Integration technology for MNT based systems (packaging) Active Projects EU FP6 INTEGRAMplus" Integrated MNT Platforms & Services (IP), PATENT- DfMM Design for Micro & Nano Manufacture (NoE) and MINOS-EURONET Micro-Nanosystems European Network pursuing the integration of NMS and ACC in ERA. EPSRC "Nanoelectronics : from novelty toys to functional systems" and IeMRC projects SiP-Design and I-Health. HEIF / NWDA Science & Entrepreneurship training award in MNT

8 University of Greenwich Centre for Numerical Modelling and Process Analysis 5 Profs, 20+ Post Docs, 40 + PhD s One of largest groups in UK Electronics and Microsystems 2 Profs, 3 Post Doc s, 5 PhD s Over 2m of support since 1998 in electronics and microsystems modelling.

9 Expertise - Reliability Physics of Failure approach Exploitation of COTS Modelling to support HALT Thermal, Power Cycling, Vibration BGA s, Flip-Chip, etc. Consumer, Medical, Aerospace, automotive, etc. Accelerated Life Testing Fatigue, etc

10 Interest from NXP Solder Joint Reliability Wafer Level CSP SiP Modules Virtual Design of Experiments Thermo-mechanical Analysis Vertical Metallic Structures in Silicon Electro-magnetic analysis shielding of TV tuner device Diagnostics/Test Bench Embedded Test Low cost, high throughput embedded test solutions

11 Interest from Selex E-Scan Radar Technology Transmission/Receive Modules Power Amplifier + Core Chip High Power Density High Frequency Concerns Thermal Management CTE Miss-match Lead-Free Solders Modelling GaAs MMIC Transient Analysis for High Frequency Trade-off between electrical, thermal and mechanical 3W Si ASIC ASIC 0.5W

12 Progress to Date (1 st 9 months) NXP main driver with Flomerics and Coventor providing tool access Build a modeling & Simulation infrastructure to build a reliable SiP infrastructure (assembly and interconnect) Build a solution to monitoring stress and electromagnetic contamination within SiP packages Investigate embedded test solutions for both the SiP infrastructure and RF / functions with non-electrical interfaces.

13 Reduced Order Modelling (ROM): Model Reduction Techniques Order Reduction Techniques Proper Orthogonal Decomposition Krylov Subspace Methods Response Surface Analysis Compact Models Full Model PDES Space discretisation System of n ODEs Model Reduction Reduced system of r<<n ODEs

14 Assembly & Interconnect (NXP Demonstrator) Top passivation Passive die UF1 UF3 UF2 Active die PCB Objectives: Investigate the influence of various design parameters and their combinations on the reliability (life time) of SiP Perform sensitivity analysis and identify the most influential factor(s)

15 Failure Models Solder (SAC) γ Creep cr = A sinh n ( ασ ) exp( Q RT ) A n α Q/R Sn37Pb 9.6E Sn3.5Ag 9.0E Failure Model (Fatigue) N f = ( Wp) 1 Creep Strain Energy

16 Geometry One-eight of the SiP modelled due to symmetry Passive die UF1 Active die PCB Balls UF3 UF2

17 Von Misses Stress and Deformation Modes for SiP 11 11

18 Identifying Suitable Underfills Design Space Youngs Modulus CTE Design of Experiments Top passivation UF2 PCB Damage (Pa) Passive die UF1 UF3 Active die E (GPa) E(GPa) CTE (ppm/ C) CTE(ppm/C) 60 2

19 Reduced Order Model for Underfills The cost function that expresses Accumulated Creep Energy Density in terms of CTE (C) and Young Modulus (E) found by Composite Design Method appears to be quadratic 2 2 F( C, E) a be d E gc h = C + + C + + E + k a b d g h k Damage (Pa) E (GPa) o 20 C 60(ppm/ C) 2 E 6(GPa) S21 S16 S11 CTE (ppm/c) S6 S1

20 Identifying Critical Design Paramters What can designer change? Underfill 2 & 3 Die Size Die Thickness Top passivation UF2 PCB Passive die UF1 UF3 Active die Die Size Reinforcement (UF2) Underfill (UF3) Passive Die Thickness Actual values 7 7; 9 9; 11 11mm No; Yes No; Yes 200µm; 400 µm

21 Sensitivity Analysis A contribution of a critical parameter to the cost function appears linear f ( x, x, x, x ) = ax + bx + cx + dx + e Accumulated Creep Energy Density Actual values Values in f x 1 Size 7 7; 9 9; ; 0; 1 x 2 Reinforcement (UF2) No; Yes -1; 1 x 3 UF3 No; Yes -1; 1 x 4 Passive Die Thickness 200µm; 400 µm -1; 1

22 Sensitivity Analysis f( x, x, x, x ) = ax + bx + cx + dx + e The coefficients of the function have been determined by the Least Squares Method based on 18 experiments a b c d

23 Sensitivity Analysis f( x, x, x, x ) = ax + bx + cx + dx + e a b c d Most influential parameters: a (Size) the highest absolute value 40,000, positive The larger the size, the more the damage, the less reliable SiP c (UF3) the second highest absolute value 36,000, negative If present, the less the damage, the more reliable SiP

24 Status The presence of UF3 can improve reliability of the SiP Package CTE is the most influential CTE as low as possible Elastic Modulus as high as possible SiP design parameters SiP size and presence of UF3 are the most influential parameters Passive Die thickness and Presence of UF2 have smaller effect on solder joint reliability Recommendation: to improve reliability smaller package size with suitable UF3 and thinner Passive Die

25 Solder Ball Reliability Objective : Build an Analytic Method of Reliability for Solder Joint in Package Inter Metallic Layer (IMC) So ACK, Chan YC. Reliability studies of surface mount solder joints effect of Cu-Sn intermetallic compounds. IEEE Trans Comp Pack Manuf Technol Part B 1996; 19: Weibull distribution β : Weibull slope parameter η : Characteristic life parameter N : Random thermal life cycles to failure δ : IMC layer thickness

26 Inter Metallic Layer growth Reflow profile δ : IMC layer thickness t : Reflow time T : Temperature of reflow Dependence on reflow time (given temperature) : Dependence on temperature (given time) : * Ts : saturated temperature * More accurate than polynomial fitting proposed in Huang W, Loman JM, Sener B. Study of the effect of reflow time and temperature on Cu-Sn intermetallic compound layer reliability. Microelectronics reliability. 42(2002)

27 Results : 3D plots - Low reflow temperature Desirable interval [190,240] - As small a reflow time as possible

28 Status Reliability and MTTF of solder joint (63Sn37Pb) depend on reflow time and temperature. For high reliability we suggest reflow temperature between 190 o C & 240 o C. Avoid temperature between 250 o C and 270 o C. Reflow time is as low as possible. Next Investigate the lower limit of the reflow time. Extend this method to other solder material.

29 Electromagnetic Contamination Monitoring Investigated two antenna architectures : Dipole Loop Analytical model for these two antennas exists

30 Dipole: Simulation versus analytical model 1.00E E E E E E-09 h = 7.5cm 1.00E-01 h e = 7cm S max = 0.07 V/V/m C a = 1.37 pf Sensitivity (V/V/m) Analytical Simulation /1 Simulation /pt 1.00E E-03 Cl (F) 1.00E-04 MicroStripes simulation

31 Dipole: Simulation versus analytical model Without load H z (centre) = 1.33mA/A

32 Status Initiated work on standard EM probes Initiated simulation work using MicroStripes Working with Philips technology to design the EM probes Working with Philips to evaluate the shield effectiveness using MicroStripes Investigating Intra SiP coupling

33 Embedded Test Health Monitor Concept Vision : An embedded tester challenge : non-electrical interfaces Analog IC RF Electronic Digital IC - Production testing - Online testing - Reconfiguration Health monitor MEMS Memory SiP Standard test access Low cost Reusable, flexible, standard: programmable, reconfigurable Low performance -> low frequency Share by a lot of components Have a lot of functionalities : production testing, online testing and reconfiguration/reparation of the SiP to improve yield or reliability.

34 Example 1 RF Receiver / transceiver MEMS inductors, MEMS variable capacitance, MEMS switches, MEMS resonator, MEMS micro machined cavity, Micromachined transmission lines

35 Case study : RF MEMS capacitive switch UP DOWN Bridge Dielectric Substrate V bias RF choke RF in DC block DC block C up / C down RF out Equivalent schematic with passive components to superpose the actuation signal

36 MEMS switch : bias superposition C tf R tf V tr Enveloppe detector Test response analyser R act V bias V stim Actuation generator V act C p RF in C bl L ch V s C bl C stim RF out Test generator V in V out RF switch controller C up / C down Health Monitor Switch with passive components Passive components integrated on the substrate

37 MEMS switch : bias superposition Actuation generator output RF line voltage UP DOWN Amplitude variation Switch output Test response In the UP state, the capacitance measurement is affected by parasitic capacitances. Stiction and breakdown of the dielectric should be detected

38 Status Low frequency testing of a RF MEMS switch by the a low cost Health Monitor is possible although limited by parasitic impedances The feasibility of this technique should be proven on other devices to build a Health Monitor

39 Outputs 3 Conference Papers IEEE IMSTW, June 2006, Edinburgh. NMI / EPPIC workshop on wafer level packaging, June 27th 2006, Cambridge. IEEE EPTC, December 2006, Singapore Invitation for Journal Article in Circuit World Invitation for FP7 Proposal Collaboration

40 Conclusions SiP technology is complex and now the primary packaging platform for integrated MEMS Research challenges associated with manufacturability extensive and beyond the scope of the project Initial work focused on 4 challenges Assembly reliability, solder ball reliability, electromagnetic contamination and embedded test Future focus on assembly and interconnect reliability simulation Electromagnetic contamination and embedded test handled by I-Health Looking to FP7 for further support in cooperation with French national project AMELIA.