Design Of A Power Amplifier Based On Si-LDMOS For WiMAX At 3.5GHz

Transcription

1 ITB Department University Of GävleG Sweden Design Of A Power Amplifier Based On Si-LDMOS For WiMAX At 3.5GHz CHARLES NADER June 2006 Master s s Thesis in Electronics/Telecommunication Supervisor: Prof. Nuno Borges De Carvalho Examiner: Prof. Daniel Rönnow R 1

2 Introduction This Thesis Work Is Carried Out At The Department Of Electronics And Telecommunications, Instituto De Telecomunicações, Universidade De Aveiro, Portugal In This Work, We Will Design A Power Amplifier For WiMAX Applications At 3.5GHz Based On Cheap Si- LDMOS Technology And We Will Analyze The Behavior Of The Design Regarding Nonlinear Distortions And Memory Effects 2

3 Outline WiMAX Si-LDMOS Transistor Power Amplifier Design And Simulation Implementation And Measurements Second Design Intermodulation Distortions And Memory Effects Conclusions And Future Work 3

4 WiMAX What Is WiMAX? WiMAX - Worldwide Interoperability for Microwave Access Next Generation Wireless Network For Data Provide Interoperable Broadband Wireless Connectivity To Fixed, Portable And Nomadic Users NLOS High-Speed Connectivity Up To 70 Mbps With A Service Area Up To 50 Km. 4

5 WiMAX Properties Frequency Allocation 2.5GHz, 3.5GHz, 5.8GHz Signal Bandwidths 1.25MHz to 20MHz Modulation QPSK, 16QAM, 64QAM OFDM with 256 sub-carriers OFDMA with 2048 sub-carriers 5

6 WiMAX Power Amplifier For BS Frequency Bandwidth Power Level Operation Class Efficiency SNDR (EVM) 3.5 GHz 20 MHz > 29 dbm A-AB AB (Highly Linear) 4-5% at 6dB Backoff 32 dbc (2.5%) 6

7 Si-LDMOS Features Si-Lateral Diffused MOSFET Widely Used In BS s s Power Amplifiers For Wireless Communication Cheap Technology High Power Gain Good Linearity And High Thermal Stability Low Intermodulation Distortions 7

8 Si-LDMOS RF Properties Low Doped & long n-drift n region High Breakdown Voltage High Output Power High Drain Resistance Degrade RF Performance Short p-type p Channel & Sinker Principle Better Saturation Velocity Less Number Of Contacts Lower Source Inductance Enhance RF performance 8

9 Power Amplifier Operation Classes Class A/AB PAE 50 % Highly Linear Class B PAE 78.5 % Lower Power Dissipation Class C PAE 100 % Highly non-linear 9

10 Power Amplifier Properties Efficiency (%) High Efficiency Results In Longer Battery Life And Lower Self Heating η=pout/pdc PAE=(Pout-Pin)/Pdc Pin)/Pdc Linearity Non Non-linearity Is Attributed To Gain Compression And Harmonic Lead To Imperfect Reproduction Of The Signal 10

11 Power Amplifier Properties Linearity Characterization 1 db Compression Point Third Order Intermodulation Distortion Third Order Intercept Point (IP3) 11

12 Design & Simulation DUT Motorola s s Electro Thermal (MET) Si-LDMOS MW6S004NT1 Model From Freescale Designed For Class A/AB Base Station Applications With Frequency Up Till 2GHz. Suitable For Analog And Digital Modulation And Multicarrier Amplifier Applications. Typical Output Power Is 4 Watts, 33% PAE And Vds =28V 12

13 Design & Simulation DC Analysis 13

14 Design & Simulation DC Analysis 14

15 Design & Simulation DC Analysis P dmax =(Tj =(Tj-Tc)/RTc)/R JC =8.353Watts ds =28V gs =3.02 V ds = A Knee =2V th =2.5V V ds V gs I ds V Knee V th 15

16 Design & Simulation Bias Network 16

17 Design & Simulation OMN-Load Pull 17

18 Design & Simulation OMN-Load Pull Choose the Load In Order To Maximize The PAE And The Output Power Z L =8.081-j

19 Design & Simulation OMN/IMN 19

20 Design & Simulation Optimization The Design Have Shown A Poor Power Performance Optimization Regarding Maximum Output Power, PAE And Gain. Adjustments In The Matching And Bias Networks Sensibility To Any Changes In Length 20

21 Design & Simulation Optimized Design 21

22 Design & Simulation Optimized Design db Gain Low Output Matching Flatness 0.8 db 22

23 Design & Simulation 1Tone Simulation Pout =37.02dBm= PAE=31.87% PAE=14.5% At 6dB Backoff Gain=13.62dB 23

24 Design & Simulation 2Tones Simulation IMR= IMR=18.83dB IP3(25,40)dBm Low Performance Regarding Intermodulation Distortions 24

25 Manufacturing First Design 25

26 Manufacturing First First Design Measurements Oscillation at 4.12 GHz Small Signal Gain =1.71dB Poor Output Matching High Self Heating Shift In The DC Bias Relative To ADS 26

27 Manufacturing Adjusted Design More Ground Soldering Adjustment Of The Inductance Position 22 Additional Capacitors New Bias Point, Vds=20V, Vgs=3.6V And Ids=242mA Adjustments In The Matching Network 27

28 Manufacturing Sparam. Measurements S21=6.17dB S11= S11=-14.2dB14.2dB S22=2.28dB Flatness=0.155 db Over 20MHz Bandwidth Improved Gain Poor Output Matching 28

29 Manufacturing 1Tone Measurements Rohde & Schwarz Signal Generator And Spectrum Analyzer Gain=5.55dB Pout=28.9dBm 8.57dB Short In Both Compared To ADS 29

30 Manufacturing 1Tone Measurements Third Harmonic Distortion=-47.89dBc PAE At P1dB=9.27% PAE At 6dB Backoff=3.5% 22.6% Lower Than ADS 30

31 Manufacturing 2Tones Measurements Short In Driver Amplifier have Limited the Measurements 31

32 Manufacturing 2Tones Measurements Pout Both Tones= 28.78dBm IMD= IMD=-25.78dBc IP3(33.5, 39)dBm Short of 6.3dB regarding WiMAX Standards SNDR 32

33 Second Design Adjustments Width Transformer (TAPPER) Achieve Width Continuity Between Transistor & Lines And Reduce The Reflections Wide λ/4 Butterfly Stub Have Been Added At The End Edge Of The Tight λ/4 Transformers In The Bias Network Improve The Effect Of The DC-Feeding/RF Feeding/RF-Blocking In The Bias Networks. Bias Point Vds=20V, Vgs=3.14V And Ids=370mA Reduce The Self Heating In The System The Design was Optimized For Maximum Output Power, PAE And Gain 33

34 Second Design Final Design 34

35 Second Design Small Signal Simulation Similar Result As The Previous Design 35

36 Second Design 1&2 Tones Simulations PAE Improved By 3.7% Similar Power Performance 36

37 Second Design Manufacturing 37

38 Second Design Sparam. Measurements Different Behaviour Compared With ADS The Internal Feedback Is Transformed Into A Positive Feedback Bias Point Vds=20V, Ids=270mA and Vgs=3.62V Heat Dissipation At The Surface The Gain Is Improved To 11.55dB At 3.5GHz With A Flatness Of 0.133dB For 20MHz Bandwidth 38

39 Second Design 1&2 Tones Measurements Gain At The P1dB Is 10.59dB For An Output Power Of 24.34dBm. PAE=4.32% Near P1dB And 1.4% For A 6db Backoff IMR= 27.51dB 4dB Short In Power Performance 39

40 IMD Introduction The New Modulation Technologies, Such As OFDM, Require Highly Linear System PA Linearity Is Important As PA Handle The Highest Power Level In The System The Newest Linearization Achievements Is To Optimize The PA Linearity By Searching Large Signal Intermodulation Distortion (IMD) Sweet Spots Which Will Improve The Carrier To IM3 Ratios (IMR) Near The P1dB Compression Point 40

41 IMD New Operation Class Definition Old Class Definition Nonlinear Volterra Series Iout[Vin(t)]= Iout DC + G* Vin(t) + G2* Vin (t)2 + G3* Vin(t)3 41

42 IMD New Operation Class Definition The IMD(Pin) Characteristic Of Each Operation Class Is Characterised By Some Specific Sweet Spot 42

43 IMD Class Simulations Class B(2.39V 2.39V ) Class A(2.98V 2.98V ) Class AB(2.425V 2.425V ) Class C(2.25V 2.25V ) 43

44 IMD Class Simulations Class(V) Pout_dBm ŋ% PAE% Gain_dB HM3_dBc IMR_dB A_ AB_ C_

45 IMD Class Measurements To Determine The Classes Operation 2Tones Measurements; We Will Vary The Gate Voltage With A Frequency Spacing Of 10KHz And Input Power 0dBm. Class B Will Correspond To The Voltage That Minimizes The IM3 Seen At The Spectrum Analyser. Class A: Vds=20V, Vgs=3.6V, Ids=242mA. Class AB: Vds=20V, Vgs=3.07V, Ids=53mA. Class B: Vds=20V, Vgs=2.98V, Ids=36mA. Class C: Vds=20V, Vgs=2.9V, Ids=19mA. 45

46 IMD Class Measurements 46

47 IMD Class Measurements Class(V) Pout_dBm(Both) ŋ% PAE% Gain_dB IMR_dB A_ AB_ B_ C_

48 Memory Effects Definition Change In The Amplitude And Phase Of Distortion Components Caused By Changes In Modulation Frequency. Important When Dealing With Linearization Techniques, Espacially When The Distortion Is Reduced By A Similar Distortion In The Opposite Phase Memory Effects Are Subdivided Into Two Groups: -Short Term -Long Term Or Envelope Memory 48

49 Memory Effects Sources Thermal effects Affect Low Modulation Frequencies Electrical effects Major Part Is Produced By Envelope (Base Band) Impedances Variation. 49

50 Memory Effects Memory effects and IMD Relation Between IMDs And Load Termination At The Base-Band Band Frequency Memory Effects Appear As IMD Asymmetry With Tone Spacing 50

51 Memory Effects Memory effects and IMD Relation Between IMDs And Load Termination At The Base-Band Band Frequency Memory Effects Appear As IMD Asymmetry With Tone Spacing IMD Amplitude Will Change By The Impact Of The Second Order Coefficient Which Is A Function Of The Base-Band Band Frequencies. The Variation Of The IMDs Will Only Appear If Both Output Impedances At w2- w1 And w2+ w1 Are Complex Appear At IMD Sweet Spots Nonlinear Voltera Series 51

52 Memory Effects Measurements Class A Low Memory Effects Class AB 52

53 Memory Effects Measurements Class B Low Memory Effects Class C 53

54 Conclusions and Future Work Class(V) A_ 2.98 Pout_dBm 28.9 Acceptable ŋ% 12.9 PAE% At P1dB At 6dB Backoff Acceptable Gain_dB IMR_dB More Improvements Measurements Results ADS Simulations Improving The ADS Model Of The Transistor Will Lead To A Good Improvement In The Power Performance And Open The Door To The Use Of The Cheap Si- LDMOS Technology In High Frequency Systems 54

55 Professor Nuno Borges Carvalho And I 55

56 Thank You For Your Attention Questions?? :) 56