Case Study: Amp5. Design of a WiMAX Power Amplifier. WiMAX power amplifier. Amplifier topology. Power. Amplifier

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1 MICROWAVE AND DESIGN Case Study: Amp5 Design of a WiMAX Presented by Michael Steer Reading: Chapter 19, Section 19.6 Index: CS_Amp5 Based on material in Microwave and Design: A Systems Approach, nd Edition, by Michael Steer. SciTech Publishing, 13. Presentation copyright Michael Steer Design of a WiMAX power at 1 db gain compression is 8 dbm Slides copyright 13 M. Steer. WiMAX power amplifier Necessary to use nonlinear simulation, harmonic balance analysis preferred. Thermal heat-sinking is very important. Must consider possible layout at the beginning. Must have a topology in mind. Specifications: 8 dbm output power 3 topology High level topology: 1 Z = 5 Linear Class AB amplifier loadline: M Transistor 1 M 1 1 Matching Matching Network Network Gate bias Quiescent point 119 A _ I D 5 V 1 ma Drain bias DC loadline Z = 5 (Final bias voltages are shown) AC loadline V DS 4

2 Transistor selection Bias concept.1 GHz silicon LDMOS transistor. DIE DRAIN SOURCE DIE V GS V BONDWIRES CC BONDWIRES I D (ma) V DIE SOURCE CB CA BONDWIRES GATE 5 1 Quiescent DC power = 5 W. 4 V DS (V) V -1.5 V 1 6 S 11 and S S 33 // 4.4 pf.5 j11 S 1 and S 1 4 operating frequency -5 (db) S -1 S 11 S (db) S S almost 5 operating frequency (with small parallel capacitance) Frequency (GHz) 8

3 Design concept OUTPUT Layout INPUT 9 Index: CS_Amp5B Presentation copyright Michael Steer 1 Layout INPUT OUTPUT matching network 5 LINE INPUT TRANSISTOR GATE DC BLOCK ACITORS 5 RESISTOR LINE WITH HIGH Z GATE BIAS 11 1

4 matching network TRANSISTOR DRAIN (.5 j11 LINE WITH HIGH Z 5 LINE OUTPUT DC BLOCK matching network Z=5 Ohm ID=TL8 ID=C L=.8 mm C=5.6 pf L=8 mm ID=TL3 5 3 L=.8 mm 4 W1=1.156 mm W=.54 mm W=.54 mm L=1.8 mm ID=TL7 W=.54 mm ID=TL9 1 W=.54 mm ID=TL4 3 W1=1 mm W=1.88 mm P= Z=5 Ohm H=.818 mm T=.3556 mm Rho=1. Tand=. 9 ID=C3 C=5.6 pf ID=V ID=C1 C=1 nf ID=V3 1 ID=C4 C=1 nf ACITORS 6 W=.54 mm 4 ID=C6 C=1 uf ID=V4 DRAIN BIAS 5 7 W=.54 mm L=.99 mm 13 8 W=3 mm L=5 mm 14 Gate DC bias voltage matching network ( Path) matching network (detail) Z=5 Ohm ID=TL8 L=.8 mm ID=C C=5.6 pf L=8 mm ID=TL3 W1=1 mm W=1.88 mm P= Z=5 Ohm Z=5 Ohm ID=TL8 ID=C L=.8 mm C=5.6 pf L=8 mm ID=TL3 W1=1 mm W=1.88 mm P= Z=5 Ohm L=.8 mm Gate DC bias voltage H=.818 mm T=.3556 mm Rho=1. Tand=. 3 L=.8 mm 4 W1=1.156 mm W=.54 mm W=.54 mm L=1.8 mm ID=TL4 H=.818 mm T=.3556 mm Rho=1. Tand=. ID=C3 C=5.6 pf 9 15 REST OF BIAS CIRCUIT 16

5 matching network Z=5 Ohm ID=TL8 ID=C L=.8 mm C=5.6 pf L=8 mm ID=TL3 5 3 L=.8 mm 4 W1=1.156 mm W=.54 mm W1=1 mm W=1.88 mm P= Z=5 Ohm H=.818 mm T=.3556 mm Rho=1. Tand=. ID=TL4 W1=1 mm W=1 mm W=1 mm Z=5 Ohm L=5 mm ID=TL8 W=.58 mm L=13.4 mm W=1 mm L=8.85 mm ID=TL9 W1=1 mm ID=TL3 W=3 mm W=3 mm L=5.7 mm 3 ID=C1 C=.5 pf ID=C3 C=5.6 pf L=.88 mm P= Z=5 Ohm matching network W=.54 mm L=1.8 mm ID=TL4 ID=C3 C=5.6 pf 9 ID=TL7 W=.58 mm 3 ID=C C=1 nf 4 L=1.5 m ID=V ID=TL7 W=.54 mm ID=TL9 1 W=.54 mm 3 ID=C1 C=1 nf ID=C4 C=1 nf 1 ID=V ID=V3 6 9 W=.58 mm 7 4 ID=C4 C=1 nf ID=V3 6 W=.54 mm 4 ID=C6 C=1 uf ID=V4 W=.58 mm 8 5 ID=C6 C=1 uf 6 ID=V4 5 7 W=.54 mm L=.99 mm 1 W=.58 mm 8 W=3 mm L=5 mm Gate DC bias voltage 17 W=3 mm L=6.6 mm Drain DC bias voltage 5 V H=.818 mm T=.3556 mm Rho=1. Tand=. 18 topology Final bias voltages are shown. Design 1 Z = 5 1 Matching Network M Transistor 1 M 1 Matching Network Z = 5 Gate bias 119 A _ 5 V 1 ma Drain bias Linear Class AB amplifier loadline: I D DC loadline AC loadline Index: CS_Amp5C Presentation copyright Michael Steer 19 Quiescent point V DS

6 Load pull system Signal source Load pull points amplfiier Automated tuner Z in sensor meter Instrument controller Spectrum analyzer meter Signal source amplfiier Automated tuner Active device Impedance transformer Automated tuner High sensor power attenuator 1 load pull contour of P OUT At 3.5 GHz showing the reflection coefficient (here S 11 ) looking into the output matching network and the contours of constant output power. P OUT,MAX = 4.6 dbm. power for the first contour surrounding P OUT,MAX is 4.5 dbm and the powers of the contours reduce in.5 dbm steps. S 11 of the final output matching network design is shown from S 11 P OUT,MAX 3 power and gain at 3.5 GHz Gain (db) or power (dbm) 5 4 P OUT 3 Gain power (dbm) 4

7 power, gain, and drain efficiency at 3.4, 3.5, 3.6, 3.7, and 3.8 GHz Gain (db) and power (dbm) P OUT Drain efficiency Gain power (dbm) 5% 4% 3% % 1% Drain efficiency Two tone input f 1 and f (dbm) dbm f dbm f dbm f dbm f 1.8 dbm 11.5 dbm f 3 f 4 5 Tones at 3.5 GHz and 3.51 GHz each 3 dbm. -1. dbm f Frequency (GHz) 6 Response to a two tone input signal power (dbm) Fundamental 1:1 IM3U 3: power (dbm) tones are at 3.5 GHz and 3.51 GHz Fundamental plotted is at 3.51 GHz. 7 Summary Transistor vendors strive to offer transistors for high volume applications that simplify design effort. A few standard topologies are used. For high power amplifier design harmonic balance analysis is used. High dynamic range is not available with transient simulators. Load pull analysis used in simulation and also when adjusting final amplifier design. 8