5.8 GHz Single-Balanced Hybrid Mixer

Transcription

1 Single-Balanced Hybrid Mixer James McKnight MMIC Design EE JHU Fall 200 Professor John Penn

2 Abstract This report details the design of a C-Band monolithic microwave integrated circuit (MMIC) single-balanced mixer. The mixer was designed for a radio frequency (RF) input range of GHz and local oscillator (LO) design frequencies from (LSLO) or GHz (HSLO), for a resultant down-converted intermediate frequency (IF) of 00 MHz. This standard mixer topology is constructed on a 4-port 90 hybrid mixer and two Field Effect Transistors (FETs) configured as diodes. The design simulations showed conversion loss <0dB, return loss >0dB and RF-LO isolation >0dB over the entire band of interest. For this performance, however, a large LO drive-level of +0dBm was required. All simulations are based on the Triquint model library parts process and fitting within a 60mil x 60mil Anachip layout.

3 Introduction RF mixers are 3-port active or passive devices which are designed to yield both sum and differences of input signals. Often referred to as frequency translation devices, mixers are most commonly used to convert one frequency to another for ease of transmission or signal processing. In order to produce new frequencies (combinations or RF and LO), mixers require nonlinear devices. The single-balanced mixer employs two diodes whose effects are combined through a hybrid coupler junction (Figure ). The hybrid network also allows the RF and LO to feed the device while maintaining relatively strong RF-LO isolation. Figure - Balanced mixers topologies (Pozar) The RF input frequencies range from GHz and the LO frequencies range from GHz. The design targeted a maximum LO power of +5dBm, yet simulations showed a functional design at +0dBm. Simulations demonstrate conversion loss approximately 9dB. Each segment of the device, its design and performance is elucidated in subsequent sections.

4 2 Design Approach Mixers are an important component in the RF chain for an array of communication systems (i.e. superheterodyne receivers), and, as such, require certain specifications to properly function in concert with other RF components. Outlined in Table are a list of basic mixer specifications. Table : Balanced hybrid mixer design requirements Mixer Property Minimum Requirement Goal RF Frequency GHz GHz LO Frequency GHz GHz IF Frequency 00 MHz 00 MHz RF Power < 0dBm <-5dBm LO Power <5 dbm 5-0 dbm Conversion Loss <5dB <0dB Supply Voltage 0-3V 0.7V RF and LO Return Loss >8dB >0dB The design process evolved piecewise, developing the coupler, FET diodes and LPF separately. Initial design began with ideal parts and subsequent iterations incorporated parasitic parts the device was tuned regularly to compensate for the parasitic effects. 90 Hybrid Coupler Design Central to the single-balanced mixer is the 90 hybrid coupler. The coupler design hinges entirely on the characteristic impedance and frequency of operation, chosen respectively to be 50Ω and. The Balanced mixers made with the 90 hybrid coupler will, in theory, have a better input match over a wide bandwidth relative to those using the rat-race coupler. With the hybrid coupler, either the LO drive or the RF signal is balanced (applied in anti-phase), adding destructively at the IF port of the mixer and providing inherent rejection. The level of rejection is dependent on the amplitude and phase balance of the coupler. Figure 2 Distributed Hybrid Coupler

5 A basic hybrid coupler made of distributed lines is shown in Figure 2. To conserve chip space and for ease of use, a lumped-element equivalent circuit can be used in its place. The coupler was designed with the equations below and simulated with both ideal and parasitic Triquint parts. ID=L2 L=0.97 nh PORT P= L=.372 Z=50 nhport Ohm ID=C3 CAP P=4 L=0.97 nh C=.325 pf ID=CCAP C=.325 ID=C4 pf C=.325 pf P C+C2 C+C2 P2 L2 L4 L23 P4 L34 P3 C+C2 C+C2 Figure 3 Lumped Hybrid Coupler with, Z 0 = 50Ω

6 [db] [db] ID=V2 W=3.543 mil L=3.543 mil PORT P= ID=C4 C=C pf W= mil ID=L4 N=2 ID=C3 C=C pf W= mil PORT P=2 ID=L3 N=2 ID=L2 N=2 PORT P=4 ID=C C=C pf W= mil ID=L N=2 ID=C2 C=C pf W= mil PORT P=3 C=.325 Figure 4 - Hybrid Coupler Schematic w/ Triquint parts 0 0 Triquint Hybrid Coupler db db db DB( S(,) ) DB( S(2,) ) DB( S(3,) ) DB( S(4,) ) DB( S(,) ) DB( S(2,) ) DB( S(3,) ) DB( S(4,) ) Figure 5-90 Hybrid Coupler S-parameters (Mag.)

7 [ma] [deg] [deg] 200 Phase 200 Triquint Hybrid Coupler Phase 6.5 Deg Deg Deg Deg Ang(S(,)) (Deg) Ang(S(2,)) (Deg) Ang(S(3,)) (Deg) Ang(S(4,)) (Deg) Deg Ang(S(,)) (Deg) Ang(S(2,)) (Deg) Ang(S(3,)) (Deg) Ang(S(4,)) (Deg) Figure 6-90 Hybrid Coupler S-parameters (Phs.) FET Diodes The simple P-N junction of a diode can be created by shorting together the drain and source terminals of a FET. For this design, two Triquint, D-mode, PHEMT FETs are used. IVCURVE ID=IV VSWEEP_start=0 V VSWEEP_stop=0 V VSWEEP_step=0. V VSTEP_start=-0.8 V VSTEP_stop=0.6 V VSTEP_step=0.2 V Swp Step Figure 7 - Triquint FET operating as a diode 5.68 ma 0 V ma -0.8 V 2.84 ma TQPED_PHSS_T3i ID=PHSSi2 W=50 NG=6 TQPED_PHSS_T3_MB=PHSS_T Diode FET Biasing V.994 ma.5 2 Voltage (V) Figure 8 - Diode curves showing +0.7V turn-on IVCurve() (ma) Power sweep p: Vstep = -0.8 V p2: Vstep = -0.6 V p3: Vstep = -0.4 V p4: Vstep = -0.2 V p5: Vstep = 0 V p6: Vstep = 0.2 V p7: Vstep = 0.4 V p8: Vstep = 0.6 V Figures 2 and 3 demonstrate the true diode-like behavior of the Triquint FETs. For the case where Vstep (applied to the cathode ) is 0V, the device is shown to be forward conducting when +0.7VDC is applied to the anode, the nominal diode turn-on voltage.

8 Mixer Design When driven properly, the nonlinear devices create a wide variety of harmonics which are pivotal to strong intermodulation products and low conversion loss. However, a common disadvantage of balanced mixers is their greater LO power requirements. To tease out that problem upfront, the complete coupler was built entirely of ideal blocks, but with Triquint FETs. Conversion loss was observed for three diode FETs while sweeping LO power from 0-25dBm - each of the three FETs have a different number of gate fingers. The plots below depict how reducing the number of gates fingers (while maintaining the same gate width), can drastically reduce the LO power needed to drive the diodes for low conversion loss. Figure 9 Conversion Loss vs. LO sweep to determine number of FET gates Added biasing Figure 0 Conversion Loss vs. LO sweep w/ DC bias

9 Return Loss (db) Additionally, a simple 0.7V bias circuit is applied to one of the diodes can bring up the conversion loss by ~25dB for all LO input power levels. Still, the conversion loss is unacceptably low at > 20dB. Trade-offs A main focus of this work was to keep the design simple while fully functional. There were many niceties which may have been included for performance increases, but may not have been worth their space on the limited chip size. Reducing the number of gates greatly improved the LO drive level needed, but altering gate width offered up its own trade-offs. A wider gate had lower conversion loss, but only at higher LO power levels. Conversely, a narrower gate was driven better with lower LO power, but had ~5dB more CL. The DC bias only marginally improved the LO power needed for low conversion loss, but was included in the end. 3 Simulations 0 Mixer Return Losses LO Return Loss, db RF Return Loss, db Figure Return Loss vs. LO sweep w/ DC bias

10 Output Level (dbm) (dbm) 0-5 Isolation (dbm) (dbm) Figure 2 Mixer Isolation GHz dbm harmonics 5.7 GHz dbm -2.3 dbm GHz dbm DB( Pharm(PORT_2) )[,] (dbm) Mixer Final.AP_HB.$F_SPEC Figure 3 RF Spectrum

11 [db] -9 Conversion Loss vs Freq DB( LSSnm(PORT_2,PORT_,_-,_0) ) Mixer Final.AP_HB Figure 4 Conversion Loss over frequency CL vs LO Power -8 p DB( LSSnm(PORT_2,PORT_,-_,_0) )[,X] Mixer Final.$F_SPEC Power (dbm) Figure 5 Conversion Loss vs. LO drive p: FREQ = 5.8 GH

12 4 Schematic RF Schematic ID=V4 W=3.543 mil L=3.543 mil RF PORT P= Pwr=-5 dbm ID=P2 ID=C3 C=5 pf W=3.937 mil ID=C6 C=C pf W=.575 mil ID=L4 N=2 ID=C5 C=C pf W=.575 mil TQPED_PHSS_T3i ID=PHSSi2 W=50 NG=2 TQPED_PHSS_T3_MB=PHSS_T3 2 ID=P ID=V W=3.543 mil L=3.543 mil 3 LO PORTFNS P=3 Freq=5.9 GHz PStart=0 dbm PStop=5 dbm PStep= db Tone=2 ID=L3 N=2 ID=C4 C=5 pf ID=C W=3.937 mil C=C pf W=.575 mil ID=L N=2 ID=L2 N=2 ID=C2 C=C pf W=.575 mil 3 2 ID=C8 C=2 pf W=.969 mil TQPED_PHSS_T3i ID=PHSSi W=50 NG=2 TQPED_PHSS_T3_MB=PHSS_T3 DCVSS ID=V3 VStart=0 V VStop= V VStep=0. V ID=P0 DCVS ID=V7 V=0.7 V ID=P W=8.5 W2=4.5 C=.325 ID=L9 N=3 ID=P7 ID=P6 ID=V5 W=3.543 mil L=3.543 mil ID=V2 W=3.543 mil L=3.543 mil ID=P5 ID=P3 ID=P9 width_out=6 nturns_out=0 PORT P=2 width=4 nturns=8 C_out=0 IF ID=C7 C=2 pf W=.969 mil ID=V6 W=3.543 mil L=3.543 mil ID=P8 ID=P4 Figure 2 - RF Schematic for Hybrid Mixer

13 DC Schematic ID=V4 W= mil L= mil ID=C6 C=C pf W=.575 mil ID=L4 N=2 TQPED_PHSS_T3i ID=PHSSi2 W=50 NG=2 TQPED_PHSS_T3_MB=PHSS_T3 ID=C5 C=C pf W=.575 mil 2 ID=V W= mil L= mil 3 ID=L3 N=2 ID=L2 ID=L N=2 N=2 3 DCVSS ID=V3 VStart=0 V VStop= V VStep=0. V ID=C C=C pf W=.575 mil ID=C2 C=C pf W=.575 mil 2 TQPED_PHSS_T3i ID=PHSSi W=50 NG=2 TQPED_PHSS_T3_MB=PHSS_T3 Figure 3 - DC schematic for single-balanced hybrid Mixer

14 5 Layout Figure 4 - S-band single-balanced mixer layout

15 6 Test Plan DC Testing. Apply DC probe to the DC bias terminal 2. Apply power meter to IF port 3. Slowly increase V DC to+0.7v 4. Look for ~0.07V(as was simulated) Down Mixer Testing. Calibrate the network work analyzer for 5.2 to 6.0GHz 2. Connect a signal generator or VNA to the LO port for 5.7GHz 3. Set LO power to +0dBm 4. Connect a signal generator or VNA to the RF port for 5.8GHz 5. Set RF power to -5dBm 6. Connect a spectrum analyzer to the IF port 7. Apply +0.7VDC to the DC bias terminal 8. Measure the 00MHz IF output power at each frequency interval 7 Conclusions A C-band single-balanced mixer was designed and simulated to meet most design requirements. The device was capable of achieving <0dB of conversion loss from GHz and >0dB of return loss at f center. A DC voltage was shown to improve conversion loss for lower LO power levels, but not to an acceptable range. With plenty of room left on the chip, additional parts could be added for better impedance matching and higher-order filters(hpf for RF/LO and LPF for IF) for suppression of RF, LO and nearby mixing products.