Efficiency Improvement of WCDMA Base Station Transmitters using Class-F power amplifiers

Transcription

1 Efficiency Improvement of WCDMA Base Station Transmitters using Class-F power amplifiers Muthuswamy Venkataramani Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science In Electrical Engineering Dr. Charles W. Bostian, Chair Dr. Dennis G. Sweeney Dr. Sanjay Raman February 13, 2004 Blacksburg, Virginia Keywords: WCDMA, power amplifier, class-f, class-ab, linearity, harmonic balance, Intermodulation distortion, power added efficiency Copyright 2004, Muthuswamy Venkataramani

2 Efficiency Improvement of WCDMA Base Station Transmitters using Class-F power amplifiers Muthuswamy Venkataramani (ABSTRACT) Universal Mobile Telecommunications Systems (UMTS) is the preferred third generation (3G) communication standard for mobile communications and will provide worldwide coverage, a convenient software technology and very high data rate. The high data rate, especially, requires the use of bandwidth-efficient modulation schemes such as Quadrature Phase Shift Keying (QPSK). But modulation schemes such as QPSK need, in turn, a very linear power from the output of the transmitter power amplifier in order to meet the spectral requirements. A linear power amplifier, traditionally, has very low energy efficiency. Poor energy efficiency directly affects operational costs and causes thermal heating issues in base station transmitters. Thus the power amplifier designer is forced to trade-off between linearity and efficiency. As a result of this trade-off a Class- AB power amplifier is most often used in QPSK based systems. Class-AB power amplifiers provide acceptable linearity at efficiency values around 45-50% typically. This compromise is not a satisfactory solution but is inevitable while using traditional power amplifier design techniques. This thesis details the use of a Class-F amplifier with carefully chosen bias points and harmonic traps to overcome this problem. Class-F amplifiers are usually considered as very high efficiency (80% or more power-added efficiency) amplifiers where the high efficiency is obtained through the use of harmonic traps (L-C filters or quarterwavelength transmission lines), which provide suitable terminations (either open or short) for the harmonics generated. By doing this, a square wave drain voltage and a peaked half-sinusoidal drain current out-of-phase by 180º are produced. Since only a drain

3 voltage or a drain current exists at any given time, the power dissipation is ideally zero resulting in 100% theoretical efficiency. These very high efficiency values are usually associated with poor linearity. However the linearity can be improved to meet the design standards but compromising on efficiency. Even after this is done, efficiencies are usually 10 to 15% greater than a traditional Class AB power amplifier with similar linearity performance. Thus efficiency can be improved without affecting linearity by the use of Class-F power amplifiers. In order to verify this theory, a Class-AB and a Class-F power amplifier are designed using Motorola s high voltage laterally diffused metal oxide semiconductor (LDMOS) transistor. The choice of bias points and the design of the harmonic traps are very critical for the Class-F performance and hence were designed after careful consideration. The designs were simulated on Agilent s Advanced Design System (ADS) and the simulated results were compared for three different power levels namely, the peak power, 3 db below peak power and 6 db below peak power. At all of these power levels it was noted that the Class-F and Class-AB power amplifiers have very similar linearity performance whereas the Class-F power amplifiers show about 10% improvement in efficiency in comparison to the Class-AB power amplifiers.

4 To my advisor Dr. Charles Bostian

5 To my family Gulo, Venkataramani, Sandhya, Shiva, Sudhanva and Sudheep

6 Acknowledgment Working on this thesis was a very useful, important and memorable experience to me. I would like to thank all those people who made this thesis possible. First of all, I would like to thank Dr. Charles Bostian, my advisor at the Center for Wireless Telecommunications, Virginia Tech. The knowledge that I gained from his lectures and during personal discussions was invaluable. In addition to his roles as my thesis advisor and professor for radio engineering courses, he has been a very good friend, a father figure, who always had encouraging words for me. I also thank him for giving me various teaching assistantship positions that helped me fund my graduate studies and also served as a very useful experience. I am grateful to my thesis committee members, Dr. Sanjay Raman and Dr. Dennis Sweeney, for their insightful suggestions towards my thesis. I also thank them for their time spent reviewing my thesis. I would like to thank Motorola for providing design kits and technical support. I would especially like to thank Bob Keasler, David Shih and Cedric Cassan of Motorola for their support and suggestions. I would like to thank the staff of CWT, especially, Shelley Johnson, Judy Hood, Kathy McCloud and James Dunson for their help and support. Friends are a very important part of graduate life and I would like to thank my friends who have been with me through this. I would always relish the time spent with them. Finally I would like to thank my parents, my sister and brother-in-law for their constant support, love and prayers. I thank them for helping me pursue my academic goals.

7 Table of Contents 1 INTRODUCTION Background Problem Statement Thesis Outline Thesis Overview 3 2 RF POWER AMPLIFIER THEORY Introduction Power Output Capability Power Added Efficiency dB Compression Point Intermodulation Distortion Adjacent Channel Power Ratio Intercept Point AM-PM Conversion Power Amplifier Classification Class A Class B Class AB Class C Class E Class F Conclusion 18 3 CLASS F POWER AMPLIFIERS Introduction 19 vii

8 3.2 Background Basic Class F operation Third Harmonic Peaking Class F Power Amplifier Factors Affecting Class F Performance Conclusion 27 4 DESIGN AND IMPLEMENTATION Introduction Design Specification Bias Point Simulation Load Pull and Source Pull Design Architecture Input and Output Matching Harmonic Terminations Class F Implementation 34 5 RESULTS Introduction Bias Point Simulation Single-tone Simulation Two-tone Simulation Conclusions 50 6 SUMMARY AND CONCLUSION Summary Conclusion 6.3 Future Work References 53 Vita 55 viii

9 List of Figures dB Compression Point Intermodulation Distortion Plot of Adjacent Channel Power Plot showing Third Order Intercept Point Input Signal for Class A Biasing for Class A Input Signal for Class B Biasing for Class B Input Signal for Class AB Biasing for Class AB Single Transistor Class AB Configuration with Output Harmonic Filter Input Signal for Class C Biasing for Class C Typical Class E Waveforms Class F Design using Quarter-Wave Transmission Line at the Output Output Voltage when Fundamental and Third Harmonic Components are In-Phase Output Voltage when Fundamental and Third Harmonic Components are Out-of-Phase 3.4 Normalized Amplitudes of the Drain Current Harmonic Components at DC, f 0 and 3f 0 as a function of the Drain Current Conduction Angle ix

10 4.1 Plot of Transistor DC Transfer Characteristics at Vds = 26 V Load Pull Analysis to determine Load Impedance for Maximum Efficiency Load and Source Impedance for Maximum Efficiency Class F Power Amplifier Design Architecture Input and Output Matching Networks Schematic of the Class F Power Amplifier Design Schematic of the Class AB Design Class AB Drain Voltage Waveform Class AB Drain Current Waveform Class F Drain Voltage Waveform Class F Drain Current Waveform Class F: AM-PM Conversion (deg/db) Class F: Output Spectrum Class F: Zoomed Output Spectrum showing 3 rd, 5 th and 7 th Order IMD Products Class F: Plot of Third Order Intermodulation Products (dbc) Class AB: Plot of Third Order Intermodulation Products (dbc) Class F: Plot of Fifth Order Intermodulation Products (dbc) Class AB: Plot of Fifth Order Intermodulation Products (dbc) Class F: Plot of PAE (%) vs. Output Power (dbm) Class AB: Plot of PAE (%) vs. Output Power (dbm) Class F: Plot of Gain (db) vs. Output Power (dbm) Class AB: Plot of Gain (db) vs. Output Power (dbm) 48 x

11 List of Tables 4.1 Design Specifications for WCDMA power amplifier Class AB Bias Voltages Class F: Impedance at Third and Second harmonic frequency Class F: Harmonic levels at the output Class AB: Harmonic levels at the output Comparison of Class F and Class AB PA Performance 49 xi

12 Chapter 1 Introduction 1.1 Background Universal Mobile Telecommunications Systems (UMTS) is the preferred third generation (3G) communication standard for mobile communications offering potential worldwide coverage and a convenient technology for software and applications developers [1], [2]. The radio technology proposed in UMTS is Wideband CDMA (WCDMA) and the planned frequency range of operation for UMTS is close to 2GHz. WCDMA uses a bandwidth that is four times wider (5 MHz bandwidth) than the conventional CDMA systems that are typically used in second generation networks in North America. UMTS utilizes a bandwidth-efficient modulation, namely the Quadrature Phase Shift Keying (QPSK) modulation, and therefore is capable of providing higher bit rates per unit of bandwidth. Typically UMTS systems are expected to deliver peak data rates of up to 2.4 Mbps with average data rates of 300 kbps when the user is walking or driving [1]. The data rate increases further when the user is stationary. UMTS is designed to deliver 1

13 services which require high bandwidth such as streaming multimedia, large file transfers and video-conferencing. High data rates, however, demand a linear power amplifier output from the transmitter to conform to transmitted spectrum requirements. A highly linear power amplifier, in turn, has very poor energy efficiency, forcing the power amplifier designer to trade-off between linearity and efficiency. 1.2 Problem The power amplifiers for existing second generation GSM (Global System for Mobile Communications) transmitters are highly efficient, typically providing efficiencies of 50% or more. However these transmitter designs cannot be applied to UMTS/WCDMA. This is because GSM uses the constant envelope feature of GMSK (Gaussian Minimum Shift Keying) modulation which introduces phase variations only. UMTS on the other hand must maximize spectral efficiency in order to accommodate higher data rate services. A WCDMA system with QPSK modulation is used in UMTS systems to obtain spectral efficiency. In these systems both phase and amplitude variations are introduced by the modulation. The amplitude variation requires a linear output from the transmitter. A conventional linear power amplifier, such as a Class A amplifier, has a very low efficiency (typically 10-35%). This is unacceptable for most applications since efficiency is a major issue directly affecting power consumption, cost, reliability, size of transmitter and talk time. The power amplifiers are thus challenged to amplify complex modulated signals without distortion and at minimum dc power consumption. High linearity and high efficiency thus become contradicting requirements for the power amplifier of a WCMDA system. 1.3 Thesis Outline A reasonable compromise between linearity and efficiency can be achieved by using a Class AB power amplifier wherein fairly linear amplification can be achieved with an 2

14 efficiency of around 45%. However, keeping in mind the advantages of a high efficiency amplifier, many techniques have been proposed to achieve higher efficiencies (50% or more) without additional distortion. In this thesis a Class F power amplifier design is proposed to achieve higher efficiency in comparison to a Class AB power amplifier for a WCDMA based system without compromising linearity. The amplifier will be designed using Motorola s LDMOS transistor model in Agilent s Advanced Design System (ADS) software to operate over the frequency band ranging from 2.11 GHz to 2.17 GHz. Several important parameters such as power added efficiency, dc power consumption, third order intermodulation distortion, AM-PM conversion and third order input intercept point will be examined to assess the efficiency and linearity performance of the power amplifier. 1.4 Thesis Overview Chapter 2 discusses the theoretical concepts behind power amplifier design and the various classes of RF power amplifiers. Chapter 3 explains the operation of a Class F power amplifier and details the underlying design concepts. Chapter 4 describes the actual design of the Class F power amplifier based on simulations using Agilent s ADS. Internal matching of the die model using Motorola s HVIC components is also explained. Chapter 5 presents the simulated results and enables a comparative study between the performance of a Class AB and Class F power amplifier. Chapter 6 summarizes the thesis by providing conclusions and also suggestions to build on this work. 3

15 Chapter 2 RF Power Amplifier Theory 2.1 Introduction The RF power amplifier (PA), a critical element in transmitter units of communication systems, is expected to provide a suitable output power at a very good gain with high efficiency and linearity. The output power from a PA must be sufficient for reliable transmission. High gain reduces the number of amplifier stages required to deliver the desired output power and hence reduces the size and manufacturing cost. High efficiency improves thermal management, battery lifetime and operational costs. Good linearity is necessary for bandwidth efficient modulation. However these are contrasting requirements and a typical power amplifier design would require a certain level of compromise. There are several types of power amplifiers which differ from each other in terms of linearity, output power or efficiency. This thesis will present a Class F PA design and discuss its performance in comparison to a traditional Class AB amplifier. Parameters which quantify the various aspects of amplifier performance such as 1-dB compression point, input intercept point, intermodulation distortion, power output 4

16 capability, power added efficiency and adjacent channel power ratio are discussed in this chapter. In addition the Class AB power amplifier operation is discussed in detail. 2.2 Power Output Capability (C p ) The power output capability, C p, is defined as the RF output power produced when the device has a peak drain voltage of 1 volt and a peak drain current of 1 ampere [3]. This is a unit less quantity. If the power amplifier uses two or more transistors, then the number of transistors is included in the denominator. If P 0 is the RF output power, I d, pk is the peak drain current, V d, pk is the peak drain voltage and N is the number of transistors, then P 0 C p = (2.1) NI d,pkvd,pk Usually the power output capability of a Class A amplifier is the highest since it is operated at the center of the load line allowing room for maximum voltage and current swings. Based on this, another parameter called the power utilization factor (PUF) is defined as the ratio of RF power delivered by a device in a particular mode to the power delivered by operating the device as a Class A amplifier. 2.3 Power Added Efficiency (PAE) Efficiency or drain efficiency is simply defined as the ratio of output power at the drain to the input power supplied to the drain by the dc supply. P 0 η d = (2.2) Pdc 5

17 Drain efficiency is usually not enough to characterize RF power amplifier performance. This is due to the substantial RF power at the input of the amplifier, especially in amplifiers with low gain. Power added efficiency (PAE) includes the effect of input drive power and is defined as: PAE P Pdrive 0 = (2.3) P dc dB compression point (P 1-dB ) When a power amplifier is operated in its linear region, the gain is a constant for a given frequency. However when the input signal power is increased, there is a certain point beyond which the gain is seen to decrease. The input 1-dB compression point is defined as the power level for which the input signal is amplified 1 db less than the linear gain. The 1-dB compression point can be input or output referred and is measured in terms of dbm. A rapid decrease in gain will be experienced after the 1-dB compression point is reached. This gain compression is due to the non-linear behavior of the device and hence the 1-dB compression point is a measure of the linear range of operation. 6

18 Linear P 1-dB, out 1 db Output Power in dbm Compressed P 1-dB, in Input Power in dbm Fig dB compression point 2.5 Intermodulation Distortion (IMD) Intermodulation distortion is a nonlinear distortion characterized by the appearance, in the output of a device, of frequencies that are linear combinations of the fundamental frequencies and all harmonics present in the input signals [4]. A very common procedure to measure the intermodulation distortion is by means of a two-tone test. In a two-tone test a nonlinear circuit is excited with two closely spaced input sinusoids. This would result in an output spectrum consisting of various intermodulation products in addition to the amplified version of the two fundamental tones and their harmonics. If f 1 and f 2 are the fundamental frequencies then the intermodulation products are seen at frequencies given by f IMD = mf 1 ± nf 2 where m and n are integers from 1 to. 7

19 The ratio of power in the intermodulation product to the power in one of the fundamental tones is used to quantify intermodulation. Of all the possible intermodulation products usually the third order intermodulation products (at frequencies 2f 1 -f 2 and 2f 2 -f 1 ) are typically the most critical as they have the highest strength. Furthermore they often fall in the receiver pass band making it difficult to filter them out. Third Order Intermodulation ` Second Order Intermodulation Amplitude 5 th 5 th 7 th 7 th f2-f1 2f1-f2 f1 f2 2f2-f1 f1+f2 Frequency Fig 2.2 Intermodulation Distortion 2.6 Adjacent Channel Power Ratio (ACPR) In many modern communication systems, the RF signal typically has a modulation band that fills a prescribed bandwidth on either side of the carrier frequency. Similarly the intermodulation products also have a bandwidth associated with them. The IM bandwidth is three times the original modulation band limits for third order products, five times the band limits for fifth order products and so on. Thus the frequency band of the intermodulation products from the two tones stretches out, leading to leakage of power in the adjacent channel. This leakage power is referred to as adjacent channel power. The adjacent channel power ratio (ACPR) is the ratio of power in the adjacent channel to the power in the main channel. ACPR values are widely used in the design of power 8

20 amplifiers to quantify the effects of intermodulation distortion and hence also serve as a measure of linearity. ACPR, dbc Fig 2.3 Plot of Adjacent Channel Power 2.7 Intercept Point (IP) The intercept point is the point where the slope of the fundamental linear component meets the slope of the intermodulation products on a logarithmic chart of output power versus input power. Intercept point can be input or output referred. Input intercept point represents the input power level for which the fundamental and the intermodulation products have equal amplitude at the output of a nonlinear circuit. In most practical circuits, intermodulation products will never be equal to the fundamental linear term because both amplitudes will compress before reaching this point. In those cases intercept point is measured by a linear extrapolation of the output characteristics for small input amplitudes. Since the third order intermodulation products, among the IM products, are of greatest concern in power amplifier design, the corresponding intercept point called the third order intercept point (IP3) is an important tool to analyze the effects of third order nonlinearities. In fact intercept point serves as a better measure of linearity in 9

21 comparison to intermodulation products as it can be specified independent of the input power level [4]. OIP3 Third Order Intercept Point Output Power (dbm) Fundamental Response 1:1 Third Order Response 3:1 Input Power (dbm) IIP3 Fig 2.4 Plot showing Third Order Intercept Point 2.8 Amplitude Modulation to Phase Modulation (AM-PM) Conversion: An amplifier driven under strongly nonlinear conditions produces phase distortion in addition to amplitude distortion. The phase distortion is a serious problem in systems with phase modulation such as QPSK. This phase distortion is characterized by AM-PM conversion which is defined as the change in phase of the output signal when the drive level at the input is increased toward and beyond the compression point. The AM-PM effects are usually caused by the storage elements in the circuit like the gate-source junction capacitances and parasitics associated with inductors under nonlinear conditions. 10

22 2.9 Power Amplifier Classification There are several types of power amplifiers and they differ from each other in terms of their linearity, efficiency and power output capability. The first step in designing a power amplifier is to understand the most important design factor and choose the power amplifier type most suited for that purpose. For example, communication systems which require good linearity often use Class A or Class AB architecture whereas those which require good efficiency use a Class C, E or F type power amplifier. In addition there are power amplifier types which satisfy special needs such as a Doherty amplifier which provides high efficiency at backed-off power levels or a Chireix amplifier which gives linear performance using nonlinear components. Class AB power amplifier provides a reasonable trade-off between linearity and efficiency and is the popular power amplifier type for WCDMA applications. In this section the Class AB power amplifier is detailed and other basic power amplifier types are briefly discussed. These discussions based on MOS transistor viewpoint Class A: Class A is the simplest power amplifier type in terms of design and construction. The Class A amplifier has a conduction angle of 2π radians or 360. Conduction angle refers to the time period for which a device is conducting. Thus a conduction angle of 360º tells us that in Class A operation the device conducts current for the entire input cycle. Class A amplifiers are considered to be the most linear since the transistor is biased in the center of the load line to allow for maximum voltage and current swings without cut-off or saturation. However the problem with Class A amplifiers is their very poor efficiency. This is because the device is draining current at all times which translates to higher power loss. In fact it can be shown that the maximum efficiency achievable from a Class A power amplifier is only 50% [5]. However this is a theoretical number and the actual efficiency is typically much less. In fact commercial Class A amplifiers have efficiency as low as 20%. Hence Class A amplifiers are usually used only in places where linearity 11

23 is a stringent requirement and where efficiency can be compromised as in the initial stages of a multi-stage power amplifier. Input Voltage V V Threshold I D Class A bias Time V Threshold V GS Fig 2.5 Input signal for Class A Fig 2.6 Biasing for Class A Class B: The next class of power amplifiers is Class B. The transistor is biased at the threshold voltage point of the transistor for Class B operation. Hence there is a current flowing at the output of the device only when there is a signal at the input. Moreover the device would conduct current only when the input signal level is greater than the threshold voltage. This occurs for the positive half cycle of the input signal and during the negative half cycle the device remains turned off. Hence the conduction angle for Class B operation is 180º or π radians. Due to this behavior; there is a large saving in the power loss. It can be shown that the maximum theoretical efficiency achievable with Class B operation is about 78.5% [5]. Commercial Class B amplifiers typically have an efficiency of 50-60%. However, the increased efficiency comes at the cost of reduced linearity. The reduction in the output power occurs because the output current flows for only one half cycle of the input signal. The poor linearity is primarily attributed to an effect called the crossover distortion [5]. Whenever the transistor is turned on (at the start of positive half 12

24 cycle) and turned off (at the start of negative half cycle) the transistor does not change abruptly from one state to the other. Instead the transition is gradual and nonlinear, and results in an offset voltage. This voltage alters the output waveform (crossover distortion) thereby reducing the linearity. Sometimes a Class B amplifier is realized in push-pull configuration. In this configuration the two transistors are driven 180º out-of-phase so that each transistor is conducting for one half cycle of the input signal and turned off for the other half cycle. Input Voltage V V Threshold I D Class B bias Time V Threshold V GS Fig 2.7 Input signal for Class B Fig 2.8 Biasing for Class B Class AB: The crossover distortion effect in Class B amplifiers can be minimized by biasing the gate in such a way so as to produce a small quiescent drain current. This leads to the type of amplifiers called Class AB, where the transistor is biased above the threshold voltage but below the center of the load line. Class AB amplifier operation, as the name suggests, can be considered to be a compromise between Class A and Class B operation. The conduction angle of a Class AB amplifier lies between 180º and 360º. By varying the conduction angle the amplifier can be made to behave more as a Class A or Class B amplifier. Hence the theoretical maximum efficiency of a Class AB amplifier is between 13

25 50% and 78.5%. But commercial Class AB amplifiers typically have much lower efficiency in the order of 40-55%. Thus a trade-off between linearity and efficiency can be achieved by simply changing the gate bias. Class AB amplifiers can also be realized in push-pull configurations even though single transistor configuration is preferred for high frequency linear operation. Input Voltage V V Threshold I D Class AB bias Time V Threshold V GS Fig 2.9 Input signal for Class AB Fig 2.10 Bias for Class AB A practical implementation of a single transistor Class AB is shown in Figure In addition to the matching networks and the bias networks, a parallel filter tuned to the fundamental frequency is often used. This filter presents the load impedance to the fundamental component of the output signal and presents a short circuit to all other frequencies. Thus harmonics are shunted to ground, preventing them from reaching the load. 14

26 V DD V GG OMN 50 Ω IMN L 0 C 0 RF f 0 Fig 2.11 Single transistor Class AB configuration with output harmonic filter Class C: A Class C power amplifier is a non-linear power amplifier used in places where linearity is not a requirement and high efficiency is highly desired. Class C amplifiers are widely used in constant envelope modulation systems where linearity is not required. The transistor is biased below threshold for Class C operation and hence the device conduction angle varies from 0º to 180º. When a voltage signal is applied to the input, the transistor conducts only for the period of time when the input signal is greater than the threshold voltage. The transistor remains switched off at all other times. Since only a portion of the positive input voltage swing takes the device into the amplifying region the output current is a pulsed representation of the input. Due to this pulsed output current the input and output voltages are not linearly related. Thus the amplitude of the power amplifier output is highly distorted. The efficiency of a Class C amplifier depends on the conduction angle. The efficiency increases for decreasing conduction angle. The maximum theoretical efficiency of a Class C power amplifier is 100%. However this is obtainable only for a conduction angle of 0º which means that no signal is applied and 15

27 this condition is of no interest. Commercially Class C amplifiers typically show an efficiency of 60% or more. Input Voltage V V Threshold I D Class C bias Time Fig 2.12 Input signal for Class C V Threshold V GS Fig 2.13 Bias for Class C Class E: Class E power amplifiers are fundamentally different from the other types of power amplifiers discussed before. In the previously described power amplifier classes, it was seen that the operational differences were obtained by the selection of the bias point. However, in a Class E amplifier, only circuit-independent signal guidelines are given (discussed below), and the topology is not as restricted. The idea behind the Class E amplifier is to have non-overlapping output voltage and output current waveforms, and to limit the values of the voltage, current, and the derivative of the voltage with respect to time at the instants when the transition between non-zero currents and non-zero voltages occurs [6]. In [7], the first published work on Class E amplifiers; the important conditions for Class E operation are listed. These conditions are based on the assumption that the transistor acts like a switch for Class E operation. Also the terms on state and off state are used to describe the time period when the transistor starts conducting and stops conducting respectively. The voltage across the switch must return to zero just before the switch turns on and starts conducting current. Similarly the current through the switch 16

28 must return to zero just before the switch turns off. These two conditions avoid the energy dissipation caused by the simultaneous superposition of substantial voltage and current on the switching transistor during transition from on to off state or off to on state. Another condition for Class E operation is that the voltage across the switch must return to zero with zero slope (i.e., dv/dt = 0). Hence the current through the transistor at the beginning of on state is zero. Similarly the current through the transistor must return to zero with zero slope (i.e., di/dt = 0) and the voltage across the transistor at the beginning of off state is zero. Hence for a deviation in the switching instant from the ideal switching time the corresponding output voltage or current will be very small, and the power lost in the device due to this non-ideality will be relatively small [7]. With all these conditions satisfied, very high efficiencies can be achieved. However it is quite difficult to meet all these requirements in practice. The maximum theoretical efficiency of Class E amplifiers is 100% [3], however efficiency values around 60% are typically achieved. V in V D I D V out Time Time Time Time Fig 2.14 Typical Class E Waveforms Class F: Class-F amplifiers are usually considered as very high efficiency (80% or more poweradded efficiency) amplifiers where the high efficiency is obtained through the use of 17

29 harmonic traps (L-C filters or quarter-wavelength transmission lines) which provide suitable terminations (either open or short) for the harmonics generated. By doing this, a square wave drain voltage and a peaked half-sinusoidal drain current out-of-phase by 180º are produced. Since only a drain voltage or a drain current exists at any given time, the power dissipation is ideally zero resulting in 100% theoretical efficiency. These very high efficiency values are usually associated with poor linearity. However the linearity can be improved to meet the design standards but compromising on efficiency Conclusion The important concepts associated with power amplifier design were explained in this chapter. In addition some of the common power amplifier types, used widely commercially, were discussed. The Class F amplifier is described in detail in the next chapter. As mentioned before there are other types of power amplifiers such as the Class D, Class S, Doherty and Chireix Outphasing amplifier that were not discussed here. For a detailed study of the various amplifier classes it is recommended that the reader reviews [4]. 18

30 Chapter 3 Class F Power Amplifiers 3.1 Introduction Class F power amplifiers provide major improvement in power added efficiency, output power and gain by loading the device output with appropriate terminations at fundamental and harmonic frequencies. The idea of using harmonic terminations to improve efficiency was first introduced in 1950s [8]. Basically, an amplifier can be made to operate in Class F mode by providing to the device output open-circuit terminations at the odd harmonic frequencies and short-circuit terminations at the even harmonic frequencies of the fundamental component. The resulting ideal drain voltage waveform is a square wave and the ideal drain current is a truncated sinusoid. This results in the reduction of harmonic power since there is no flow of output current for high drain voltage and there is maximum current flow when the drain voltage waveform is at its minimum. Based on this idea, significant research has been done to determine the various factors that affect Class F performance and also the harmonic terminations required for optimum behavior. Snider [9] focused on the optimally loaded and overdriven power amplifier to derive the correct harmonic terminations under ideal conditions. Raab [10] theoretically derived the maximum output power and efficiency that can be achieved using third-harmonic and 19

31 fifth-harmonic output peaking. This is especially useful to make a trade-off between efficiency and circuit complexity. Colantonio et al. [11], [12] have derived the importance of harmonic-generating mechanisms and harmonic manipulations for optimizing Class F performance. In this section, Class F operation, the necessary background for designing Class F amplifiers and the various factors affecting Class F performance will be discussed in detail. 3.2 Background Poor energy efficiency directly affects operational costs and causes thermal heating issues in base station transmitters. To attain high efficiency, the transistor of a Class F amplifier must operate as a closed switch for half the time period and as an open switch for the rest half of the time period. By doing so, the drain voltage will be zero when the transistor is conducting current as a closed switch, and the drain current will be zero when the transistor acts as an open switch holding considerable voltage across it. Thus at any given instant, either the voltage or current at the drain is zero and hence no power is lost in the device. 3.3 Basic Class F operation λ/4 i d R 0 Input L 0 C 0 RL Fig 3.1 Class F design using quarter-wave transmission line at the output 20

32 Fig 3.1 shows a simple Class F design using a quarter-wave transmission line as discussed in [13]. The load resistor R L is shunted by a parallel tank circuit that has infinite impedance at the fundamental frequency and zero impedance at all harmonics. Thus the impedance presented to the drain by the transmission line varies with frequency. At the fundamental frequency, the input impedance of the quarter-wave transmission line of characteristic impedance R 0 is: 2 R 0 R = (3.1) R L At even harmonics, the transmission line behaves as if it is half wavelength (or multiples of λ/2) long. Hence the short-circuit for even harmonics at the output is reproduced at the drain. At the odd harmonics, the transmission line behaves as if it is quarter wavelength (or multiples of λ/4) long and translates the short circuit at the output into an open circuit at the drain. The short circuit at even harmonics results in the presence of only the fundamental and odd harmonic voltages at the drain. The DC component of drain voltage, the fundamental voltage and the odd harmonic voltages add up at the drain to produce a square-wave drain voltage. Since the average voltage of the drain must be V DD if there is no DC drop in the RF choke, the square wave voltage swings between 0 and 2V DD. If the characteristic impedance of the transmission line (R 0 ) is assumed to be equal to R L, then R is also equal to R L. The fundamental-frequency component of the square-wave drain voltage then appears across the load: 4VDD vl(t) = sin ωt (3.2) π The load voltage lags the drain voltage by 90º because of the phase shift in the quarterwave transmission line. The fundamental-frequency current that flows in the load is just the load voltage divided by R: 21

33 i L 4VDD (t) = sin ωt (3.3) πr The odd harmonics in the drain-voltage waveform convert the sine wave into a squarewave, but, since they do not cause current to flow, they consume no power. The output power is produced entirely by the fundamental-frequency current and voltage and is found to be: 2 vli L 8VDD = = (3.4) 2 π R P0 2 When the transistor is off, the drain current must be zero. The RF choke passes only dc, so the fundamental-frequency current that flows through the load must also flow through the drain. Since the transmission line is an open circuit to odd harmonics, the drain current must be composed of a fundamental and even harmonics. Furthermore, because the transmission line acts as a short circuit to even harmonics, the drain can draw any amount of even-harmonic current necessary to meet other circuit requirements. This even-harmonic current results in a half-sinusoidal drain current whose peak amplitude is equal to the peak-to-peak amplitude of the output current: i DP 8VDD = (3.5) πr The even-harmonic currents circulate through the drain, transmission line, output network, but no power is consumed because they have zero voltage. 3.4 Third Harmonic Peaking Class F PA In order to reduce the circuit complexity, a class F amplifier is often used in a third harmonic peaking mode. Third harmonic peaking refers to a Class F amplifier with only a harmonic trap for the third harmonic vs. all odd harmonics. In this section the maximum 22

34 efficiency and power output capability of a Class F amplifier with third harmonic peaking is derived. It is possible to obtain a higher efficiency with a Class F third harmonic peaking amplifier than in Class B or C amplifiers [3] because the presence of the third harmonic in the collector voltage causes its waveform to flatten. However it should be noted that the third harmonic component should be added 180º out-of-phase with the fundamental to obtain the flattened voltage waveform. This has been shown in [11] and the results are reproduced in Figures 3.2 and 3.3. The in-phase and out-of-phase behavior can be seen clearly at w 0 t = -π, 0, π, 2π and so on. Fig 3.2 Output voltage when fundamental and third harmonic components are in-phase Fig 3.3 Output voltage when fundamental and third harmonic components are out-of-phase 23

35 The purpose of adding a third harmonic component to the drain voltage is to reduce the negative peak of the voltage waveform, while leaving the magnitude of the fundamental frequency component unaffected [11]. Hence the two voltage components must have opposite signs. Since the third harmonic voltage is obtained by loading the corresponding current component with a resistive termination, proper shaping can be obtained only if the third harmonic current component is negative. In [11] the behavior of the various current components as a function of the conduction angle has been presented. Those results are reproduced in Figure 3.4. Fig 3.4 Normalized amplitudes of the drain current harmonic components at DC, f 0 and 3f 0 as a function of the drain current conduction angle From this plot, we see that for proper Class F operation, the transistor must be biased as a Class A, AB or B amplifier. Biasing the transistor below the threshold as in Class C bias would lead to phase issues due to the positive third harmonic current. Usually the Class F transistor is biased in Class B mode as it gives a better efficiency than biased as Class A 24

36 or Class B due to the generation of large harmonics. However that would result in a poor linearity. Hence a Class AB bias point was chosen for this design. The maximum efficiency and the power output capability of a Class F amplifier for Class B bias is derived below. For Class AB bias, the maximum efficiency attainable will be less than this value whereas the power output capability will be more than the corresponding Class B value. The drain voltage which is the sum of a DC component, the fundamental voltage and the third harmonic voltage can be given as: v dc 0 3 dc 0 ( θ ) = V + V cosθ V cos3θ = V + V (cosθ x cosθ) (3.6) where x > 0 and is equal to V 3 /V 0 and θ = ωt dv( θ) The optimal value of x can be found by setting = 0 d( θ) is found to be 1/9. When x=1/9, the peak-to-peak voltage swing of v(θ) is (16/9)V 0. Since the maximum drain voltage swing is 2V dc, the maximum amplitude of the collector voltage is: V 0 = (9/8) V dc (3.7) Thus the peak output power is given by P V0 81Vdc Vdc = = (3.8) 2R 128R R 0 = The amplitude of the drain current I DM and the DC current I dc are given as I DM = V 0 /R = (9V dc /8R) (3.9) I dc = (2/π) I DM = (9V dc /4πR) (3.10) 25

37 Hence the maximum drain efficiency and power output capability are given by P0 P0 η = = = 88.36% (3.11) P V I dc dc dc C P0 = (3.12) 2V I p = dc DM We notice that the third harmonic peaking Class F amplifier gives roughly 27% higher output power, 10% higher drain efficiency and has 12% higher power output capability than a Class B amplifier. 3.5 Factors Affecting Class F Performance Harmonic generating mechanisms along with bias selection play an important role on the feasibility of the Class F scheme. The amplitude and phase of the harmonic drain currents relative to the fundamental currents should meet specific requirements in order to obtain optimum performance. In power amplifiers, at higher drive levels the drain voltage and current are not purely sinusoidal they exhibit a considerable harmonic content. A higher harmonic content is useful in getting a maximally flat voltage waveform at the expense of linearity. Harmonics are usually generated by clipping which is generally due to forward conduction of the gate-channel junction pinch-off of the conducting channel gate-drain junction breakdown Resistive losses of the device in triode region. The zero power loss condition in Class F amplifiers is an ideal condition that is never practically achievable. Only a transistor with zero saturation resistance (R ON ) can lead to 26

38 zero power loss. All practical transistors have a finite saturation resistance which results in power loss and hence reduces the efficiency. In simple terms the efficiency for the finite resistance case can be given as η = R R + 2R ) (3.13) F ( on The saturation resistance also decreases the maximum power output. The effect of the saturation resistance can be reduced by placing 2 transistors in parallel. But this would lower the output impedance as well leading to difficulties in output matching. Another way to reduce R ON is to set the value of R greater than the resistance R max at which maximum power occurs [13]. This improves the efficiency but reduces the output power. A higher value of V dd may also result in a better efficiency but the transistor breakdown voltage would set a limit on this value. 3.6 Conclusion This chapter presented the necessary background on Class F amplifier operation and explained the critical parameters that affect its design. Based on this knowledge, a Class F amplifier design for WCDMA specifications will be discussed in the next chapter. 27

39 Chapter 4 Design and Implementation 4.1 Introduction The basic operating principle of a Class F power amplifier and the factors that aid or affect the Class F performance were explained earlier. A Class F power amplifier design that meets the WCDMA specifications is described in this section. The Class F amplifier was designed using Motorola s LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor models and its performance was simulated using ADS. Various procedures involved in the design of the Class F amplifier such as DC simulation, bias point selection, source-pull and load-pull characterization, input and output matching circuit design and the design of suitable harmonic traps are explained. 4.2 Design Specifications As mentioned earlier, WCDMA requires high linearity to provide bandwidth efficiency. The Class F amplifier was designed to operate in the WCDMA band ( GHz) and was expected to meet the set of specifications listed in Table

40 Operational center frequency Output power PAE at maximum output power (should be higher than similarly biased Class AB) PAE at 6 db back-off from maximum output power Third order intermodulation products at maximum output power (should be comparable to similarly biased Class AB) Third order intermodulation products at 6 db back-off from maximum output power (should be comparable to similarly biased Class AB) 2.14 GHz 4 W (36 dbm) 50% or better 20% or better -20 dbc -30 dbc Table 4.1 Design Specifications for WCDMA power amplifier 4.3 Bias Point Simulation The first step towards designing the Class F amplifier was to select a suitable bias point for operation. A Class F amplifier can be biased as a Class A, AB, B or C amplifier and then suitable harmonic terminations can be designed to get efficiency higher than what could be achieved originally. It was seen earlier that Class A, AB, B and C amplifiers differ merely by their respective conduction angles. Thus a device can be made to operate under any of these modes by suitable adjusting the gate bias. It was also seen earlier that the Class AB amplifiers are generally used in WCDMA systems in order to provide linear operation at a reasonable efficiency. Hence the Class F power amplifier was biased as a Class AB amplifier. In order to determine the bias point a DC bias point simulation was performed. Fig 4.1 shows the plot of the DC transfer characteristics for the transistor at a drain-source voltage of 26 V. The drain bias voltage value was chosen to be 26 V in order to provide a large output voltage swing and at the same time to ensure that the device is operated below the transistor breakdown voltage of 58 V. 29

41 Vgs=3.2 Ids=4.66 E-4 Vds=26 Fig 4.1 Plot of transistor DC transfer characteristics at Vds = 26 V From Figure 4.1, we see that the transistor must be provided with a gate bias voltage between 3.2 V and 5.1 V for Class AB operation. A 3.8 V gate bias voltage was chosen for this design. 4.4 Load Pull and Source Pull Load pull is a technique wherein the load impedance seen by the device under test (DUT) is varied and the performance of the DUT is simultaneously measured [4]. Similarly in source pull the performance of the DUT for varying source impedances is measured. The measured results are very useful in determining the optimum load and source impedance which the device must see to give the best performance. Load pull, in particular, is commonly used to determine the load impedance required for maximizing efficiency. The input of a power amplifier is usually conjugate matched and the source pull is not always required. However in the design of a Class F power amplifier, it has been shown in [14] that the source pull is useful to investigate the effects of the second harmonic termination and make appropriate corrections to improve the Class F performance. The impedance seen by the device for maximum efficiency, power and gain can be quite different. In such cases the impedances are chosen as per the design requirements. It should be noted 30

42 that the impedance values calculated vary with bias. In this design load pull and source pull were performed to obtain maximum efficiency. The results obtained from these simulations shows that the transistor needs to see an impedance of j24.42 ohms at the output and j1.065 ohms at the input as shown in Figure 4.3. Simulated Load Reflection Coefficients Move Marker m3 to select impedance value and corresponding PAE and delivered power values. surface_samples m3 PAE, % Impedance at marker m j Power Delivered (dbm) real_indexs11 ( to 0.567) m3 real_indexs11= surf ace_samples=0.742 / imag_indexs11= impedance = Z0 * ( j0.488 Fig 4.2 Load Pull Analysis to determine load impedance for maximum efficiency j j24.42 Fig 4.3 Load and Source Impedance for maximum efficiency 31

43 4.5 Design Architecture Figure 4.4, shows the basic design architecture of the Class F power amplifier. V DD and V GG provide the required drain and gate bias determined previously from a 26 V supply. The DC bias and Dc blocks are ignored here. The input and output matching networks transform the impedance that the transistor needs to see at their respective sides to 50 ohms. The filter combination L 0 C 0 is tuned to the fundamental frequency. It provides very high impedance (ideally an open circuit) for the fundamental frequency and very low impedance (ideally a short circuit) for harmonic frequencies. L 3 and C 3 together form the third harmonic trap. This trap provides high impedance for the third harmonics and allows all other signals to pass through. Due to this the third harmonic voltages gets added out of phase to the fundamental voltage at the drain causing the flattening of the drain voltage waveform. The series filter combination L 2 C 2 along with the bypass capacitor bypasses the second harmonics to ground and provides high impedance at other frequencies. This results in short circuit second harmonic current which in turn makes the drain current waveform resemble a peaked half 0 V DD bypass capacitor V GG C2 L 2 L 0 Output Matching Input Matching RF in C 3 L 0 C 0 50 Ω 0 Fig 4.4 Class F Power Amplifier Design Architecture 32