Radio Frequency Switch-mode Power Amplifiers and Synchronous Rectifiers for Wireless Applications

Transcription

1 Radio Frequency Switch-mode Power Amplifiers and Synchronous Rectifiers for Wireless Applications by Sadegh Abbasian A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE COLLEGE OF GRADUATE STUDIES (Electrical Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Okanagan) October 2015 c Sadegh Abbasian, 2015

2 Abstract This thesis focuses on identifying and evaluating device, circuit, and system level issues that affect the power efficiency of class-d and class-f switch-mode amplifiers, and class- F synchronous rectifiers. The amplifier and rectifier circuits are used to implement pulse encoded switch-mode power amplifier systems. A detailed power efficiency analysis of current mode class-d amplifiers is presented for variable duty cycle pulse trains. A device model with current saturation in the switch is introduced and gives insight into how to select an appropriate load line for variable duty cycle switching conditions. Other new results include the effect of capacitive switching losses which are usually neglected in current mode amplifiers. The analytical results are compared with simulation results and confirm that the model can provide good predictions of power efficiency for a more general class of pulse encoded signals. Class-F amplifiers are also investigated in this work. The work investigates how input harmonic matching impedances at the gate affect amplifier power efficiency. Second harmonic matching is very important and desensitizes the circuit to nonlinear capacitances in the device. Third harmonic input terminations are much less significant. A comparison of voltage and current mode circuits is also made and the current mode is better in terms of maximizing power efficiency. The work is supported by experimental results. Class-F amplifier circuits are reconfigured into synchronous rectifiers using the theory of time-reversal duality. Time-reversal duality is usually applied in the context of lossless circuits and a discussion of how loss impacts the circuit duals is presented. The rectifier dual always has slightly higher power efficiency and insights into why this occurs are described. Experimental results are shown for voltage and current mode class-f rectifiers as well as a wideband current mode class-f rectifier. The thesis concludes with the analysis and experimental results for an energy recycling switch-mode power amplifier. A signal splitting network is implemented at the output of the amplifier and out-of-band power is rectified to enhance the power efficiency of the amplifier. Experimental results confirm that energy recycling can increase power efficiency. Concluding remarks based on this research are summarized in the context of how best to use these circuits for implementing high efficiency amplifiers and rectifiers for wireless applications. ii

3 Preface Some of the research results presented in this thesis have been published before in conference and journal articles. My co-author for these publications was Dr. Thomas Johnson, my research supervisor, and the relations between the published work and this thesis are summarized below. A part of Chapter 2 has been published as a conference paper. S. Abbasian and T. Johnson, RF current mode class-d power amplifiers under periodic and non-periodic switching conditions, in IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp Part of Chapter 3 has been published as a journal paper. S. Abbasian and T. Johnson, Effect of second and third harmonic input impedances in a class-f amplifier, Progress In Electromagnetics Research C, vol. 56, pp , Parts of Chapter 4 have been published as a journal paper and a conference paper. S. Abbasian and T. Johnson, High efficiency GaN HEMT class-f synchronous rectifier for wireless applications, IEICE Electronics Express, vol. 12, no. 1, pp. 1-11, S. Abbasian and T. Johnson, High efficiency and high power GaN HEMT inverse class-f synchronous rectifier for wireless power applications, in European Microwave Conference (EuMC), Paris, France, Sep. 2015, pp iii

4 Table of Contents Abstract ii Preface Table of Contents iii iv List of Tables vii List of Figures Acknowledgements Dedication List of Acronyms viii xiv xv xvi Chapter 1: Introduction Background Architecture of Switch-Mode Power Amplifier Systems Bandpass Sigma-delta Modulation Pulse Position Modulation Switch-mode Power Amplifier Circuits Class-D Power Amplifiers Class-E Power Amplifiers Class-F Power Amplifiers Summary of Amplifier Classes Based on Harmonic Termination Impedances Power Efficiency and Device Technology Literature Review Class-D Power Amplifiers Class-F Power Amplifiers RF Synchronous Rectifiers Research Goals and Objectives Predicting the Power Efficiency of CMCD Power Amplifiers for Time Encoded Input Signals RF Switch-mode Power Amplifiers with Energy Recycling RF Rectifier Circuits Class-F and Class-F 1 Power Amplifiers Supporting Publications iv

5 TABLE OF CONTENTS 1.7 Thesis Outline Chapter 2: Power Efficiency Analysis of RF Current Mode Class-D Amplifiers The Current Mode Class-D RF Amplifier Device Models Level Level Level Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Selecting the DC Supply Voltage Load Power Power Loss Mechanisms Selecting a Device Load Line Current Saturation Model Analytical versus Simulated Results Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals Time Encoded Input Signal Power Efficiency for 1 T Periodic Signals NT Periodic Signals Power Efficiency Analysis for a 2T Periodic Signal Power Efficiency for 6T Periodic Signals Chapter Summary Chapter 3: Class-F RF Power Amplifiers Level 3 Device Model Bare Die Device Model Class-F Amplifier Simulation Experiments Class-F Amplifier Design Harmonic Input Impedances and Sensitivity to Device Capacitances Class-F Amplifier Experimental Results Physical Circuit Design Experimental Results Inverse Class-F Power Amplifier Design Methodology Experimental Results Wideband Inverse Class-F Power Amplifier Design Methodology Distributed Matching Networks Experimental Results Chapter Summary Chapter 4: Class-F RF Synchronous Rectifiers The Principle of Time Reversal Duality Definitions of Equivalence for Amplifier and Rectifier Duals High Efficiency GaN HEMT Class-F Synchronous Rectifier Rectifier Test Bench and Efficiency Definitions Experimental Results v

6 TABLE OF CONTENTS Class-F Amplifier and Rectifier Power Efficiency Analysis Simulation Results High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier High Efficiency GaN HEMT Wideband Inverse Class-F Synchronous Rectifier Chapter Summary Chapter 5: Switch-mode Power Amplifier with Energy Recycling Energy Recycling in Outphasing Power Amplifiers Energy Recycling in RF Switch-mode Amplifiers Spectral Shaping to Enhance Energy Recycling Efficiency Analysis of Power Efficiency Enhancement using Energy Recycling Experimental Implementation of a Switch-mode Power Amplifier with Energy Recycling Discussion and Chapter Summary Chapter 6: Conclusions and Future Work Conclusions Future Work Bibliography Appendix Appendix A: Measurement Results for Another Class-F PA vi

7 List of Tables Table 1.1 Coefficient values for the noise shaping filter H RF (s) Table 1.2 Some recently published results for class-d power amplifiers Table 1.3 Some recently published results for class-f family PAs Table 1.4 Some recently published results for RF synchronous rectifiers Table 2.1 Summary of level 2 model values for the Cree CGH60015D die Table 2.2 CMCD Design Values Table 2.3 Duty cycles for generating signals with a period of 6T Table 3.5 Table 3.1 Level 3 model values for the Cree GaN HEMT (CGH60015D) in the off-state bias condition Table 3.2 Summary of device capacitances for a Cree GaN HEMT (CGH60015D). 66 Table 3.3 Class-F amplifier designs with input harmonic termination networks Table 3.4 IMN transmission line lengths for a device model with linear capacitances Summary of simulation results for a device model with nonlinear capacitances Table 3.6 Source and load pull harmonic impedances for the class-f amplifier Table 3.7 Transmission line lengths for load and source matching networks Table 3.8 Source and load pull harmonic impedances for the class-f 1 amplifier.. 84 Table 3.9 Microstrip transmission line lengths for the class-f 1 amplifier Table 3.10 Wideband class-f/family amplifier designs comparison Table 3.11 Results of the load/source pull simulations for Z Lopt and Z Sopt Table 3.12 Admittance parameters and extracted values for a third order network.. 91 Table 3.13 Table 3.14 Admittance parameters for low-pass network and extracted values for the final band-pass structure corresponding to the input matching network. 93 Microstrip transmission line lengths and widths for load and source matching networks Table 4.1 Time reversal relations for circuit components Table 4.2 Some recently published results for RF synchronous rectifiers Table 4.3 Comparison of class-f amplifier and rectifier experimental results Table 4.4 Comparison of class-f amplifier and rectifier circuit duals Table 4.5 Comparison of class-f 1 amplifier and rectifier experimental results vii

8 List of Figures Figure 1.1 RF switch-mode power amplifier architecture with energy recycling. The figure also serves as a roadmap for this thesis Figure 1.2 A class-ab power amplifier Figure 1.3 Efficiency as a function of conduction angle for conventional power Figure 1.4 amplifiers Efficiency and output power as a function of input power for a class-ab amplifier with a conduction angle of 244 (θ = 1.36π) Figure 1.5 Block diagram of a SMPA with encoder and reconstruction filter Figure 1.6 Block diagram of a bandpass sigma-delta modulator Figure 1.7 Power spectrum of a bandpass sigma-delta modulator Figure 1.8 A bandpass sigma-delta modulator pulse train in the time domain... 8 Figure 1.9 Block diagram of pulse position modulator Figure 1.10 A noise shaped PPM pulse train in the time domain Figure 1.11 A noise shaped PPM pulse train in the frequency domain Figure 1.12 Schematic of a VMCD power amplifier Figure 1.13 VMCD amplifier voltage and current waveforms for a periodic drive signal with a duty cycle of 30% Figure 1.14 Schematic of a CMCD Figure 1.15 CMCD current and voltage waveforms for a periodic input pulse train with a duty cycle of 30% Figure 1.16 Schematic of a class-e power amplifier Figure 1.17 Class-E voltage and current waveforms for a 30% duty cycle pulse train. 16 Figure 1.18 Normalized voltage across the switch in a class-e PA for three different duty cycles: 30% (circle), 50% (star) and 70% (square) Figure 1.19 A class-f power amplifier circuit Figure 1.20 Class-F power amplifier voltage and current waveforms Figure 1.21 Amplifier classes in terms of harmonic load impedances Figure 1.22 Band gap energy and saturated velocity for Si, GaAs and GaN Figure 1.23 GaN HEMT technology: packaged device from Cree (left) and MMIC (right) Figure 2.1 A CMCD circuit Figure 2.2 Typical DC IV characteristics for a GaN device Figure 2.3 Schematic for current mode class-d power amplifier with a level 1 device model (ADS schematic) Figure 2.4 Level 1 CMCD current and voltage waveforms for a 30% duty cycle periodic drive signal viii

9 LIST OF FIGURES Figure 2.5 Transition time (τ = 0.15T ) for a CMCD with Cree CGH60015D transistors Figure 2.6 Level 2 device model for a CMCD amplifier Figure 2.7 S-parameters for the on and off state for a Cree CGH60010D device.. 42 Figure 2.8 Signal with period T and variable duty cycle (α) Figure 2.9 Device current waveforms at the drain terminal of the switching device. The ADS simulation results are for a Cree large signal device model.. 45 Figure 2.10 Overlap of drain current and drain voltage waveforms in a CMCD amplifier Figure 2.11 DC IV operating region for a CMCD amplifier including margin for duty cycle variation Figure 2.12 Efficiency and output power of a CMCD as a function of load resistance (α = 0.5) Figure 2.13 Efficiency and output power of a CMCD as a function of load resistance (α = 0.3) Figure 2.14 DC device current as a function of sin(απ) (α is duty cycle) Figure 2.15 Losses in the CMCD amplifier as a function of duty cycle. The overlap period τ is 0.1 T Figure 2.16 Drain efficiency of CMCD amplifier as a function of duty cycle Figure 2.17 Signal with period 1T Figure 2.18 Comparison of power efficiency for a CMCD amplifier with a 1 T periodic signal and SDM non-periodic signal Figure 2.19 Drain efficiency as a function of modulator drive level for SDM and PPM encoders Figure 2.20 Signal with period 2T Figure 2.21 A 6T signal with a zero mean DC component Figure 2.22 Drain efficiency of CMCD amplifier as a function of duty cycle when driven with a 2T periodic signal Figure 2.23 CMCD amplifier power efficiency for periodic (1T, 2T, and 6T ) and non-periodic pulse trains (SDM and PPM) Figure 3.1 Level 3 equivalent circuit model for GaN HEMT Cree CGH60015D [reproduced courtesy of The Electromagnetics Academy] Figure 3.2 Equivalent circuit model for off-state bias conditions Figure 3.3 Z-parameters for the level 3 device model (symbols) and for the large signal device model (solid lines) for the off-state bias condition Figure 3.4 Y -parameters for the level 3 device model (symbols) and for the large signal device model (solid lines) for the off-state bias condition Figure 3.5 Extracted intrinsic device capacitances for the Cree GaN HEMT (CGH60015D): (a) drain-source capacitance, (b) gate-source capacitance, (c) gatedrain capacitance, and (d) gate-source capacitance versus gate-source voltage Figure 3.6 Device model for packaged die [reproduced courtesy of The Electromagnetics Academy] Figure 3.7 Comparison of Y 11 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. 68 ix

10 LIST OF FIGURES Figure 3.8 Comparison of Y 12 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. 69 Figure 3.9 Comparison of Y 22 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. 69 Figure 3.10 Schematic for the class-f PA [reproduced courtesy of The Electromagnetics Academy] Figure 3.11 Output matching network (OMN) structure [reproduced courtesy of The Electromagnetics Academy] Figure 3.12 Spectrum for the case where C gd = 0 pf: drain voltage (left) and gate voltage (right) [reproduced courtesy of The Electromagnetics Academy]. 73 Figure 3.13 Spectrum for the case where C gd = 0.36 pf: drain voltage (left) and gate voltage (right) [reproduced courtesy of The Electromagnetics Academy]. 74 Figure 3.14 Input matching network circuits: (a) Design 1, (b) Design 2 and (c) Design 3 [reproduced courtesy of The Electromagnetics Academy] Figure 3.15 Simulated drain efficiency as a function of second harmonic level for a device model with linear capacitances [reproduced courtesy of The Electromagnetics Academy] Figure 3.16 Schematic of the class-f power amplifier with output and input matching circuits and bias networks [reproduced courtesy of The Electromagnetics Academy] Figure 3.17 Simulated drain voltage and drain current waveforms (left) and gate voltage and drain current waveforms (right)[reproduced courtesy of The Electromagnetics Academy] Figure 3.18 Photograph of the 10 W class-f power amplifier Figure 3.19 The class-f amplifier test bench Figure 3.20 Measured and simulated drain efficiency and output power as a function of input power for a CW test signal [reproduced courtesy of The Electromagnetics Academy] Figure 3.21 Measured and simulated drain efficiency and output power as a function of frequency for a CW test signal [reproduced courtesy of The Electromagnetics Academy] Figure 3.22 Measured output spectrums for a WCDMA signal at three different output power levels: (a) 35.1 dbm (b) 33.4 dbm and (c) 31.6 dbm [reproduced courtesy of The Electromagnetics Academy] Figure 3.23 Measured drain efficiency and ACLR as a function of output power for a WCDMA signal [reproduced courtesy of The Electromagnetics Academy] Figure 3.24 Schematic of the class-f 1 PA with output and input matching circuits and bias networks Figure 3.25 Simulated drain voltage (solid) and drain current (dash) waveforms for the class-f 1 power amplifier. The waveforms are shown for the drain terminal of the packaged device Figure 3.26 Photograph of the class-f 1 power amplifier Figure 3.27 Drain efficiency and output power as a function of input power for the fabricated class-f 1 PA x

11 LIST OF FIGURES Figure 3.28 Different steps for design of a lumped element matching network: (a) low-pass network with normalized admittances g j ; (b) bandpass matching network; (c) Norton transformation to increase output impedance.. 90 Figure 3.29 Impedance and frequency scaled lumped element lowpass network for synthesizing a wideband output match Figure 3.30 Lumped element output network after applying a lowpass to bandpass transformation Figure 3.31 Impedance transformed output network (top) and the corresponding Norton transformation to create the impedance transformation (bottom). 92 Figure 3.32 Bandpass output matching network with an impedance transformer to match the output to 50 Ω Figure 3.33 Bandpass input matching network by Norton transformation (n T = Figure ) Dividing the capacitance C 1 into three parallel capacitances to reform the output structure as a distributed network Figure 3.35 Equivalent transmission line circuit for a shunt resonator Figure 3.36 Distributed output matching network Figure 3.37 Distributed input matching network Figure 3.38 The fundamental frequency impedances of the input and output matching networks Figure 3.39 The second harmonic impedances of the input and output matching networks Figure 3.40 Wide frequency range sweep of the impedances of the output matching network. Fundamental, second harmonic and third harmonic frequency ranges are shown Figure 3.41 Photograph of the wideband class-f 1 power amplifier Figure 3.42 Measured and simulated drain efficiency of the wideband class-f 1 PA as a function of frequency for a CW test signal Figure 4.1 (a) Network N and its current and voltage, (b) network N vc, a voltage and current dual of N, and (c) network N tr, a time reversal dual of N. 100 Figure 4.2 The direction of energy flow in a network and its TR dual Figure 4.3 Block diagrams of (a) a power amplifier, (b) synchronous rectifier dual, and (c) synchronous rectifier with feedback to provide gate drive Figure 4.4 Dynamic load lines for: (a) a class-f amplifier (b) a class-f rectifier Figure 4.5 The class-f rectifier test bench Figure 4.6 Measured RF to DC conversion efficiency and output DC power as a function of load resistance for a class-f rectifier Figure 4.7 Measured power efficiency and output DC power as a function of RF input power for a class-f rectifier Figure 4.8 Measured power efficiency and output DC power as a function of frequency for a class-f rectifier Figure 4.9 Class-F rectifier power efficiency with and without mismatch loss Figure 4.10 A class-f power amplifier with a series quarterwave transmission line Figure 4.11 Drain voltage and drain current waveforms for: (a) a class-f power amplifier and (b) a class-f rectifier xi

12 LIST OF FIGURES Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 4.17 Figure 4.18 Figure 4.19 Figure 4.20 Figure 4.21 Figure 4.22 Drain voltage and drain current waveforms with overlap loss for the class-f amplifier and rectifier duals Estimated drain efficiency of class-f PA and rectifier as a function of output capacitance. R on for both the amplifier and rectifier are 2.2 Ω Predicted losses in a class-f power amplifier as a function of output capacitance Predicted losses in a class-f rectifier as a function of output capacitance.121 Test bed for the class-f 1 rectifier. A class-f amplifier is used as a high power RF input source Measured RF to DC conversion efficiency and output DC power versus load resistance for the rectifier. The measurements conditions are for an input RF source power of dbm at a frequency of 910 MHz Measured power efficiency and output power as a function of frequency for the rectifier. The measurements conditions are for an input RF source power of dbm Power efficiency comparison of a class-f and class-f 1 synchronous rectifier. Experimental results are shown Measured drain efficiency as a function of frequency for the wideband class-f 1 rectifier Measured drain efficiency as a function of input power for the wideband class-f 1 rectifier at frequencies of 650 MHz, 850 MHz and 1050 MHz. 127 Measured drain efficiency as a function of input power for class-f, class- F 1 and wideband class-f 1 synchronous rectifiers Figure 5.1 Outphasing amplifiers: (a) reactive signal combining and (b) isolated signal combining with energy recycling Figure 5.2 Switch-mode power amplifiers (a) with reactive output filter and (b) with energy recycling Figure 5.3 Block diagram of a noise shaped PPM encoder with dither (top) and example input and output waveforms (bottom) Figure 5.4 Power spectrum of a noise shaped PPM signal without out-of-band spectral shaping (top) and with spectral shaping (bottom) Figure 5.5 Block diagram of a power amplifier with energy recycling Figure 5.6 Examples of amplifier power efficiency with energy recycling Figure 5.7 Test bed with a class F amplifier and a class-f 1 rectifier to recover out-of-band energy. The system implements the block diagram shown in Figure 5.2(b) Figure 5.8 Measured in-band and recovered power as a function of the coding efficiency for encoder of the noise shaped PPM modulator Figure 5.9 Measured drain efficiencies with and without energy recycling Figure A.1 Figure A.2 Figure A.3 Measured drain efficiency as a function of input power for a CW test signal Measured drain efficiency as a function of frequency for a CW test signal.155 Measured output spectrums for a WCDMA signal at three different output power levels: (a) 34.2 dbm (b) 32.4 dbm and (c) 30.5 dbm xii

13 LIST OF FIGURES Figure A.4 Measured drain efficiency and ACLR as a function of output power for a WCDMA signal xiii

14 Acknowledgements First of all, I would like to offer my sincere gratitude to my supervisor, Dr. Thomas Johnson who has inspired me to continue my work in this field, and thanks to him for his patient guidance and generous support throughout my studies. I would like to thank Dr. Stephen O Leary and Dr. Wilson Eberle for their support during the past few years as members of my supervisory committee. I would also like to thank all the professors in the electrical engineering department who contributed to my learning through lectures and classes. I would like to appreciate Dr. Fadhel Ghannouchi from the university of Calgary and Dr. Homayoun Najjaran as members of my examining Committee. I offer my gratitude to Dr. Andrew Labun with whom I spent a great time doing research with in the summer of I also would like to thank my colleagues especially Dr. Ali Tirdad and Mr. Saimoom Ferdous for their support throughout the work. I offer my best and special thanks to my parents and family who have supported me with their unconditional love throughout my years of education. xiv

15 Dedication I dedicate this thesis to my parents and family who have supported me throughout my years of education. xv

16 List of Acronyms ADS ACLR Advanced Design System Adjacent Channel Leakage Ratio CMCD Current-Mode Class D CE CW GaN Codding Efficiency Continuous Wave Gallium Nitride HEMT High Electron Mobility Transistor HSPA JFOM MMIC MSE PA PPM PWM RF SDM SMPA TL TR Hard Switched Power Amplifier Johnson s Figure of Merit Monolithic Microwave Integrated Circuit Mean Square Error Power Amplifier Pulse Position Modulation Pulse Width Modulation Radio Frequency Sigma Delta Modulation Switch-Mode Power Amplifier Transmission Line Time Reversal VMCD Voltage-Mode Class D ZVS Zero Voltage Switching xvi

17 Chapter 1 Introduction This thesis is about the design and implementation of high efficiency amplifiers and rectifiers for wireless applications. The work is motivated by interest to improve the power efficiency of transmit amplifiers in mobile devices like smartphones and basestations. The transmit power amplifier (PA) is a large signal stage in the transceiver and the power consumption of the amplifier circuit is a significant portion of the total power consumed by the equipment. Reduced energy consumption improves battery utilization in mobile devices and decreases electric utility costs for operating basestations. The motivation to improve power efficiency in high power radio frequency (RF) amplifiers has led to a shift from analog modes of amplification to digital modes of amplification. The allure of the digital amplifier is based on the concept that if an amplifying device is operated as a switch instead of as an analog amplifier, then the power dissipation in the amplifying device is significantly reduced. If device dissipation is reduced, then the overall amplifier power efficiency is increased because more of the DC supply power is converted to RF power. An amplifier that is designed to operate the amplifying device as a switch, is called a switch-mode amplifier. Examples of switch-mode amplifier circuits are class-d and class-e. The term switch-mode can also be extended to circuits where the waveforms are designed to minimize overlap losses, and in the limit of no overlap loss, the circuit operation is equivalent to a switch. Class-F is an example of circuits which use waveform shaping to minimize device dissipation. In theory, very high power efficiencies are possible in switch-mode amplifiers providing losses are minimal. Unfortunately, at high frequencies, ideal switching is not realizable with current device technology, and losses can be very significant. Therefore, switch-mode power amplifier circuits in the GHz frequency range are very challenging to implement. The designer is forced to carefully evaluate circuits and seek to understand what limits performance and determine how to overcome these limitations. The goal of this research is to gain insight into ways to improve the power efficiency of RF switch-mode amplifiers. The work can be divided into four main topics. The first topic is an analytic study of power losses in class-d amplifiers for arbitrary duty cycle pulse trains. The second topic is related to a study of the relationship between input harmonic impedance and power efficiency for class-f amplifiers. The class-f work also includes experimental measurements for three different types of class-f amplifiers and conclusions are made on the best circuit topology for the highest power efficiency. The third topic is the analysis and implementation of a new switch-mode power amplifier system that employs energy recycling as an efficiency enhancement technique. The experimental implementation of the energy recycling amplifier led to a fourth topic which was the design of high efficiency RF rectifiers required to convert RF power into DC power. The rectifier designs are closely linked to the design of switch-mode power amplifiers and a design methodology based on the theory of time-reversal duality has been used. An overview of the thesis is given in Figure

18 Chapter 1. Introduction Energy Recovery System Class-F/Family Synchronous Rectifiers Chapter 5 Chapter 4 Bandstop Power Spectrum VDD RF to DC Conversion RF Modulated Signal Encoder SMPA A Out-of-band Power Signal Separator In-band Power Power Spectrum at node A Bandpass Power Spectrum PPM/SDM with Spectral Shaping Class-D 1 Chapter 2 Chapter 5 Class-F/Family Chapter 3 Figure 1.1: RF switch-mode power amplifier architecture with energy recycling. The figure also serves as a roadmap for this thesis. 2

19 1.1. Background 1.1 Background The quest to design power efficient amplifiers has a long history. Two examples are the Doherty amplifier [1] and the Chireix outphasing amplifier [2] both which were patented in the early 1930 s. As a testament to this early work, the theory remains in widespread use today and work continues to improve these types of amplifiers. A study of power amplifiers nearly always begins with classical (conventional) transconductance amplifiers which are defined by the current conduction angle in the amplifying device. These amplifiers are called class-a (100% current conduction), class-ab (typically around 70% current conduction), class-b (50% current conduction) and class-c (less than 50% current conduction). An example of a transconductance amplifier circuit is shown in Figure 1.2. The current conduction in the transistor is dependent on the gate bias and the load line for the device. The relationships between conduction angle, output power, and power efficiency are shown in Figure 1.3 [3]. The class-ab operating point is commonly used in wireless communication applications as it provides a good balance between power efficiency and distortion. i d (θ) Vg v d (θ) d M 1 L DD I DC C B L 0 C 0 R L V out V DD Figure 1.2: A class-ab power amplifier. One of the drawbacks of the class-ab amplifier is that power efficiency is amplitude dependent. The amplitude dependence is most commonly shown as a relationship between input power and power efficiency. An example for a class-ab amplifier is shown in Figure 1.4. The plot shows that maximum efficiency is obtained at maximum power which corresponds to the maximum input amplitude to the amplifier. Power efficiency decreases as the input amplitude (input power) is reduced. The term back-off refers to how much the input power is backed off from the peak output power which the amplifier can deliver. For the class- AB amplifier shown in Figure 1.4, the peak efficiency at the 1 db compression point (0 db back-off) is 63%, while the power efficiency at 6 db back-off is 38%, much less than peak efficiency. The amplitude response shown in Figure 1.4 is an example of the how the amplifier would respond to an unmodulated signal. An unmodulated signal, also called a continuous wave (CW) signal, is a sinusoidal signal with a constant frequency (f c ), constant amplitude (A) and phase (φ o ): s cw (t) = A cos(2πf c t + φ o ). (1.1) Although useful for characterizing amplifiers, a CW signal does not carry information, and in a communication system application, modulation is added to the carrier. More generally, any 3

20 1.1. Background Figure 1.3: Efficiency as a function of conduction angle for conventional power amplifiers. communication signal which can be transmitted through a physical medium can be expressed as s(t) = r(t) cos[2πf c t + φ(t)] where r(t) 0. (1.2) The signal envelope, r(t), adds information to the carrier by amplitude modulation (AM), while the phase term, φ(t), adds information by phase modulation (PM). Both the AM and PM components in a communication signal can be problematic for power amplifiers. Since power efficiency in an amplifier is amplitude dependent, the average power efficiency of the amplifier depends on the statistical distribution of the envelope variation in the signal. Most signals have a peak amplitude that occurs infrequently and the average envelope amplitude is typically much smaller than the peak amplitude. The measure most commonly used to quantify amplitude variation in the signal is called the peak to average power ratio (PAPR): ( ) peak signal power PAPR (db) = 10 log 10. (1.3) average signal power Many common wireless communication signals have a PAPR in the range of 6-10 db. The implication of signals with high PAPR is that, on average, the power amplifier operates in a back-off state approximately equal to the PAPR of the signal. Therefore, when a class- AB amplifier is used to amplify a signal with a 6 db PAPR, the average efficiency of the amplifier is approximately equal to the efficiency at 6 db back-off. For the class-ab amplifier example shown in Figure 1.4, the average power efficiency of the amplifier for a 6 db PAPR signal would therefore be approximately 38%, much less than peak efficiency which is 63%. Although a more accurate estimate of the average efficiency is obtained by integrating the CW response characteristics over the amplitude probability distribution of the input signal, 4

21 1.1. Background Efficiency (%) Designed Class AB PA Using Cree CGH60015D Ideal Class AB PA 1 db 1 db Compression Point Output Power (dbm) 6 db Back off Mode Input Power (dbm) Figure 1.4: Efficiency and output power as a function of input power for a class-ab amplifier with a conduction angle of 244 (θ = 1.36π). the estimate using PAPR is a very useful approximation. Consequently, the average power efficiency of a class-ab amplifier is much less than the peak power efficiency when amplifying typical communication signals. Another important characteristic of power amplifiers is distortion. Distortion is created by nonlinear amplitude and phase characteristics in the amplifier. Under large signal conditions, the amplifier saturates leading to amplitude compression. Under small amplitude conditions, the amplifier may enter cut-off depending on the bias point of the amplifying device. Any deviation from linear amplitude characteristics results in distortion that appears in the output signal. Distortion can also be generated from phase distortion that may be both amplitude and frequency dependent. Because conventional transconductance amplifiers have amplitude dependent power efficiency characteristics, the key to implementing a high efficiency amplifier is to devise circuits whose power efficiency has reduced sensitivity to amplitude variation. There are different approaches to this problem. One method is to implement parallel signal paths which work together to reduce amplitude sensitivity. Examples of this method include Doherty [1] and Chireix outphasing [2] techniques. Another approach is to create signalling and circuits that maintain a saturated operating point in the amplifier. Examples of these methods include envelope tracking [4] and switch-mode power amplifier techniques [5]. In this research, the focus is on the latter method and new analytic and experimental results are presented for switch-mode power amplifiers (SMPAs). 5

22 1.2. Architecture of Switch-Mode Power Amplifier Systems 1.2 Architecture of Switch-Mode Power Amplifier Systems In a switch mode power amplifier (SMPA), the active device is used as a switch instead of a linearly controlled current source. When the switch is on, the voltage across the switch is low and current is high, and when the switch is open, the voltage is high and the current is low (ideally zero). The switching action theoretically leads to 100% efficiency if the switches are ideal, because the dissipation in the device, equal to the product of the current times voltage, is zero. However, practical devices, especially at high frequencies, have capacitance, inductance, and finite on and off state resistances that all lead to dissipation in the device which degrades power efficiency. Assuming that a high efficiency switch-mode amplifier can be implemented, the drawback of switch-mode operation is that a modulated signal with an AM signal envelope cannot be directly amplified because the amplitude states created by the switching action quantize the output amplitude. For a switch-mode amplifier with two amplitude states, the output amplitude is binary, and the only information which can be conveyed to the output signal is the timing of level crossings. Therefore, if the high efficiency operation of a switch-mode amplifier is to be utilized in a wireless communication application, additional circuit blocks must be added to the amplifier system to map the modulated input signal into a pulse train and to reconstruct the original modulated source after amplifying the pulse train. A block diagram of the amplifier system is shown in Figure 1.5. Figure 1.5: Block diagram of a SMPA with encoder and reconstruction filter. Signal reconstruction in a switch-mode power amplifier is constrained by the types of circuit elements that can be used in a high power radio frequency output stage. Almost universally, signal reconstruction is implemented with a bandpass filter, and this in turn imposes design constraints on the type of signal mapping which can be used to implement the pulse encoder. By quantizing the modulated signal to binary amplitude levels, a large amount of quantization noise is added by the pulse encoder. The quantization noise is spread over a very wide bandwidth and signal encoders implement methods to shape the noise spectrum and create a narrow region of high signal to noise ratio (SNR) where the source signal is placed. Examples of compatible source encoding techniques include bandpass sigma-delta modulation (SDM) [6, 7] and noise shaped pulse position modulation (PPM) [7, 8]. More generally, SDM and PPM are examples of a larger signal set called time encoded signals which are a class of signals that convey information in the timing of the zero-crossings (amplitude transitions). In the following sections, a brief summary of SDM and PPM pulse encoding methods are given. 6

23 1.2. Architecture of Switch-Mode Power Amplifier Systems Bandpass Sigma-delta Modulation Bandpass sigma-delta modulation has been proposed by many researchers as one way of implementing a pulse encoder for switch-mode power amplifiers [7, 6]. A block diagram of a bandpass SDM is shown in Figure 1.6. The input to the encoder is an RF modulated source signal and the output is a quantized two level pulse train. The quantization process generates significant quantization noise that is shaped by a loop filter H RF (s). The noise shaping filter creates a noise well where the RF input signal spectrum is placed. The noise well is called the in-band spectrum and the broadband noise is called the out-of-band spectrum. An example of the output spectrum from a SDM encoder is shown in Figure 1.7 and the corresponding time domain signal is shown in Figure 1.8. Noise Shaping Filter Clock (f s ) Sampling Quantizer s(t) H RF (s) p(t) Figure 1.6: Block diagram of a bandpass sigma-delta modulator. 20 Modulator Output Power Spectrum; 0.25Tc 0 Power [dbm] Frequency [MHz] Figure 1.7: Power spectrum of a bandpass sigma-delta modulator. The quantizer in a bandpass SDM is triggered by a sampling clock with a frequency f s. The sampling clock is typically selected to be at least above the Nyquist rate of the carrier frequency, which means the complex envelope is oversampled. For example, a 1 GHz wideband code division multiple access (WCDMA) modulated input signal with a bandwidth of 10 MHz sampled by a 3.4 GHz clock, has an envelope over sample ratio of 170 and a carrier oversample ratio of The signal to noise ratio of the reconstructed load signal which is determined by 1 In SDM theory, oversample ratio is usually defined relative to the Nyquist sample rate. For example, 7

24 1.2. Architecture of Switch-Mode Power Amplifier Systems 1 p(t): Sigma-delta pulse trains Time (ns) Figure 1.8: A bandpass sigma-delta modulator pulse train in the time domain. the envelope oversample ratio. Therefore, a high envelope oversample ratio is required; the carrier oversample ratio can also affect the signal to noise ratio but in a less predictable way [6]. Because the timing of the level crossings in a bandpass sigma-delta modulator are triggered by a clock, the pulse widths in the output are integer multiples of the clock period, T s, where T s = 1/f s. Therefore the minimum pulse width is constrained to T s which is beneficial since the current mode class-d power amplifier (CMCD) has a bandwidth limitation and cannot amplify very narrow pulses. On the other hand, long pulses are possible, but occur very infrequently. Examples of pulse distributions can be found in the literature [9]. For this research project, a fourth order bandpass SDM is used. The fourth order transfer function for the noise shaping filter H RF (s) is H RF (s) = 3 n=0 b ns n 4 n=0 a ns n (1.4) and the coefficients are shown in Table 1.1. The carrier oversample ratio for the quantizer is always 3.4 times the carrier frequency of the input source signal. The quantizer amplitude levels are normalized to ±1 V and a full scale input amplitude is defined as an amplitude of 1 V. The modulator is implemented in Matlab/Simulink and data files are generated for the pulse trains. The data files can be used for both simulation and for experimental work where the files are downloaded to an arbitrary waveform generator Pulse Position Modulation Noise shaped pulse position modulation (PPM) [10] is another encoding method that can be used for switch-mode power amplifiers. Unlike bandpass SDM which generates level transitions that are synchronized with a clock, PPM amplitude changes are asynchronous and can occur at any time. A block diagram of a noise shaped PPM encoder is shown Figure GHz/(2 1 GHz) =

25 1.2. Architecture of Switch-Mode Power Amplifier Systems Table 1.1: Coefficient values for the noise shaping filter H RF (s) n b n a n In the noise shaped PPM encoder, the amplitude and width of pulses are constant and the position (timing) of pulse edges are variable and dependent on the input source signal s(t). Similar to bandpass SDM, the spectrum of PPM is broadband, and the feedback loop shapes the in-band noise to ensure the source signal is encoded with a high signal to noise ratio. Examples of a noise shaped PPM signal in the time domain and frequency domain are shown in Figures 1.10 and 1.11, respectively. s(t) Noise Shaping H RF (s) Pulse Generator T p p(t) Figure 1.9: Block diagram of pulse position modulator. 1 p(t): Pulse position pulse trains Time (ns) Figure 1.10: A noise shaped PPM pulse train in the time domain. The noise shaped PPM encoder is implemented in a Matlab/Simulink model. The noise 9

26 1.3. Switch-mode Power Amplifier Circuits Power [dbm] Frequency [MHz] Figure 1.11: A noise shaped PPM pulse train in the frequency domain. shaping filter H RF (s) is identical to the bandpass SDM filter whose coefficients were given in Table 1.1. The pulse width, T p, is set to be equal to half the period of the input carrier frequency. This leads to an efficient encoder with high coding efficiency. Data files are generated from the Matlab models and used for simulation and the files are downloaded to an arbitrary waveform generator for experimental work. 1.3 Switch-mode Power Amplifier Circuits The high efficiency amplifier circuit topologies which are relevant to this work are class-d, class-e and class-f. Class-D and class-e are called switch-mode classes because the gate of the device is switched by the input signal. Class-F is also frequently lumped into the switchmode category, although it does not necessary require a two level input signal to switch the amplifying device. Class-F originated from the design of harmonic tuning in the output circuit rather than from a concept where the input signal switches the device. Within class-d and class-f, the circuit designs can be subdivided into two types of circuits. Circuits which switch voltage are called voltage mode (VM) circuits and circuits which switch current are called current mode (CM) circuits. The terms voltage switched and current switched are most widely applied to class-d amplifiers. Within the context of class-f amplifiers, the term inverse class-f, also written at class-f 1, is more widely used to distinguish current switching from voltage switching which is simply written as class-f. A short overview of the basic operation of these circuits is presented next. 10

27 1.3. Switch-mode Power Amplifier Circuits Class-D Power Amplifiers Voltage Mode Class-D A voltage mode class-d power amplifier (VMCD) is shown in Figure The circuit consists of two active devices in a cascade configuration. The common junction between the devices is connected to a series output filter to reconstruct a sinusoidal load signal from the pulse train. The gate drive signals, V in1 and V in2, are two antiphase pulse trains which control the state of the switches (devices). V DD I DC P DC L DD C RF V D1 V in1 M 1 Bandpass Filter P out V D2 L t C t M 2 R L VL V in2 Figure 1.12: Schematic of a VMCD power amplifier. Figure 1.13 shows current and voltage waveforms for the VMCD amplifier when the input pulse train is a periodic pulse train with a duty cycle of 30%. The first row shows the gate drive waveforms, the second row shows the drain-source voltages across each switch, and the third row shows the current through each switch. The drain voltage waveforms are similar to the gate voltage waveforms except for distortion arising from switch resistance. Since the voltage waveform follows the input pulse train, the circuit is called a voltage mode class-d amplifier. The current through the switches are a portion of a sinewave. The two switch currents sum to provide a sinusoidal load current. 11

28 1.3. Switch-mode Power Amplifier Circuits V D1 (V) V D2 (V) Figure 1.13: VMCD amplifier voltage and current waveforms for a periodic drive signal with a duty cycle of 30%. 12

29 1.3. Switch-mode Power Amplifier Circuits Current Mode Class-D Figure 1.14 shows a current mode class-d power amplifier. Similar to a VMCD amplifier, the input pulse trains, V in1 and V in2, are two antiphase signals that control the state of the switches. When a device is turned on, the voltage across the switch is zero and all the DC current, I DC, provided by the supply goes through the switch. When the same device is turned off, there is no current through the switch and the voltage across the switch is a portion of a sinusoidal wave. The switch current is similar to a square wave and the voltage across the device is a portion of a sinusoidal wave. In other words, the CMCD amplifier can be considered as the voltage-current dual of the VMCD amplifier. The reconstruction filter is a shunt filter in a CMCD circuit which is also the dual of the series resonator in the VMCD circuit. V DD I DC P DC L DD V D1 L t R L L DD V D2 V in1 V g1 C t M 1 M 2 V g2 V in2 Figure 1.14: Schematic of a CMCD. One of the main advantages of the CMCD circuit in Figure 1.14 compared to the VMCD circuit in Figure 1.12 is that the gate drive signals in CMCD are ground referenced, while the gate drive signal for the upper transistor in the VMCD circuit, M 1, requires a bootstrap drive circuit. This feature of CMCD amplifiers makes it more attractive for experimental work [11, 12]. Current and voltage waveforms for an example of a CMCD amplifier are shown in Figure In the first row, the gate drive waveforms are shown. The input signal is a periodic square wave with a duty cycle of 30%. In the second row, the current through the switches is shown. Clearly the current follows the gate waveform and current is switched in the circuit. In the third row, the drain-source voltage across each switch is shown. The drain voltage waveforms are a gated sinewave and the differential voltage, V D1 V D2, is a sinusoidal signal. The differential drain voltage is the same as the voltage across the load resistor and the shunt resonator circulates harmonic current between the switches. 13

30 1.3. Switch-mode Power Amplifier Circuits V D1 (V) V D2 (V) Figure 1.15: CMCD current and voltage waveforms for a periodic input pulse train with a duty cycle of 30%. 14

31 1.3. Switch-mode Power Amplifier Circuits Class-E Power Amplifiers Several years after the class-d circuit topology was introduced, Sokal reported the first class-e amplifier in 1975 [13]. The novelty in the class-e circuit topology is that, unlike class-d which requires two switches, the class-e amplifier requires only one switch. A class-e amplifier circuit is shown in Figure The switch M 1 is shunted by a capacitor C P and the load is connected through a series resonator. When the switch is on, current flows through the switch and the voltage across the shunt capacitance C P is low. When the switch is open, the capacitor provides current to the load and the voltage across the capacitor changes. V DD I DC P DC L DD V drain Series Resonator P out i sw M 1 i c L X C P L t C t R L VL V in Figure 1.16: Schematic of a class-e power amplifier. Example waveforms for a class-e amplifier are shown in Figure The gate drive signal is shown at the top of the figure and the waveform is a square wave pulse train with a duty cycle of 30%. The load current is sinusoidal because the series resonator filters the nonsinusoidal drain voltage waveform, and the sinusoidal current is alternately sourced/sunk by the switch, M 1, or the shunt capacitor, C P. The current into the switch and the current into the capacitor are shown, and the two currents sum to equal the sinusoidal load current. The voltage waveform is more difficult to understand and requires analysis [3]. The key features of the voltage waveform are that the voltage is zero when the current is switched between the switch and the capacitor. By proper choice of capacitance C P and inductance L X, the first derivative of the voltage waveform can also be zero at the switching instances. In this way, the voltage waveform smoothly approaches zero at each switching instant and the circuit implements a zero-voltage switching and zero-derivative switching condition. This is the key feature of the class-e amplifier. Therefore, the circuit is attractive because it has a single switch and very high efficiency because of the zero-voltage switching condition. The shunt capacitance C P can also be partitioned between the intrinsic output capacitance of the device and an external capacitance such that the sum is equal to C P. The primary disadvantage of class-e is the peak voltage generated across the switch. The peak voltage depends on the duty cycle of the input signal and the variation in peak voltage is illustrated in Figure The peak drain voltage is normalized to V DD in this figure and ranges from 2.7 for a 50% duty cycle to 4.8 for a 30% duty cycle. The variation in peak voltage as a function of duty cycle is distinctly different from class-d where peak voltage is independent of duty cycle. The variation in peak voltage is even more problematic for non- 15

32 1.3. Switch-mode Power Amplifier Circuits Figure 1.17: Class-E voltage and current waveforms for a 30% duty cycle pulse train. 16

33 1.3. Switch-mode Power Amplifier Circuits periodic pulse trains generated by SDM or PPM pulse encoders where peak voltages can easily be five times larger than V DD. Therefore, although class-e has attractive features, voltage peaking limits its application in switch-mode power amplifiers and this amplifier topology will not be analyzed further in this work. Literature references to class-e amplifiers will be made later in the context of designing RF rectifiers. Normalized drain voltage Time (ns) Figure 1.18: Normalized voltage across the switch in a class-e PA for three different duty cycles: 30% (circle), 50% (star) and 70% (square) Class-F Power Amplifiers In class-d and class-e amplifier circuits, the device is operated as a switch and the switched waveforms at the drain node of the devices are the result of both a switched gate drive signal as well as an output resonator. In class-f, the principle idea is to shape the drain signal waveforms by controlling the harmonic impedance of the output network such that overlap between the current and voltage waveforms are minimized. In practical class-f amplifiers, harmonic impedances up to the third harmonic are commonly controlled and in some designs even higher harmonic order impedance terminations are implemented to maximize power efficiency. Although output harmonic impedances presented to the drain terminal of the device are very important in class-f circuits, harmonic impedances at the gate (input) terminal of the device can also significantly affect the power efficiency of the amplifier. The importance of input harmonic matching is a topic that is investigated further in this work. A class-f amplifier circuit with harmonic control up to the fifth harmonic is shown in Figure 1.19 and example waveforms are shown in Figure The input signal has a fundamental frequency f o. The amplifying device is usually biased near a class-b operating point and the current through the device conducts for half a cycle. The device current waveform is ideally a half sinusoid and has a fundamental frequency component and even harmonics. The output matching circuit is designed to short the even harmonics in the current waveform and present an open circuit impedance for odd harmonic frequencies. With open circuit impedances at 17

34 1.3. Switch-mode Power Amplifier Circuits odd harmonics, the voltage waveform across the switch is shaped to be a rectangular square wave. Ideally, the overlap of the current and voltage waveforms across the device is small which then leads to low dissipation and high power efficiency. Since the voltage is a square wave in class-f, the circuit switches voltage. V DD I DC P DC L DD V drain Third Harmonic C 3 Fifth Harmonic C 5 P out L 3 M L 5 C 0 L 0 R L VL V in f 0 Figure 1.19: A class-f power amplifier circuit. Class-F amplifier circuits can also be designed to switch current and the current switched dual is called inverse class-f or class-f 1. In a current switched amplifier, the odd harmonics are shorted at the drain node and the even harmonics are open. Under these conditions, the current is switched and the voltage is a half sinusoid. Class-F amplifiers are explored much more extensively in Chapter 3. 18

35 1.3. Switch-mode Power Amplifier Circuits 2 1 Vinput (V) 0-1 Vdrain (V) Idrain (ma) VLoad (V) Time (ns) Time (ns) Time (ns) Time (ns) Figure 1.20: Class-F power amplifier voltage and current waveforms. 19

36 1.3. Switch-mode Power Amplifier Circuits Summary of Amplifier Classes Based on Harmonic Termination Impedances The concept of harmonic impedances in class-f can be applied more broadly to other amplifier classes and this provides a unified way to see the relationships between different amplifier classes. Every amplifier has an output matching circuit that provides a fundamental frequency match. The output matching circuit also presents the device with harmonic impedances that may be either explicitly controlled as in class-f, or implicitly controlled as in class-e. By considering the relative impedance of the odd and even harmonics, the different amplifier classes can be identified in a diagram as shown in Figure This type of visualization for the amplifier classes was first presented by Raab in 2001 [14]. In the diagram, the x-axis shows the relative magnitude of the even harmonic impedance (reactance) and the y-axis shows the relative magnitude for the odd harmonic impedance presented to the drain terminal of the amplifying device. Mid-scale on each axis is the relative load line resistance presented to the device at the fundamental frequency. Starting with class-f, the output matching network should have high impedance at odd harmonics and low impedance for even harmonics. This places class-f in the upper left hand corner of the diagram. Inverse class-f is in the lower righthand corner and requires high impedance at even harmonics and low impedance at odd harmonics. Voltage switched class- D has an output series resonator that in theory presents an open circuit impedance at all harmonics and therefore class-d is in the upper right. Conversely, inverse class-d has an antiresonant parallel resonant circuit which shorts all harmonic frequency components placing class-d 1 in the lower lefthand corner. Class-E has a specially designed output network impedance that leads to zero voltage switching and consequently the harmonic impedances are neither shorted nor open. Class-E harmonic impedances lie within the middle of the figure. Z n=3,5,... F D R 1 E 0 0 D 1 R 1 F 1 Z k=2,4,... Figure 1.21: Amplifier classes in terms of harmonic load impedances. 20

37 1.4. Power Efficiency and Device Technology 1.4 Power Efficiency and Device Technology Of the different types of device technologies which are available for wireless communication applications, Gallium Nitride (GaN) device technology is now used in many power amplifier designs [8, 15, 16, 17, 18, 19, 20, 21]. GaN device technology has the following features: A large band-gap energy leads to high electric field breakdown potentials [22]; for instance, the breakdown voltage of a Cree CGH40010 transistor is 84 V [23]. GaN has a higher carrier saturation velocity compared to other technologies [22]. The thermal dissipation of GaN devices is high. Combined with high breakdown voltages, GaN devices have higher power densities (W/mm of gate width) compared to other device technologies such as silicon LDMOS (laterally diffused metal oxide semiconductor). Figure 1.22 shows the band-gap energy of three different materials versus saturation velocity. From this figure it shows that GaN offers much better high power and high frequency possibilities compared to Gallium Arsenide (GaAs) and Silicon (Si) device technologies. For a better comparison of different semiconductor materials, Johnson s figure of merit (JFOM) was proposed [24]. It uses the breakdown voltage and saturated electron drift velocity to define a value for the high-frequency handling capability of a certain semiconductor material. JFOM is expressed as V sat E c /(2π) where V sat is the saturated electron velocity and E c is the critical breakdown field. For example, the JFOM for GaN is 27 times higher than that of silicon, about 15 times that of GaAs, and about 1.4 times that of Silicon Carbide (SiC) GaN Eg (ev) Si GaAs Vsat (cm/s) Figure 1.22: Band gap energy and saturated velocity for Si, GaAs and GaN. GaN device technology is available in both discrete high power devices as well as monolithic microwave integrated circuit (MMIC) processes. A picture of a discrete GaN device and a MMIC GaN circuit are shown in Figure In this research project, power amplifiers are x

38 1.5. Literature Review Figure 1.23: GaN HEMT technology: packaged device from Cree (left) and MMIC (right). built using discrete GaN devices and a 10 W device available from Cree; model CGH40010, is used. For modeling work, the bare die, model CGH60015D, is used along with a package model. Although Cree provides comprehensive large signal device models for these components, they are black-box models, and equivalent circuit models are developed to provide further insight into device losses and to predict power efficiency of different amplifier circuits. 1.5 Literature Review A short summary of relevant published work which provides context for this research is given in the next sections Class-D Power Amplifiers Of the three amplifier classes (class-d, class-e and class-f), the class-d circuit topology is well suited for amplifying pulse encoded signals. Providing the devices are driven with a broadband driver, the amplifier is broadband, and the circuit is fundamentally robust enough to amplify signals with a range of different duty cycles. The output resonant circuit can also be used as a reconstruction filter, although higher order filter structures are usually required to sufficiently attenuate out-of-band noise. These features have motivated significant research interest in the design of RF class-d power amplifiers for pulse encoded signals Voltage Mode Class-D Amplifiers The origin of the class-d amplifier dates back just over fifty years ago, when Baxandall reported the first experimental results in 1959 [25]. The circuit was designed as a way of generating high power sinusoidal signals for RF transmitters. During the next two decades, a number of different high frequency class-d amplifiers were designed and implemented for various applications. Variants of the original class-d amplifier which used complementary switches then evolved into transformer coupled voltage and current switched configurations [26, 27]. Experimental circuits optimized for high power amplifiers which use periodic signal source to generate sinusoidal load signals continue to the present day [28, 29]. The first reported work associated with class-d power amplifiers that amplify pulse encoded signals was described by Raab in 1973 [30]. In his circuit, an RF PWM (pulse width 22

39 1.5. Literature Review modulated) signal was amplified by a class-d amplifier in the MHz frequency range. The first simulated results for a class-d power amplifier with sigma-delta modulation was published in [31]. In 2008, Johnson et al. [6] published the analysis of a VMCD with bandpass sigma-delta modulation and he introduced the concept of coding efficiency to generalize the analysis of power efficiency to include pulse encoded signals. The loss mechanisms of a voltage mode class-d amplifier were formulated in [32] and supported by experimental results for a CMOS VMCD amplifier in Recently, other experimental work with time-encoded signals including SDM, PPM and PWM for a GaN VMCD amplifier have been reported [8] Current Mode Class-D Amplifiers In 2001, researchers at USCD published a paper on a CMCD power amplifier circuit that used a differential tank with two inductors providing DC to the circuit [33]. The circuit was shown earlier in Figure 1.14 and most CMCD work since 2001 has built on this circuit topology. The analytic work associated with CMCD has focused primarily on conduction losses and inductive switching losses for period periodic signals with 50% duty cycles [34]. In [35], equations are derived for variable duty cycle switching conditions under the assumption of independent loss mechanisms; however, the device model is based on a switch and effects of current saturation are not analyzed. Different device technologies have been used to implement CMCD circuits with most work using either GaN devices for high power amplifiers and CMOS technology of low power amplifiers. A CMOS design reported in 2011 [12] describes a fully integrated CMOS inverse class-d amplifier but the experimental results are limited to periodic pulse trains with a fifty percent duty cycle. Several research groups in Germany have conducted experimental work to realize CMCD amplifiers and evaluate the amplifier performance with pulse encoded signals [15, 16, 17]. They have also evaluated a derivative of the CMCD amplifier called class-s which includes diodes in series with the switches to prevent an off-state switch from turning on when the duty cycle is not 50%. The experimental work shows that the CMCS amplifier is not any better than CMCD, and the general consensus is that the additional losses in the diode are offset by gains in preventing off-state switches from turning on under variable duty cycle switching conditions. Also, their work has primarily focused on designing and implementing experimental circuits and evaluating the circuit performance with different types of pulse encoders including SDM. The work has not focused as much on detailed analysis and prediction of power efficiency. A summary of recent work related to CMCD and CMCS amplifiers are shown in Table

40 1.5. Literature Review Table 1.2: Some recently published results for class-d power amplifiers. Number Topology Technology Input signal Model Year Author Ref. 1 Class D (CM) GaN Sigma-delta Yes 2013 Abbasian et al [36] 2 Class D (CM) LDMOS RF PWM No 2012 Foad et al [37] 3 Class D (CM) GaN Periodic No 2012 Park et al [38] 4 Class D (CM) CMOS Periodic Yes 2012 Chowdhury et al [39] 5 Class D (CM) GaAs Periodic Yes 2011 Kamper et al [40] 6 Class D (CM) GaN Periodic No 2011 Aflaki et al [41] 7 Class D (CM) LDMOS PWM No 2010 Schuberth et al [42] 8 Class D (CM) GaN Periodic No 2009 Aflaki et al [43] 9 Class D (CM) LDMOS Periodic Yes 2009 Brackle et al [35] 10 Class D (CM) LDMOS Periodic No 2006 Nemati et al [44] 11 Class D (CM) LDMOS Periodic No 2005 Kim et al [45] 12 Class D (VM) GaN Sigma-delta No 2012 Wentzel et al [8] 13 Class D (VM) GaN Periodic No 2011 Lin et al [29] 14 Class D (VM) CMOS Sigma-delta Yes 2007 Hung et al [32] 15 Class D (VM) CMOS Sigma-delta Yes 2006 Johnson et al [6] 16 Class S GaN Sigma-delta No 2011 Wentzel et al [15] 17 Class S GaN Sigma-delta No 2010 Wentzel et al [16] 18 Class S GaN Sigma-delta No 2009 Wentzel et al [17] 19 Class S GaN Periodic No 2010 Samulak et al [18] 20 Class S GaN Periodic No 2009 Samulak et al [46] 21 Class S GaN Sigma-delta No 2008 Leberer et al [47] 24

41 1.5. Literature Review Class-F Power Amplifiers The first description of a class-f amplifier was presented by Tyler in 1958 [48]. A few years later, the first application of a high efficiency class-f power amplifier was reported by Snider [49] when he constructed and tested a 46 W, 250 MHz power amplifier for generating high power CW signals. The theory of class-f expanded in the mid-90 s by Raab in several papers where he systematically evaluated the shape of class-f waveforms related to the output termination impedances for a finite number of harmonics [50, 51, 52]. Experimental and theoretical work to optimize class-f amplifier performance has continued and reports of high power amplifiers with peak efficiencies greater than 80% in the GHz frequency range are common [19, 53, 54, 55]. Although peak efficiency is high, the power efficiency of these amplifiers reduces in a similar way to class-ab amplifiers as output power is backed off from peak power. Also, the class-b bias point that is used in class-f leads to high distortion levels. On the other hand, if the input signal to the amplifier can be conditioned to maintain operation in a highly saturated state, then class-f amplifiers offer a promising future for wireless applications. The harmonically tuned impedance networks inherent in the class-f amplifier design methodology are not likely to be optimal for continuous spectrum pulse encoded signals, so methods of implementing broadband class-f amplifiers are of great interest. Broadband amplifiers also have applications in multi-band wireless communication systems. A summary of recent work in terms of class-f amplifiers is given in Table

42 1.5. Literature Review Table 1.3: Some recently published results for class-f family PAs Number Topology Technology Power Efficiency Frequency Year Author Ref. 1 Class F GaN 40.5 dbm 78.8% 0.99 GHz 2015 Abbasian et al [56] 2 Class F GaN 40.7 dbm 80.1% 2.1 GHz 2014 Hwang et al [57] 3 Class F 1 GaN 42.2 dbm 83.9% 1.9 GHz 2014 Kim et al [58] 4 Class F GaN 40 dbm 82% 3.1 GHz 2013 Chen et al [59] 5 Class F/F 1 GaN 41 dbm 73.5% 2.65 GHz 2012 Moon et al [19] 6 Class F GaN 30.4 dbm 69% 4 GHz 2012 Zomorodian et al [20] 7 Class F GaN 10.5 W 74% GHz 2011 Carruba et al [21] 8 Class F GaAs 20 dbm 83% 0.9 GHz 2011 Carruba et al [53] 9 Class F GaN dbm 62.5% 0.9 GHz 2010 Osori et al [60] 10 Class F GaN 37 dbm 79% 1 GHz 2008 Aflaki et al [61] 11 Class F CMOS 21.8 dbm 43.9% 2.4 GHz 2006 Huang et al [54] 12 class-f 1 GaN 39.9 dbm 76.7% 3.5 GHz 2012 Dong et al [62] 13 class-f 1 GaN 47.2 dbm 69.4% 3.54 GHz 2011 Kim et al [63] 14 class-f 1 GaN 41.4 dbm 73.5% 2.5 GHz 2009 Wu et al [64] 15 class-f 1 GaN 46 dbm 60.8% 2.35 GHz 2009 Tanany et al [65] 16 class-f 1 GaN 22.7 dbm 74% 1 GHz 2006 Woo et al [66] 17 class-f 1 LDMOS 41.2 dbm 74% 1 GHz 2006 Ouyahia et al [55] 18 Class FE GaN 2.36 W 86.8% MHz 2010 You et al [67] 26

43 1.5. Literature Review RF Synchronous Rectifiers Interest in RF to DC rectification has grown recently with growing interest in wireless power systems. Although wireless power is an active research area, significant contributions began in the early 1960 s with the pioneering work of Brown [68]. He worked on high power microwave rectifying antennas, called rectennas, to remotely power a helicopter. Microwave power was also being considered as a way to distribute power on the moon and to transmit power from orbiting solar arrays to earth. These systems require very high power microwave amplifiers and highly directional antenna to collimate high power fields. Recent work has focused on much lower power level applications with interest to remotely power or remotely recharge portable devices and sensors. For these applications, the work can be broadly classified into two categories: 1) diode rectifiers and 2) synchronous rectifiers based on switching transistors [69]. RF diode rectifier circuits [70, 71, 72] are simpler to implement and avoid the design issues associated with gate drive circuitry which is required in a synchronous rectifier. On the other hand, synchronous rectifiers can also exploit advances in device technology including high efficiency GaN power devices. With clever insight, a paper in 2012 was presented by Ruiz et al. [73] where he showed the implementation of class-e RF rectifier based on reconfiguring a class-e power amplifier circuit. The RF rectifier delivered 50 mw of DC power with an efficiency of 83% at a frequency of 900 MHz. The insight for the circuit came from work presented by Hamill [74] in the early 1990 s where he showed how the theory of time-reversal duality could be applied to relate amplifier and rectifier circuit topologies. The 2012 work has led other researchers to investigate the design of synchronous RF rectifiers based on converting switch-mode amplifiers circuits into rectifiers. Other important references related to synchronous rectifiers are shown in Table 1.4. In this thesis, class-f amplifiers are reconfigured into class-f rectifiers and new contributions have been made in terms of both understanding the impact of loss in applying timereversal duality as well as the implementation of high power rectifiers and wideband rectifiers. 27

44 1.5. Literature Review Table 1.4: Some recently published results for RF synchronous rectifiers Num. Type Device f (GHz) PDC η (%) Year Author Ref. 1 class-f GaN HEMT W Abbasian et al [75] synch. 2 class-f 1 GaN HEMT W Abbasian et al [76] synch. 3 class-d CMOS mw Dehghani et al [77] synch. 4 class-c GaN HEMT W Litchfield et al [78] self-synch. MMIC 5 class-c GaN HEMT W Litchfield et al [78] self-synch. MMIC 6 class-e E-PHEMT mw Ruiz et al [79] self-synch. 7 class-e E-PHEMT mw Ruiz et al [79] self-synch. 8 class-e GaAs PHEMT mw Ishikawa et al [80] self-synch. 9 class-f GaAs PHEMT mw Ishikawa et al [81] self-synch. 10 class-f 1 GaN HEMT W Roberg et al [82] self-synch. 11 class-e E-PHEMT mw Ruiz et al [73] synch. 12 class-f E-PHEMT mw Gómez et al [83] self-synch. 28

45 1.6. Research Goals and Objectives 1.6 Research Goals and Objectives The goals of this research are: 1. to improve analytic methods to predict the power efficiency of RF switch-mode power amplifiers under general non-periodic switching conditions; 2. to build experimental prototypes of switch-mode power amplifiers to benchmark and compare the performance of different circuit topologies; 3. to investigate and evaluate new switch-mode power amplifier circuit topologies that can efficiently amplify pulse encoded signals. The research goals are derived from the literature survey where the following observations are made. First, there are many published experimental results that demonstrate high efficiency operation for classes D, E and F; however, these results are almost always reported under optimal switching conditions which correspond to a square wave drive signal with a 50% duty cycle. The power efficiency of switch-mode amplifiers degrades as the duty cycle deviates from 50% and it is very important to understand how power efficiency changes as the duty cycle (pulse width) changes in order to predict how well an amplifier will work for wireless communication applications. Second, although there are many reports on different switch-mode power amplifier circuits, it is not always that easy to compare results because different devices are used in different circuit topologies and the objectives of the work have not been to conduct comparative studies. In this work, amplifier circuits are analyzed and evaluated using the same device to improve the consistency of experimental work and to draw conclusions by comparing experimental results. Third, despite the high efficiency potential of RF switch-mode power amplifier circuits, a competitive digital switch-mode power amplifier has yet to be reported compared to conventional analog amplifier techniques such as Doherty [1]. Therefore, it still remains a challenge to realize high efficiency switch-mode power amplifiers. This suggests that research must continue to evaluate new switch-mode power amplifier architectures as a way to realize the full potential of high efficiency operation that can theoretically be obtained by operating the device as a switch. In pursuit of these research goals, specific research objectives are defined Predicting the Power Efficiency of CMCD Power Amplifiers for Time Encoded Input Signals As Table 1.2 shows, many publications have been written about CMCD; however, a careful review of published work reveals the following limitations: Most authors have focused on building and measuring the performance of CMCD amplifier circuits to present experimental results without providing an analytic model to predict and explain the experimental outcomes. Some researchers have presented analytical models; however, the models are usually restricted to periodic input signals with fifty percent duty cycle. The peak current which the device can deliver in the saturation region is never considered. The device models are usually simple switches with an on-state resistance that has no current limitations. 29

46 1.6. Research Goals and Objectives The output capacitance of the device is constant. However, most device capacitances are nonlinear and capacitance can vary significantly under large signal conditions. Inductive switching losses associated with bond wires and the packaging are considered to be a significant loss mechanisms in CMCD amplifiers, while capacitive switching losses are usually neglected. Analytical results in Chapter 2 show that capacitive switching losses can in fact be very significant under variable duty cycle switching conditions. Overlap losses have not been modeled; however, in practice rise time and fall times of the voltage and current waveforms for the switches are significant. Improving analytical models to predict power efficiency in CMCD amplifiers for general switching conditions is a research objective. The analysis gives insight into the loss mechanisms as a function of the duty cycle as well as insight into how to appropriately select the device load line considering current saturation in the switch. This work is described in Chapter RF Switch-mode Power Amplifiers with Energy Recycling As the experimental results of the published work show, it is difficult to obtain high efficiency operation when amplifying pulse encoded signals. One of the reasons for this is that the spectrum of the pulse encoded signals is broadband and continuous rather than harmonically peaked. Also, the quantization noise is shaped to create a narrow noise well and consequently a reconstruction filter with sharp attenuation characteristics is required to suppress out-ofband noise. Highly selective filters have multiple resonators and are more complex than a simple resonator. The filters are usually added after the amplifier circuit design and as a result the out-of-band impedance presented to the device is rarely controlled in a predictable way. If the required out-of-band impedance is violated, then the high efficiency operation of the amplifier is compromised. As shown in Figure 1.21, all the amplifier classes can be related to specific harmonic impedance conditions. Time encoded signals are challenging signals to amplify because they have continuous power spectrums and are different from periodic signals that have discrete harmonic frequency components. A different approach to implementing RF switch-mode amplifiers was presented in [84] where the output load circuit across the switch is broadband rather than harmonically tuned. The load circuit was implemented by a complementary diplexer which has a matched broadband input port that splits into two complementary filter branches that separate the amplified pulse train into an in-band signal and an out-of-band (quantization noise) signal. After signal separation, the in-band signal couples to the antenna and the out-of-band signal can be rectified. The rectified output power can provide an auxiliary supply which offsets the DC power supplied to the amplifier. In this way, out-of-band power is recycled to improve the power efficiency of the amplifier. A diagram of a switch-mode power amplifier with energy recycling was shown in Figure 1.1. RF energy recycling has been reported for another power amplifier architecture called linear amplification using nonlinear components (LINC), but the concept is new in terms of its application to RF switch-mode power amplifiers. Energy recycling is motivated by the observation that when high PAPR signals are encoded into a pulse train, the coding efficiency of the pulse train is low, and large amounts of power are generated in the out-of-band frequency spectrum. Therefore, two approaches to the design of an efficient switch-mode power amplifier are: 1) to design a circuit that inherently operates 30

47 1.6. Research Goals and Objectives with high efficiency even for pulse trains with broadband spectrums, or 2) design a high efficiency broadband amplifier and use energy recycling to capture out-of-band energy and use this to offset the DC supply to the amplifier. The second method is investigated in this work. The concept of energy recycling is evaluated in detail and supported by experimental results. The work is described in Chapter RF Rectifier Circuits If energy recycling is to be implemented in a RF switch-mode power amplifier, a fundamental circuit block that must be designed is the RF rectifier. RF rectification has become increasingly important especially in terms of research related to the development of wireless power technology. In wireless power, RF signals are transmitted to a remote device, for example a sensor, and the remote device rectifies incident RF power to autonomously power the device or recharge a battery in the remote device. The research is motivated by the need for remote systems that never need to be serviced and the devices can be embedded into structures where access is difficult or impossible to replace batteries. Therefore, although the motivation in this work is to design RF rectifiers for energy recycling in switch-mode power amplifiers, the work contributes to a broader effort focused on implementing efficient RF rectifiers for wireless power applications. In a very interesting paper presented by Hamill in 1997, he showed how switch-mode power amplifiers can be time reversed to operate as rectifiers. The work was motivated by the design of power electronics circuits where he showed how time-reversal duality theory can be applied to unify the design of inverters (amplifiers) and rectifiers. The application of time-reversal duality to the design of RF rectifiers is quite recent with the first reported work in [73]. Since this research began with a focus on RF switch-mode power amplifiers, the implementation of synchronous RF rectifiers based on time-reversal duality is a natural extension. Similar to switch-mode power amplifiers, the theory and analytic support for RF synchronous rectifiers continues to evolve. This work contributes to the design of RF rectifiers in terms of both analysis and experimental work by investigating the following points. When there is significant power loss, there is an ambiguity in how the amplifier and rectifier circuits should be compared in the context of time-reversal duality. Hamill s original work has been applied to lossless circuits, and the implications of loss are considered. The power efficiency of a class-f amplifier and the corresponding rectifier dual are analyzed and compared experimentally. The results show that the rectifier has slightly higher power efficiency and reasons for the difference are given. The power efficiency of RF rectifiers is dependent on the DC load impedance. The relationship between power efficiency and load resistance is investigated both analytically and experimentally. The class-f and class-f 1 synchronous rectifiers are compared to clarify which of these configurations is better in terms of power efficiency and dynamic range. A wideband class-f 1 synchronous rectifiers is designed and implemented experimentally. This is the first report of a wideband RF rectifier design based on time-reversal theory applied to a wideband class-f 1 synchronous rectifier. 31

48 1.6. Research Goals and Objectives The analysis and experimental results of different class-f RF rectifiers is described in Chapter Class-F and Class-F 1 Power Amplifiers In this research, class-f type amplifiers are used for both switch-mode amplifiers and RF synchronous rectifiers. Therefore, a chapter in this work is dedicated to the design of class-f amplifiers. In carrying out the detailed analysis of class-f circuits and reporting on experimental results, effort has been made to contribute to a deeper understanding of these circuits. Two contributions are made. First a detailed study of the importance of input harmonic matching is made in terms of the relationship between input match and power efficiency. The work builds on other published contributions and shows that second harmonic input matching is very important, while third harmonic input matching provides diminishing improvements in power efficiency. Second, unified experimental work is shown that provides results for comparing the performance of both class-f and Class-F 1. The conclusion is that current switched Class-F 1 amplifiers are better than voltage switched class-f amplifiers in terms of power efficiency and dynamic range. Chapter 3 describes the details of the class-f amplifier design work and the results are used to compare with class-f rectifier circuits in Chapter Supporting Publications Some parts of this research work have been previously published in journals and conferences as listed below. 1. S. Abbasian and T. Johnson, RF current mode class-d power amplifiers under periodic and non-periodic switching conditions, in IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp L. Xiao, S. Abbasian, and T. Johnson, All-digital encoders for RF switch-mode power amplifier applications, in IEEE Wireless and Microwave Tech. Conf. (WAMICON), Jun. 2014, pp S. Dehghani, S. Abbasian and T. Johnson, Tracking load to optimize power efficiency in RF to DC rectifier circuits, IEEE Wireless Power Transfer Conference (WPTC), Boulder, Colorado, U.S.A., pp. 1-3, S. Abbasian and T. Johnson, High efficiency and high power GaN HEMT inverse class-f synchronous rectifier for wireless power applications, in European Microwave Conference (EuMC), Paris, France, Sep S. Abbasian and T. Johnson, High efficiency GaN HEMT class-f synchronous rectifier for wireless applications, IEICE Electronics Express, vol. 12, no. 1, pp. 1-11, S. Abbasian and T. Johnson, Effect of second and third harmonic input impedances in a class-f amplifier, Progress In Electromagnetics Research C, Vol. 56, pp , Also another journal article is under review and a second article is in preparation. 32

49 1.7. Thesis Outline S. Dehghani, S. Abbasian and T. Johnson, Adjustable load with tracking loop to improve RF rectifier efficiency under variable RF input power conditions submitted to IEEE Trans. Microwave Theory Tech., Jun S. Abbasian, L. Xiao, and T. Johnson, Energy recycling in RF power amplifiers, in preparation for IEEE Trans. on Circuits and Systems II. 1.7 Thesis Outline A roadmap of this thesis was given in Figure 1.1. Chapter 2 describes analysis and modeling of a CMCD power amplifier circuit with focus on predicting power efficiency for nonperiodic pulse trains. Chapter 3 describes the design of class-f and class-f 1 power amplifiers. In Chapter 4, the class-f amplifiers in Chapter 3 are reconfigured as RF synchronous rectifiers using the theory of time-reversal duality. Chapter 5 presents theory and experimental results for a switch-mode power amplifier with energy recycling. Conclusions and future work are presented in Chapter 6. 33

50 Chapter 2 Power Efficiency Analysis of RF Current Mode Class-D Amplifiers In this chapter, the power efficiency of RF current mode class-d (CMCD) amplifiers are analyzed for a general class of time encoded signals. Time encoded signals are continuoustime signals with only two amplitude levels. Consequently, a time encoder maps an input source signal, such as a modulated carrier, into a binary amplitude pulse train where all the source information is contained in the timing of the amplitude changes in the signal. In this way, time encoding is similar to frequency modulation. Time encoded signals are suitable for amplification in RF switch-mode amplifiers such as CMCD providing the encoders synthesize signals which have a power spectrum that is compatible with signal reconstruction using an output bandpass filter. Examples of time encoded signals which meet these requirement are bandpass sigma-delta modulated signals and noise shaped pulse position modulation. Although papers have been published which analyze the power efficiency of CMCD amplifiers, the input signal in most cases is assumed to be a periodic signal with a 50% duty cycle [12, 34, 85, 86]. The 50% duty cycle switching condition in class-d is the optimal switching condition that minimizes loss and maximizes output power; however, it does not give insight into the amplifier power efficiency for a modulated source signal. In other work, equations have been derived for variable duty cycle switching conditions under the assumption of independent loss mechanisms [35] and for unconstrained peak current conditions that are typically encountered in practical devices. Therefore, the limitations of existing work motivates a more comprehensive power efficiency analysis of the CMCD amplifier under general switching conditions that are typical for time encoded signals. This chapter expands the analysis of power efficiency to include capacitive switching losses associated with the effective output capacitance of the device under variable duty cycle switching conditions. Power efficiency equations are derived to model conduction losses, inductive switching losses, capacitive switching losses, peak current limits (I max ), and overlap losses during switch transitions. The analysis under variable duty cycle switching conditions is verified with a simulation in Keysight s ADS software using large signal device models for a CMCD amplifier with two 15 W Cree GaN power devices. Circuit simulations using time encoded signals are also compared with the analysis. Conclusions show that capacitive switching losses normally assumed to be negligible in CMCD circuits can be significant under back-off conditions from peak power. Also, the selection of the load line must consider the minimum and maximum pulse widths of the switching signal to control power loss under variable duty cycle switching conditions. 1 Parts of Chapter 2 have been published in an article. Reprinted with permission from IEEE [36]. 34

51 2.1. The Current Mode Class-D RF Amplifier 2.1 The Current Mode Class-D RF Amplifier A circuit diagram for a CMCD amplifier is shown in Figure 2.1. The circuit consists of two devices, M 1 and M 2, which are switched by a pair of complementary pulse trains, V s1 and V s2. The pulse trains can be either a periodic signal such as a square wave or more generally a non-periodic pulse train which has an encoded source signal such as a modulated carrier. The currents, i sw1 and i sw2, form a pair of differential switched current signals. The differential current is filtered by a parallel tank circuit (L T and C T ) which is anti-resonant at the carrier (fundamental) frequency. Harmonic or out-of-band current components are shorted by the tank and the fundamental frequency component or in-band current components are delivered to the load. v L Node A R L C T Node B L T i sw1 L DC1 L DC2 R s1 I DC M 1 M 2 i sw2 R s2 V s1 VDD V s2 Figure 2.1: A CMCD circuit. In this chapter, a CMCD amplifier design is analyzed for a circuit which uses Cree GaN power devices for the switches. The devices are 15 W unpackaged die, model CGH60015D. Although Cree provides a comprehensive large signal model for this device, the model is proprietary and the details of the intrinsic devices are not available to the user. The Cree model is like a black box with terminals for the gate, drain and source, and cannot be used for analysis. Therefore, equivalent circuit models which capture the primary behaviour of the devices are very useful to gain insight into the design of the CMCD amplifier and analyze the contribution of different loss mechanisms to the overall power efficiency of the amplifier. 2.2 Device Models Three levels of device models are identified to support analytical and simulation results for CMCD amplifier circuits. The level 3 model described below is also used extensively in later chapters related to the design of class-f amplifiers. The models are described in the following sections. 35

52 2.2. Device Models Level 1 The level 1 model is the most commonly used model in the analysis of CMCD amplifier circuits. Many literature references can be found for this type of model and the associated analysis of the class-d amplifier under periodic switching conditions [87, 41]. In the level 1 model, the device is modeled as a switch with an on-state resistance R on and an infinite off state resistance R off. The switch changes states instantaneously in accordance with an amplitude transition in the gate drive pulse train. Power loss associated with dissipation in the on-state is modeled and called conduction loss, P Ron. The equivalent on-state resistance for the device model is obtained from an approximation of the DC IV characteristics for the device. In the on-state, the current is constrained to operate in the linear region of the device at or below the knee point, the point which separates the linear and saturation regions of the device IV curve. An example of the knee point and the on-state resistance approximation are shown in Figure 2.2. As will be shown later, the linear on-state resistance model can lead to analytic results that are less accurate especially for cases where the input pulse train is periodic and the duty cycle is not 50%. A schematic diagram of a CMCD amplifier using a level 1 device model is shown in Figure 2.3. Figure 2.2: Typical DC IV characteristics for a GaN device. The level 1 model can also include device capacitances and inductances. A fixed output capacitance, C out, models the total effective output capacitance of the device and the capacitance can be added to shunt the switch. Since device capacitances are nonlinear, the output capacitance is the effective output capacitance at the drain node and includes contributions from C ds and C gd. In Figure 2.3, the effective device capacitances are modeled by C 1 and C 2. 36

53 2.2. Device Models Figure 2.3: Schematic for current mode class-d power amplifier with a level 1 device model (ADS schematic). 37

54 2.2. Device Models As is well-known, one of the advantages of the CMCD amplifier is that there is zero-voltage switching across the devices providing the gate pulse train in a periodic square wave with a 50% duty cycle. This means that with a 50% duty cycle there are ideally no switching losses associated with the discharge of C out. Further, the output capacitance of the two switches shunts the differential tank circuit with an equivalent capacitance of C out /2 and the tank capacitance C T can be modified to compensate for the additional shunt capacitance. When the duty cycle is not 50%, the zero-voltage switching is no longer valid and there is stored charge in C out that must be dissipated during the switching transition. An example of the current and voltage waveforms at the drain terminals of the devices for a duty cycle of 30% is shown in Figure The analysis of power loss associated with the discharge of C out for non-zero voltage switching conditions in CMCD is presented later in Section (2.3). The power loss associated with the discharge of C out is denoted as P cap. Another power loss mechanism that is commonly analyzed for CMCD circuits is the power loss associated with series inductance in the switch, L s. The inductance is primarily associated with the drain inductance on the die and in the package. Because current is hard-switched in the CMCD circuit, stored energy in the inductor is dissipated each time the switch opens. The inductance also leads to voltage spiking when the switch changes state, because the current cannot instantaneously change through the inductance. For a periodic gate signal with a fundamental frequency f o, the corresponding power loss from the inductor, called P ind, is L s IDC 2 f o. The equation models the power loss in the two switches where the switched current has an amplitude of I DC, the total DC current into the CMCD circuit (see Figure 2.1). Typically, inductive switching losses are low because the device and package design minimize series inductance. The magnitude of inductive power loss relative to other loss mechanisms is compared later in section (2.3.6). In summary, the level 1 model is appropriate for independently calculating the power loss associated with the on-state resistance (P Ron ), capacitive switching losses (P cap ), and inductive switching losses (P ind ). Considering these power loss mechanisms, the overall drain efficiency of the CMCD amplifier is η = P L (2.1) P DC where P L is the power delivered to the load resistor R L and the DC power is P DC = P L + P Ron + P cap + P ind. (2.2) 2 This figure was shown earlier in Figure 1.15 and is repeated for convenience of reference. 38

55 2.2. Device Models Figure 2.4: Level 1 CMCD current and voltage waveforms for a 30% duty cycle periodic drive signal. 39

56 2.2. Device Models Level 2 Although the level 1 model is used in many papers for analyzing CMCD circuits, it has limitations especially under more general switching conditions including arbitrary duty cycle periodic switching and non-periodic switching. Since the primary application of CMCD amplifiers in this research is to consider this amplifier as an efficient means of amplifying wireless signals, it is necessary to consider how the CMCD works under general switching conditions when the input signal is an encoded pulse train. The level 2 model extends the analysis of the CMCD circuits and includes the following features. 1. An important loss mechanism in switch-mode power amplifiers is the loss created from non-ideal switching waveforms which have finite switching times. During the switching interval, of duration τ, the current and voltage waveforms across the device overlap which leads to power dissipation in the device. An example of the drain current and drain voltage waveforms which include overlap loss are shown in Figure 2.5. In the level 1 model, switching is assumed to be instantaneous and overlap power loss is zero. In level 2, overlap power loss, denoted as P τ is included in the calculation of the overall power efficiency of the amplifier. The overall DC power for the CMCD amplifier with overlap loss is P DC = P L + P Ron + P cap + P ind + P τ. (2.3) which can then be used in equation (2.1) to calculate the drain efficiency for the amplifier. 2. When the duty cycle for a periodic input signal is not 50%, then the average current carried by each switch is no longer equal to I DC /2. This means that one switch carries more current than the other. If a CMCD amplifier is designed using the assumption of a 50% duty cycle condition which is often done, then current saturation in one of the switches can appear if the load line is selected for maximum power. Consequently, margin must be allocated in a CMCD design to consider the variation in pulse width (duty cycle) to ensure that current saturation is avoided as this will significantly increase the dissipation in the amplifier. An analysis with a level 1 model does not include any current saturation limitations as the on-state resistance is an ideal resistor. In level 2, current saturation is modeled which constrains the peak current and models the limitation of a practical device where the peak switch current cannot exceed I max, the maximum device current at saturation. 3. The effective output capacitance of the device is in general a nonlinear function of the gate and drain voltages. Since often during a switching period the device is either in the on-state or the off-state, the output capacitance model can be modified to include an on-state capacitance C on and an off-state capacitance C off. A time averaged capacitance between the on and off state capacitances can then be used to analyze capacitive switching losses under arbitrary duty cycle switching conditions. The level 2 model is shown in Figure 2.6. The model is partitioned into two states, onstate and off-state, and includes current saturation and different on-state and off-state switch resistances and switch capacitances. The model also assumes that current and voltage overlap for a state transition interval time of τ. 40

57 2.2. Device Models Drain Current (A) Time (ns) Drain Voltage (V) Figure 2.5: Transition time (τ =0.15T ) for a CMCD with Cree CGH60015D transistors. The model values used for the Cree CGH60015D are summarized in Table 2.1. The values were extracted from the Cree large signal device model by measuring the S-parameters in the on and off state. The on state corresponds to a gate voltage (V gs,on ) of 0 V, the off state corresponds to a gate voltage (V gs,off ) of -4 V, and the DC supply voltage V DD is 25 V. S-parameters for a frequency range of 10 MHz to 2.5 GHz were fitted to the simplified model to minimize the mean square error. A comparison of the S-parameters for the level 2 model versus the S-parameters obtained for the Cree large signal model are shown in Figure 2.7. As shown, the level 2 model matches well with the Cree model. Table 2.1: Summary of level 2 model values for the Cree CGH60015D die. R on C on C off L s 2 Ω 1.8 pf 0.5 pf 250 ph Level 3 Level 3 is a simulation model that is implemented to independently include and control nonlinear device capacitances. The model includes a current generator that models the DC IV characteristics, nonlinear device capacitances for C gs, C gd, and C ds, series inductance in the drain, and gate resistance. The model is implemented in ADS and used for circuit simulations to compare with analytic results. The simulation model is referenced much more in the next chapter and additional details are given there. 41

58 2.2. Device Models d g d s d L d ON state L d OFF state V gs,on g I sat R on d C on V gs,off g τ d R off C off s s Figure 2.6: Level 2 device model for a CMCD amplifier. +j1.0 +j0.5 +j2.0 +j0.2 S22 ON-State: Model S22 ON-State: Device S22 OFF-State: Model S22 OFF-State: Device +j j0.2 -j5.0 -j0.5 -j2.0 -j1.0 Figure 2.7: S-parameters for the on and off state for a Cree CGH60010D device. 42

59 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching 2.3 Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching The level 2 device model is used to analyze the power efficiency of a CMCD amplifier for a periodic switching signal. For the analysis, the periodic signal has a period T and a duty cycle α. An example gate drive waveform is shown in Figure 2.8. The analysis works through the following steps. First, equations for the DC supply voltage and supply current are derived for an arbitrary duty cycle. The analysis shows that the minimum DC current corresponds to a duty cycle of 50% and increases for non-50% duty cycle conditions. The DC analysis also provides guidelines on how to select an appropriate load resistance for an arbitrary duty cycle. The power loss associated with the discharge of the output capacitance is analyzed next. The analysis shows that capacitive switching losses are not negligible for duty cycles which vary significantly from 50%. Conduction, inductive and overlap loss mechanisms are also analyzed. Finally, a comparison of analytic versus simulated results is made for each of the loss mechanisms. Amplitude α 0 T 2T 3T Time Figure 2.8: Signal with period T and variable duty cycle (α) Selecting the DC Supply Voltage The constraints on the DC supply voltage V DD for the CMCD amplifier are determined by the drain-source breakdown voltage of the device, V ds,bd, and the maximum amplitude of the load voltage, V max. For a periodic switching signal, the maximum load voltage corresponds to a duty cycle of 50% and the voltage across the device (switch) is a half sinusoid. The expected value of the drain voltage is equal to the DC supply voltage. Therefore, for a 50% duty cycle V DD = V max (2.4) π with the constraint that V max must be less than the breakdown voltage. For the Cree CGH60015D, the breakdown voltage is 84 V, and a DC supply voltage of 25 V is selected. From (2.4), the peak amplitude of the load voltage is 78.5 V which leaves a margin of 5.5 V relative to the breakdown voltage. The relative values of the DC supply voltage, the maximum switch voltage, and the breakdown voltage are shown for a typical device in Figure

60 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Load Power Let s now consider the relations between the DC current, I DC, supplied to the CMCD circuit and the peak amplitude of the load current, I om, to estimate load power, P L. With reference to the drain current waveforms in Figure 2.4, the amplitude of on-state switch current is equal to I DC. Since the drain current waveforms are periodic square wave signals with a duty cycle of α, they can be expanded into a Fourier series. The corresponding peak amplitude of the load current is then equal to I om = 2 π I DC sin(απ). (2.5) Once the peak output load current is found, an expression for the load power can be written as P L = 1 2 R L I 2 om (2.6) Equations (2.5) and (2.6) can also be combined to show the relationship between duty cycle and load power: P L = 2 π 2 R L I 2 DC [sin(απ)] 2. (2.7) From the last equation, it is clear that load power is a function of the load resistance, the current switched by the transistors, and the duty cycle of the periodic signal. Load power is maximized for a 50% duty cycle and power reduces as the duty cycle moves away from 50%. By changing duty cycle, load power changes, and therefore duty cycle can be used to control the amplitude of the load signal Power Loss Mechanisms The level 2 device model includes output capacitance, inductance, and finite switching time, and the current waveforms at the device terminals are modified compared to the ideal class D switched current waveforms. An example of a typical drain current waveform including additional losses is shown in Figure 2.9. When switch 1 (M 1 ) is on, the output capacitance of the device is essentially shorted by the low on resistance of the device (see Figure 2.6 for the level 2 device model). Therefore, the on-state device capacitance, C on, is negligible and loss is primarily associated with switching current through the series lead inductance L s. On the other hand, when M 1 is on, M 2 is in the off-state, and the off-state capacitance, C off, shunts the drain-source terminals of the switch. The voltage across C off must be charged to track the voltage at node B (see Figure 2.1). The energy required to charge C off must be supplied by M 1 and this leads to an additional current component that is superimposed on the drain current flowing into switch 1. The drain current waveform through switch 1 including C off is given by i sw1 (θ) = I 1 (θ) I Roff (θ) I Coff (θ) (2.8) where θ = ωt and I 1 (θ) = I DC (θ/τ) 0 < θ < τ I DC τ < θ < 2πα + τ 2πα + 2τ θ I DC 2πα + τ < θ < 2πα + 2τ τ 0 2πα + 2τ < θ < 2π (2.9) 44

61 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching I Roff (θ) = V om R off sin(θ) (2.10) I Coff (θ) 4 π ωc off R p I DC sin(απ) sin(τ/2) τ cos(θ). (2.11) In these equations, R p = R L R off ; however, R off is usually much greater than R L, thus R p R L. Also, the current through C off is calculated from the derivative of the voltage across the switch with respect to time. Figure 2.9: Device current waveforms at the drain terminal of the switching device. The ADS simulation results are for a Cree large signal device model. The peak amplitude of the load current, I om, which flows through the load resistance R L is found by calculating the amplitude of the fundamental frequency component of the drain current given in (2.8). From a Fourier series analysis of the pulse train, the peak amplitude of the load current is where R p I om = A 2 + B 2 (2.12) A = 2 I DC [sin(d) sin(τ/2)] sin(τ/2) I Coff π R L τ (2.13) B = 2 R p I DC [cos(τ/2) cos(d)] sin(τ/2) π R L τ (2.14) and D = 2πα + 3τ/2. The current component I Coff associated with charging C off is small relative to the amplitude of the load current. Therefore, the expression for I om can be simplified to I om = 4 π I DC sin(απ + τ/2) sin(τ/2). (2.15) τ 45

62 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching As a check on equation (2.15), consider the limit as τ 0. In the limit, overlap reduces to zero and the current waveform simplifies to the ideal CMCD waveform where I om = 2 π I DC sin(απ). (2.16) When overlap loss is not negligible, as in a practical CMCD design, the peak load current is reduced by the finite rise and fall times of the switched current waveform. The power losses associated with on-state conduction loss and the charging of the off-state switch capacitance are [ 1 π ] P Ron = 2 R on (I DC I Coff (θ)) 2 dθ 2π 0 = R on I 2 DC R on max(i Coff ) 2. (2.17) There is also power loss associated with non-zero voltage switching for duty cycles which are not 50%. During an off to on state transition, the output capacitance of the off state switch must be discharged. The capacitance is nonlinear, and as an estimate of the power loss during the transition, the average drain source capacitance is used: C ds = (C off + C on )/2. The corresponding power loss is given by [35] P cap = 2f o C ds [ πvdd cos(απ) sin(απ) ] f o C ds R L cos 2. (2.18) (απ) Overlap loss during a switch transition is defined as the power loss associated with the cross-over of the drain current and drain voltage waveforms. Using a linear approximation for the amplitude transitions as shown in Figure 2.10, the overlap loss is estimated as [ 1 P τ = 2 2π [ 1 = 2 π [ 1 = 2 π 2π 0 π 0 π 0 ( θ I DC τ ( I DC θ τ ) ( ) τ θ U 0 τ ) ( ) ] τ θ U 0 dθ τ τθ θ 2 I DC U 0 τ 2 dθ ] ] dθ = I DC 3π U 0 τ. (2.19) where U 0 = V om cos(απ) τ and V om is the peak amplitude of the load voltage. The peak amplitude of the load voltage is equal to I om R L, and using the approximation for I om given in (2.16), V om (2/π) R L I DC sin(απ). Therefore, the overlap power loss can be expressed more compactly as P τ τ 3 cot(απ) P L. (2.20) The last power loss mechanism considered in this analysis is the power loss associated with the discharge of energy stored in the series inductance, L s. The fundamental frequency of the switching waveform is f o and the on-state current is I DC. The stored energy is discharged twice per cycle because there are two switches. Therefore, the inductive switching loss is P ind = L s I 2 DC f o. (2.21) 46

63 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching V om U 0 I dc τ 2απ 2απ + 2τ θ Figure 2.10: Overlap of drain current and drain voltage waveforms in a CMCD amplifier. The sum of all the power losses and the load power must equal the DC power supplied to the amplifier: P DC = P L + P Ron + P cap + P τ + P ind. (2.22) Analytical expressions have been derived for each term in the preceding analysis, and therefore the overall drain efficiency of the CMCD under periodic switching conditions can be found using η = P L P DC = Selecting a Device Load Line P L P L + P on + P cap + P τ + P ind. (2.23) An important design step in any amplifier design is to select the appropriate load line for the amplifying device. In power amplifier design, this almost always means maximizing load power and maximizing power efficiency. The load line for the CMCD amplifier is discussed next. The analysis begins by considering conduction loss, then comments are made about how the load line is adjusted for other losses. The total DC power supplied to the amplifier is equal to the sum of the load power and the losses in the circuit. The switches in a CMCD amplifier switch a current I DC, and the corresponding conduction power loss is R on IDC 2. The DC power supplied to the amplifier is equal to V DD I DC. Therefore, P DC = V DD I DC = P L + P Ron = P L + R on I 2 DC. (2.24) Using the expression for P L in equation (2.7), (2.24) can be rearranged to solve for I DC : I DC = V DD. (2.25) 2 π 2 R L sin 2 (απ) + R on A few remarks are made about this equation. First, the equation shows that DC power is a function of duty cycle. The DC current is lowest for a 50% duty cycle (α = 0.5), and DC current increases for non-50% duty cycles. Second, although the equation shows a 47

64 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching relationship between the load resistance and the DC supply current, the maximum DC current is constrained by the device characteristics. If the maximum saturation current for the device in the on-state is I max, then I DC I max. In a level 1 model (see Figure 2.4), the device is modeled as a simple switch without current saturation. If this circuit is simulated to evaluate power efficiency as a function of duty cycle, incorrect conclusions can be made because there is no current saturation function in the model. The level 2 model adds current saturation and ensures that unrealistic device currents are not generated in the simulation for arbitrary duty cycles. An important consequence of the variation of the switch current (I DC ) as function of duty cycle is that a CMCD design must consider the range over which duty cycle will vary. The 50% duty cycle switching condition is a commonly used benchmark in CMCD amplifiers because this corresponds to maximum power and maximum efficiency. On the other hand, a design optimized at 50% duty cycle is not optimal for a design which must amplify signals with variable duty cycle. Margin must be allocated to ensure that the duty cycle limits do not create switch currents that exceeds I max, otherwise the power efficiency of the amplifier will be severely reduced because the switch current pushes past the knee and deep saturation can occur. These points are illustrated in Figure In this figure, a DC current (switch current) called I o is defined to correspond to an operating point with 50% duty cycle. Evaluating equation (2.25) for α = 0.5 gives I o = V DD. (2.26) 2 π 2 R L + R on For variable duty cycle switching conditions, the 50% duty cycle switching current I o must be less than I max. As an example, suppose the duty cycle switching range in the input pulse train is constrained to a range from 30-70%. To avoid deep saturation at the end points of the duty cycle range, the load resistance is selected for the 30% duty cycle, or equivalently the 70% duty cycle point, such that I DC is equal to I max. If the duty cycle exceeds the design range, then the device becomes deeply saturated. The limiting case for saturation is when α = 0, or α = 1, which corresponds to one switch closed and one switch open. Under these conditions, the on-state device is pinned at I DC = I max and V DS = V DD, and all the DC power is dissipated in the switch no power is delivered to the load since the switches are not switched. The preceding discussion implicitly links the choice of the load resistance R L to a condition that constrains I DC to be less than or equal to I max for the limits of the duty cycle range in the pulse train. Another way to visualize the relationship between R L, load power, and power efficiency is shown in Figure With reference to equation (2.7), load power depends on the load resistance, the DC current supplied to the circuit, and the duty cycle. Additionally, we have equation (2.25) which shows that I DC varies as a function of duty cycle. The two equations can be combined to rewrite load power as P L = 2 π 2 R L [ V DD 2 π 2 R L sin 2 (α π) + R on ] 2 sin 2 (α π) (2.27) If conduction losses were zero, then P L would be proportional to V 2 DD /R L for a fixed duty cycle α which is intuitively satisfying. Equation (2.27) is more general and includes conduction losses, but it still leads to an inverse relation between load power and load resistance, as shown 48

65 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching I DS Load Line α = 0.3 α = 0 V gs,on I max I 0 α = 0.5 V gs,off 0 0 V DD V max V ds,bd V DS Figure 2.11: DC IV operating region for a CMCD amplifier including margin for duty cycle variation. by the dashed green line in Figure Note that the relations in the figure are plotted for a specific value of duty cycle; in this figure, α = 0.5. The figure also includes the corresponding power efficiency for the CMCD amplifier as load resistance varies. Using the expression for P L and P DC it is easy to show that the drain efficiency is η = 1 + π (2.28) R on csc 2 (απ) R L The solid blue trace in Figure 2.12 shows that power efficiency increases as load resistance increases, albeit with diminishing gains in efficiency as R L gets large. Although equation (2.27) shows how load power varies as function of load resistance, it is derived from a level 1 device model and depends on the on-state resistance, R on. A direct application of the equation cannot be used for a practical device without coupling it with a constraint on the maximum device current, I max. In order to determine the range of load resistance that can be used with the device, a second trace is added to the graph to add the I max constraint. Returning to equation (2.7), the maximum value of I DC that is possible with a physical device is I max. If I DC = I max, then P L = (2/π 2 )I 2 max sin 2 (απ) R L which gives a linear bound for P L as a function of R L for a specific duty cycle. A plot of this bound is shown as the dashed red trace in Figure The constrained load resistance range is the segment of the dashed green curve that lies to the right of the intersection of the two lines. The range is highlighted by a thick black line. The point where the dashed red and dashed green lines intersect is the resistance which maximizes load power, and for the data shown in the figure, the optimum load resistance is 45 Ω. Therefore, the addition of the constraint that I DC I max with equation (2.27) leads to analytic results which are consistent with the level 2 model that includes current saturation in the switch. Capacitive and inductive switching losses would lead to further adjustment in the final value of load resistance, but equation (2.27) provides a good choice to begin optimizing a CMCD design. As a final note, in a practical design, equation (2.27) should be evaluated 49

66 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Efficiency (%) Power (W) Load Resistance (Ω) Figure 2.12: Efficiency and output power of a CMCD as a function of load resistance (α = 0.5). for the endpoints of the duty cycle range which is in the pulse train, since I DC increases for non-50% duty cycles. An example is given in Figure 2.13 for a 30% duty cycle, and compared to the 50% duty cycle case, the optimum load resistance is increased to approximately 65 Ω Efficiency (%) Power (W) Load Resistance (Ω) Figure 2.13: Efficiency and output power of a CMCD as a function of load resistance (α = 0.3). 50

67 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Current Saturation Model As discussed in the previous section, a variable duty cycle periodic pulse train leads to a range of on-state switch currents that fall in the range from I o to I max. Over this range, the device is transitioning from the linear region to the saturation region and an improved model can be used to predict how I DC changes as duty cycle changes. The transition region is highlighted in Figure 2.11 and can be modeled by the following equation I DC I max (I max I o ) exp(4 [1 csc(απ)]). (2.29) The exponential function is scaled such that it is consistent with the approximation that e 4 0, and the function provides a smooth transition from I o to I max. An example of how this function models the change in I DC as a function of duty cycle is shown in Figure Figure 2.14: DC device current as a function of sin(απ) (α is duty cycle) Analytical versus Simulated Results The analytical theory which has been developed for the CMCD amplifier is now used to compare the predicted power efficiency of the amplifier with simulation results. For the comparison, a CMCD amplifier is designed using the Cree CGH60015D GaN HEMT. The schematic diagram of the circuit is the same as the circuit shown in Figure 2.1 and the component values are given in Table 2.2. A summary of the analytical results of different power loss mechanisms versus duty cycle is shown in Figure The analytical results are compared with simulation results obtained using the Cree large signal device model. For the simulated results, load power and DC source power can be measured but no further details on the breakdown of individual loss mechanisms can be isolated from the simulation results. This is where analytical results provide additional insight, and the relative magnitude of different power losses can be compared. Conduction losses and inductive switching losses are relatively insensitive to changes in duty cycle. On 51

68 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Table 2.2: CMCD Design Values Switches M 1 and M 2 Cree CGH60015D Driver resistance R drv 5 Ω Drain supply voltage V DD 25 V Off-state gate voltage V gs,off -4 V On-state gate voltage V gs,on 0 V Saturation current I max 2.3 A Duty cycle range (α) 30-70% 50% duty cycle switch current I o 1.7 A Equivalent on-state resistance R on 2 Ω Load resistance R L 65 Ω Fundamental switching frequency f o 1 GHz Drain bias inductors L DC1 and L DC2 100 nh Tank Q 5 Tank capacitance C T 12 pf Tank inductance L T 2 nh Overlap interval τ 0.1 T the other hand, capacitive switching losses, which are often neglected in CMCD analyses, becomes quite significant particularly as the duty cycle deviates from 50%. As shown, when all the individual loss mechanisms and the load power are summed together, the predicted DC power is very close to the simulated results. Note that in this figure, all the powers are normalized to the analytic value for P DC. Some of the simulated values for DC power are slightly higher than the analytic value, therefore, the normalized value for some simulated values are slightly greater than 100%. Other conclusions from the analytical and simulated results are that the conduction loss is the dominant loss mechanism for duty cycles in the range of 30% to 70%, and for very low duty cycles (or very high) in the range of 20-30% (70-80%) capacitive switching losses are significant. From this we can conclude that if it were possible to design a general pulse encoder for CMCD amplifiers, it would be desirable to constrain pulse duty cycles to be in the range of 30-70% to maintain good power efficiency. This conclusion is supported by the power efficiency versus duty cycle data shown in Figure 2.16 where we see power efficiency ranges from 55% to 78% for a duty cycle range of 30-70%. 52

69 2.3. Power Efficiency Analysis of a CMCD Amplifier with Periodic Switching Normalized to Total Losses (%) Duty Cycle (α) PL PRon Pcapacitive Pinductive Poverlap PDC PL: Simulation PDC: Simulation Figure 2.15: Losses in the CMCD amplifier as a function of duty cycle. The overlap period τ is 0.1 T. Figure 2.16: Drain efficiency of CMCD amplifier as a function of duty cycle. 53

70 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals 2.4 Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals Time Encoded Input Signal When the input pulse train to a CMCD amplifier is a periodic pulse train with a duty cycle α, the load signal is a sinusoid at the fundamental frequency of the pulse train and the peak amplitude is determined by the duty cycle. Although the duty cycle can be adjusted to create an amplitude varying load signal, for a general modulated RF carrier signal, the spectrum of the pulse train needs to be shaped to ensure that a modulated load signal with low distortion can be delivered to the load. Examples of pulse encoders that can generate suitable pulse trains for amplification by a CMCD amplifier are bandpass sigma-delta modulation (SDM) and noise shaped pulse position modulation (PPM). The time domain and frequency domain properties of SDM and PPM were briefly reviewed in Chapter 1. As a way to predict the power efficiency of a CMCD amplifier when the input signal is a general pulse encoded signal, CMCD power efficiency is evaluated for more complex periodic signals. The motivation to use longer periodic sequences is to mimic the type of level crossings that would be non-periodic pulse trains such as SDM or PPM. In the following sections, the power efficiency of a CMCD amplifier is analyzed for periodic signals of different lengths. The analytical results are then compared with simulations of a pulse encoded CMCD amplifier which has non-periodic switching Power Efficiency for 1 T Periodic Signals Analytic results have been developed in earlier sections for predicting the power efficiency of a CMCD amplifier when the input signal is a periodic signal with duty cycle α. The signal has a period of T and example pulse train is shown in Figure By adjusting the duty, the load power changes and so does the power efficiency. An example of the power efficiency versus load power characteristic for a signal with period of T is shown in Figure The same CMCD amplifier design described in section (2.1) is used to obtain these results. The peak load power is approximately 30 W and corresponds to a 50% duty cycle. The power efficiency of the CMCD amplifier is approximately 75% at peak load power. As the duty cycle decreases, load power decreases, there is a corresponding reduction in power efficiency because conduction, inductive, and overlap losses are approximately independent of load power, while capacitive switching losses increase as load power decreases. At 3 db back-off the power efficiency has dropped to 27%. Amplitude α 1 T Time Figure 2.17: Signal with period 1T. 54

71 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals Periodic Signal SDM Signal Efficiency (%) Power (W) Figure 2.18: Comparison of power efficiency for a CMCD amplifier with a 1 T periodic signal and SDM non-periodic signal. The results for the periodic signal model are now compared with simulated results for bandpass sigma-delta modulator pulse trains. In Figure 2.18, a second response is shown for the modulator pulse train. The simulation results are obtained using the SDM encoder described in section The input source signal to the encoder is a sinewave, and the amplitude of the sinewave is swept to change output load power. Three observations are made when comparing the 1T periodic signal response with the SDM response. First, for the power range where the two responses overlap (approximately 21 W to 28 W), the two responses are nearly identical. Second, the 1T response corresponds to a duty cycle range of 20-50%, and clearly this sequence length cannot generate a load power below 21 W. Longer sequences are required to generate a larger range of load powers. Third, the peak load power with the periodic signal is higher than SDM. The reason for this is that a square wave with a 50% duty cycle has maximum power at the fundamental frequency and an SDM pulse encoder usually overloads before reaching a periodic limit cycle. Therefore, the peak power with an SDM modulator is less than the total available peak power which can be obtained with a periodic signal. This limitation led to the development of the PPM noise shaped encoder described in section which has higher coding efficiency. A comparison of the SDM and PPM encoders is shown in Figure For this figure, the x-axis corresponds to the peak amplitude of the source signal relative to the quantization amplitude in the encoder. As shown, the PPM encoder can overload to a 50% duty cycle square wave where the fundamental frequency component has an amplitude of 4/π 1.27, exceeding the quantizer amplitude which is unity. 55

72 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals SDM PPM Efficiency (%) Modulator Drive Relative to Full Scale Figure 2.19: Drain efficiency as a function of modulator drive level for SDM and PPM encoders N T Periodic Signals Up to this point, we have considered periodic signals with a duty cycle of α and period T as shown in Figure If a pulse train with period 2T is considered as shown in Figure 2.20, then it can be described in terms of two duty cycles α 1 and α 2. The corresponding load signal in a CMCD amplifier is determined by the amplitude of the second harmonic in the 2T pulse train. This process can in general be extended to NT where the pulse train is parameterized in terms of N duty cycles. Amplitude α 1 α 2 T 2T Time Figure 2.20: Signal with period 2T. One drawback of the 1T and 2T pulse trains in Figures 2.17 and 2.20 is that there is a variable DC level that depends on the duty cycles. For bandpass source signals, there is no DC component and pulse encoders typically synthesize pulse trains with zero mean DC components. One way to systematically create zero mean pulse trains is to alternate adjacent intervals in the pulse train with a duty cycle of 1 α. In this way, the sequence length doubles for N duty cycles. An example of a 6T signal with N = 3 is shown in Figure For the 6T signal, the amplitude of the sixth harmonic determines the amplitude of the load signal 56

73 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals in the CMCD amplifier. Amplitude α 1 1 α 1 α 2 1 α 2 α 3 1 α 3 T 2T 3T 4T 5T 6T Time Figure 2.21: A 6T signal with a zero mean DC component Power Efficiency Analysis for a 2T Periodic Signal Assuming zero-mean pulse trains, we now consider how to predict the power efficiency of a CMCD amplifier if the input pulse train is a 2T signal. There are two duty cycles, and for a zero-mean signal, let α 1 = α and α 2 = 1 α. The parallel resonant filter in the CMCD output is tuned to extract the second harmonic of the waveform. From a Fourier series analysis, the second harmonic of this pulse can be expressed as ( ) 2 I om2t = π I DC 2T sin 2 (απ). (2.30) The output power is then P L2T = 1 2 R LI 2 om 2T = 2 π 2 R L I 2 DC 2T sin 4 (απ). (2.31) Using (2.31) and (2.7), the ratio of the output power of the 2T signal relative to the output power of a 1T signal is P L2T P L1T sin 2 (απ). (2.32) The equation is written as an approximation because it based on the assumption that the DC current drawn by the amplifier is the same for the 1T and 2T signals. Simulation results verify that this is a good assumption as will be shown shortly. Using equation (2.32), an expression for the relative power efficiency of the CMCD amplifier when amplifying 1T and 2T is η 2T = (P L 2T /P DC2T ) η 1T (P L1T /P DC1T ) sin2 (απ). (2.33) Again, the assumption that the DC currents for the two cases are the same is used to conclude that the DC power for the two cases is the same (recall that V DD is fixed in a CMCD amplifier). 57

74 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals What the power efficiency ratio enables is an extension to lower load power levels, because the second harmonic amplitude in a 2T pulse train with duty cycle parameter α is smaller than the fundamental frequency amplitude in a 1T pulse train with a duty cycle of α. Equation (2.33) is used to extend the power efficiency analysis of CMCD amplifiers from 1T to 2T. An example of analytical and simulated results for 2T signals is shown in Figure As the results show, there is good agreement between the analysis and simulation which confirms the assumption that the DC current in the CMCD amplifier is approximately equal for both the 1T and 2T signals Calculated results Simulated results Efficiency (%) Duty Cycle Figure 2.22: Drain efficiency of CMCD amplifier as a function of duty cycle when driven with a 2T periodic signal Power Efficiency for 6T Periodic Signals Longer periodic sequences can be generated to increase the amplitude range of the load signal. As an example, a zero mean 6T signal is considered next. There are six duty cycle parameters, but after imposing the zero-mean constraint, there are three independent duty cycles. The corresponding duty cycles in the 6T pulse train are α 1, 1 α 1, α 2, 1 α 2, α 3 and 1 α 3 as shown in Figure Different combinations of duty cycles, lead to different sixth harmonic amplitude levels and twenty different sequences are tabulated in Table 2.3. Circuit simulations of a CMCD power amplifier were run with all the different 6T sequences in Table 2.3 and the corresponding power efficiency is shown Figure The simulation results are compared with SDM and PPM pulse trains as well as with 1T and 2T periodic sequences described earlier. Note that all periodic sequences have been constrained to have pulse widths that are at least 0.2T or greater. From the results, it is clear that simulations results with periodic sequences are very consistent with results for more general pulse encoded signals like SDM and PPM. From these results we conclude that analytic results obtained for 1T and 2T periodic signals can lead to good predictions of the performance of a CMCD amplifier for more general pulse trains like SDM and PPM. 58

75 2.4. Predicting CMCD Amplifier Power Efficiency for Pulse Encoded Signals Table 2.3: Duty cycles for generating signals with a period of 6T. Sequence (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) α α α Input Amplitude Sequence (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) α α α Input Amplitude Solid: SDM Efficiency (%) Dash: PPM Square: 1T Signal Circle: 2T Signal Triangular: 6T Signal 2T Signal 6T Signal α=0.2 α=0.2 1T Signal Power (W) Figure 2.23: CMCD amplifier power efficiency for periodic (1T, 2T, and 6T ) and non-periodic pulse trains (SDM and PPM). In wireless communication applications, the input signal is a modulated carrier with a large PAPR. Therefore, the average power point is backed off relative to peak power. With reference to Figure 2.23, peak load power is approximately 30 W and the power efficiency is about 75%. At 3 db back-off, the output power is 15 W and the corresponding power efficiency is reduced to 28%. This shows that there is a steep reduction in power efficiency as soon as the output power is backed off. The main reason for the reduction in efficiency is the range of duty cycles in the pulse train. If the duty cycle variation could be minimized, then higher efficiency could be obtained. For example, with reference to Figure 2.22, a duty 59

76 2.5. Chapter Summary cycle range from 35-65% would maintain power efficiency at 50% or higher. Therefore, these results show the importance of the signal mapping stage in a RF switch-mode power amplifier system. 2.5 Chapter Summary Three different device model levels were introduced to analyze the power efficiency of a CMCD power amplifier. The level 1 model is a simple switch and a model that is commonly used in the literature. The level 2 model introduced in this work extends the level 1 model to include current saturation limitations in the switch as well as overlap losses. The level 3 model goes further and includes nonlinear device capacitances, and the model will be used more extensively in the next chapter. The level 2 model was used to analyze the power efficiency of a CMCD amplifier under variable duty cycle switching conditions. A thorough analysis was presented for 1T periodic signals. The analytic results were compared with simulations of a CMCD amplifier using a SDM pulse train. The two results are very similar which shows that the analysis models the behaviour of the amplifier under more general non-periodic switching conditions. The analysis was extended to 2T periodic signals. Again there is a good match between the predicted and simulated power efficiency over a large range of duty cycles. Simulation results were then made to compare the power efficiency of CMCD amplifiers with longer periodic sequences up to 6T. As with 1T and 2T, the 6T results closely match the performance of SDM and PPM pulse trains. The power efficiency of the CMCD amplifier is very dependent on the duty cycle variation in the pulse train. As the analytical and simulation results show, power efficiency reduces quickly as the load power is reduced. The results show that signal mapping in the pulse encoder and the design of the switch-mode power amplifier are closely linked. In the next chapter, class-f amplifiers are designed and later in Chapter 5, the class-f amplifiers are tested with pulse encoded signals. 60

77 Chapter 3 Class-F RF Power Amplifiers Class-F amplifiers use harmonically tuned input and output matching networks to shape the waveforms at the gate and drain of the amplifying device. The goal of harmonic waveshaping is to reduce the overlap of the drain current and drain voltage waveforms to obtain a high efficiency amplifier. Similar to the class-d amplifier, class-f amplifiers can approach a switch-mode type of operating condition providing the amplifiers are operated near saturation. There is a large body of work related to class-f amplifier design and the contributions to this work are the following. First, a systematic study of the effect of input harmonic termination impedance is made for a class-f amplifier. The study uses a level 3 device model and the relative importance of first, second, and third harmonic input impedances are analyzed. The comparison includes third harmonic terminations at the input which is new. Experimental results for a class-f amplifier including third harmonic networks for both the input and the output are also shown. Second, an inverse class-f (class-f 1 ) amplifier design is implemented using exactly the same device as the class-f amplifier, and the two amplifier designs are compared. The comparison is useful as it is more difficult to find reference designs in the literature which provide a direct compare between the voltage switched class-f amplifier and the current switched class-f 1. The experimental results clearly show that the current switched class-f 1 circuit has higher power efficiency over a larger dynamic range. The class- F amplifier designs are also very useful benchmarks for Chapter 4, where the amplifier are reconfigured into RF rectifiers. The chapter concludes with the design of a wideband class- F 1. Although experimental results for wideband class-f 1 can be found in the literature, the design presented here is reconfigured into a wideband rectifier in Chapter 4, and the wideband rectifier work which builds on the wideband amplifier design is new work. 3.1 Level 3 Device Model All the experimental circuits in this thesis use a packaged 10 W GaN HEMT (model CGH40010) available from Cree. Although a comprehensive large signal model for the device is available from Cree, it is difficult to use this model to gain insight into the underlying mechanisms that generate harmonic frequency components at the gate terminal of the device. Also, the black-box Cree model does not enable any way to tune device parameters and evaluate the sensitivity of the circuit with respect to different device parameters. Therefore, a level 3 device model is first constructed from a large signal device model for a Cree CGH60015D die. After building a model of the die, the model is then extended to include package parasitics since a packaged device is used for all the experimental work. The packaged device (model CGH40010) uses the CGH60015D die which is wire bonded to the package leads. The methods used to extract the equivalent circuit values for the level 3 model are reviewed next. 2 Parts of Chapter 3 have been published in two articles. Reprinted with permission from PIER and EuMC [56, 76]. 61

78 3.1. Level 3 Device Model G L g r g rd L d G C gd D D C gs I C ds V S Intrinsic Device Model r s L s S Figure 3.1: Level 3 equivalent circuit model for GaN HEMT Cree CGH60015D [reproduced courtesy of The Electromagnetics Academy] Bare Die Device Model A level 3 device model is shown in Figure 3.1. The equivalent circuit for the device is partitioned into an intrinsic device model composed of a current source and nonlinear device capacitances (C gs, C gd and C ds ), and extrinsic inductances and resistances associated with the interconnect to the intrinsic device. The values for the components in the equivalent circuit model are obtained from Z and Y -parameters for the large signal device model. The extraction process is described next. Let Z be the Z parameters for the intrinsic device. The corresponding Z parameters for the overall device model are [88] [ ] [ Z11 Z 12 Z = 11 + (r g + r s ) + j(l g + L s )ω Z 12 + r ] s + jl s ω Z 21 Z 22 Z 21 + r s + jl s ω Z 22 + (r. (3.1) d + r s ) + j(l d + L s )ω Therefore, once the extrinsic interconnect values for the series inductances and resistances are known, we can find the Z-parameters for the intrinsic device. After Z is obtained, the matrix can be inverted to find the admittance parameters Y. The individual admittance parameters can be matched to the Π capacitance network and lead to the following equations [89]. C gd = Im[Y 12 ] ω (3.2) C gs = Im[Y 11 + Y 12 ] ω (3.3) C ds = Im[Y 22 + Y 12 ] ω (3.4) 62

79 3.1. Level 3 Device Model Extraction of the Parasitic Inductances and Resistances At this point, we need to find a way to determine the extrinsic circuit component values. An important observation is that the series inductances and resistances are independent of the bias point of the device, while the nonlinear device capacitances in the intrinsic model are bias dependent. Therefore, a bias point can be selected that simplifiers the extraction of the extrinsic component values. A good choice for the extraction, is the off-state bias condition where V GS = V GSOF F and V DS = 0 V. Under these conditions, the transconductor in the intrinsic model is short circuited and nodes S and D are shorted, as shown in Figure 3.2. Under the off-state bias condition, the real part of the Z-parameters is directly related to the resistances in the equivalent circuit and we have the following relations: Re[Z 11 ] = r g + r s Re[Z 22 ] = r d + r s Re[Z 12 ] = Re[Z 21 ] = r s (3.5) From these equations, all the resistances can be uniquely found from Z-parameters for the off-state. Also note that the real part is frequency independent. G L g r g rd L d G C gd D D C gs C ds S Intrinsic Device Model r s V DS = 0 shorts nodes S and D L s S Figure 3.2: Equivalent circuit model for off-state bias conditions. The Z-parameters for the off-state were obtained from the large signal Cree model and the results are shown in Figure 3.3. The real and imaginary components of the Z-parameters are shown by the solid lines for a frequency range of 0.5 to 10 GHz. The data clearly show the real component is constant over frequency, consistent with equation (3.5). The equations were used to calculate the equivalent circuit resistances and the values are optimized in a final step after all component values are extracted for the level 3 model. The imaginary component of the off-state Z-parameters is more entangled and contributions to reactance are made both from the series lead inductances as well as the intrinsic devices capacitances. The entanglement is simplified by using Z-parameters at very high frequencies where the inductance starts to dominate the response and the intrinsic capacitances have low reactance. The inductive behaviour of the reactance is evident in the Z-parameter measurements shown in Figure 3.3 where the slope at high frequencies is related to the in- 63

80 3.1. Level 3 Device Model ductance. Clearly, in the limit as ω gets large the Z-parameters are approximated as Z 11 (r g + r s ) + j(l g + L s )ω Z 22 (r d + r s ) + j(l d + L s )ω Z 12 = Z 21 r s + jl s ω (3.6) These approximations are used to estimate values for the extrinsic inductances. Figure 3.3: Z-parameters for the level 3 device model (symbols) and for the large signal device model (solid lines) for the off-state bias condition Off State Device Model Once the extrinsic inductances and resistances are found, the Z-parameters of the off-state can be de-embedded to extract the intrinsic Z -parameters. The instrinsic Z -parameters are then inverted to find the admittance matrix Y from which values for the devices capacitances can be found using equations (3.2), (3.3) and (3.4). After calculating initial values for all the model components, a final step to optimize the model values is made to provide the best match 64

81 3.1. Level 3 Device Model between the level 3 model and the Cree model. The Y -parameters are particularly useful for optimizing the final values because they are sensitive to all the device characteristics. A comparison of the off-state Y -parameters for the level 3 model compared to the Cree model are shown in Figure 3.4. As shown, there is good agreement between the two models. A summary of model 3 equivalent circuit component values for the off-state is shown in Table 3.1. Figure 3.4: Y -parameters for the level 3 device model (symbols) and for the large signal device model (solid lines) for the off-state bias condition Extraction of Nonlinear Device Capacitances The intrinsic device capacitances are nonlinear, having dependencies on the gate-source voltage and the drain source voltage. Now that the extrinsic inductances and resistances are known in the level 3 model, parametric sweeps of the de-embedded Y -parameters can be used to extract models of the device capacitances over a wide range of bias conditions. It should be noted, that when V DS is no longer zero, the model includes a voltage controlled current source which models the transconductance of the device. At low frequencies, the transconductance 65

82 3.1. Level 3 Device Model Table 3.1: Level 3 model values for the Cree GaN HEMT (CGH60015D) in the off-state bias condition. Element r g r d r s L g L d L s C gs,off C ds,off C gd,off (Ω) (Ω) (Ω) (ph) (ph) (ph) (pf) (pf) (pf) Value Table 3.2: Summary of device capacitances for a Cree GaN HEMT (CGH60015D). Model Model Datasheet V gs =-5 V to 0 V, V ds =0 V to 60 V V gs =-8 V and V ds =28 V V gs =-8 V and V ds =28 V Capacitance Min. Max. Linear Value Typical C ds 0.87 pf 2.4 pf 0.92 pf 0.87 pf 0.9 pf C gd 0.1 pf 0.7 pf 0.36 pf 0.19 pf 0.2 pf C gs 4.14 pf 7.65 pf 6.17 pf 4.14 pf 4.1 pf term is associated with the real part of the Y -parameters and the imaginary part of the Y - parameters can be used to find the intrinsic device capacitance values similar to the procedure used in the off-state. The bias points which were used to extract the nonlinear device capacitances span a V GS range from -8 to 0 V (-8, -4, -2, -1, 0 V) and a V DS range from 0 to 80 V (0, 2, 4, 6, 8, 10, 20, 28, 40, 50, 60 and 80 V). The best fit values were optimized for a frequency of 1 GHz and the device capacitance characteristics are shown in Figures 3.5 (a)-3.5 (d). Notable characteristics include significant variation in C ds for low drain voltages, a significant change in C gs as the gate voltage swings between on and off states, and nonlinear C gd characteristics that depend on both the gate and drain voltages. The variation in the device capacitances over the operating range of the device are summarized in Table 3.2. The table also includes the nominal device capacitances given on the Cree datasheet for the die [90]. In order to implement the level 3 model in a circuit simulator, nonlinear circuit elements are required for the device capacitances and the transconductance to model the IV curves of the device. In ADS, nonlinear capacitor models are available that can be linked to look up tables. In this way, the instantaneous capacitance is dependent on the instantaneous gate-source and drain source voltages in the circuit. The nonlinear transconductance, which models the IV characteristics of the device, is implemented using a special component called a symbolically defined device (SDD). Similar to the capacitors, the SDD block is controlled by a look-up table that models the drain source current dependency on gate-source and drainsource voltages Level 3 Model for Die and Package A packaged die is used for experimental work and a level 3 model for the device including a package is shown in Figure 3.6. It consists of the level 3 bare die model shown earlier in 66

83 3.1. Level 3 Device Model Drain Source Capacitance (pf) Decreasing order Vgs=0 to 5 (a) Vds (V) Gate Source Capacitance (pf) Vgs= 2 V, 1 V, 0 V Vgs= 3 V Vgs= 8 V, 4 V (b) Vds (V) Gate Drain Capacitance (pf) Decreasing order Vgs= 0 to 5 (c) Vds (V) Gate Source Capacitance (pf) (d) Gate Source Voltage (V) Figure 3.5: Extracted intrinsic device capacitances for the Cree GaN HEMT (CGH60015D): (a) drain-source capacitance, (b) gate-source capacitance, (c) gate-drain capacitance, and (d) gate-source capacitance versus gate-source voltage. Figure 3.1 with additional lead inductances (L pg, L pd ) and capacitances (C pg, C pd ). Similar to the method used to find extrinsic inductances, the package inductances can be found from Z-parameters measured at high frequencies where the response is dominated by the package inductance and the package capacitance approaches a low impedance. After finding estimates of the package inductances, the package capacitances in the level 3 model are tuned to match the Z-parameters of the Cree large signal model for the packaged device (CGH40010F). The extracted values for the package model are found to be: L pg = 0.7 nh, L pd = 0.6 nh, C pg = 0.41 pf and C pd = 0.4 pf. As a confirmation of the level 3 model, the Y -parameters of the model level 3 model are compared to the Cree model. The results are shown in Figures 3.7 through 3.9. Good agreement is obtained and the level 3 model is used in the next section to study the effect of input harmonic termination impedances in a class-f amplifier. 67

84 3.1. Level 3 Device Model L pg C gd L g r d L d r g L pd I C pg C gs V C ds C pd r s L s Bare Die Figure 3.6: Device model for packaged die [reproduced courtesy of The Electromagnetics Academy]. Figure 3.7: Comparison of Y 11 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. 68

85 3.1. Level 3 Device Model Figure 3.8: Comparison of Y 12 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. Figure 3.9: Comparison of Y 22 parameters for the level 3 model including the package (symbols) and the GaN HEMT Cree large signal model for the CGH40010F (solid line). The device bias conditions are in the off-state. 69

86 3.2. Class-F Amplifier Simulation Experiments 3.2 Class-F Amplifier Simulation Experiments Class-F amplifiers are inherently nonlinear and use harmonic impedance control in the output circuit to shape the voltage waveform at the drain. In an ideal class-f design, the device is cut-off for half the cycle similar to class B, and harmonics are created in the output circuit because the drain current is a half sinusoid. Harmonic termination impedances in the output circuit preserve the shape of the current waveform by shorting even harmonics. The drain voltage waveform is shaped to reduce overlap with the current waveform by open circuit termination impedances at odd harmonics. There are however other mechanisms in a class-f amplifier that create additional harmonic frequency components in the current and voltage waveforms. Examples include deviations from the class-b bias point which means the current waveform is no longer a perfect halfsine waveform, and nonlinear device capacitances [19] and nonlinear device transconductances which create new harmonic frequency terms even for perfectly sinusoidal input signals. Of these mechanisms, nonlinear gate-source capacitance C gs and nonlinear gate-drain capacitance C gd can directly create harmonic components at the gate. There are also feedback mechanisms including C gd and source inductance which can couple drain harmonics to the gate. For example, an imperfect second harmonic termination in the output match creates a second harmonic voltage component that can be coupled to the gate through C gd. The effect of harmonic signal components at the gate is that the gate waveform is no longer sinusoidal even if the input to the amplifier is a perfect sinusoid. Changes to the gate waveform, affect the drain current waveform, and consequently the drain current waveform deviates from an ideal half sinusoidal shape. Therefore harmonic termination impedances at the gate can be used to shape both the gate waveform and the drain current waveform. The relationship between power efficiency and input harmonic impedances for class-f amplifiers has been studied by others [91, 92, 93, 94, 95, 96, 97] and a summary is presented in Table 3.3. Most work listed in the table has focused on evaluating the effect of fundamental and second harmonic impedance terminations at the input of the device. Also, in these papers, the mechanisms that generate harmonics in the device have been less important, and the work has focused on investigating harmonic termination impedances using harmonic load pull and time domain techniques. Although these techniques are general and can be extended to all harmonics, the experimental work presented in these papers has been limited to circuits with input harmonic terminations for fundamental and second harmonic impedances. This work extends the investigation of input harmonic impedance to include the effect of third harmonic terminations on the power efficiency of a class-f amplifier. A systematic comparison of the power efficiency for amplifier designs with fundamental, second harmonic, and third harmonic terminations are made. Simulations with the level 3 device model are used to investigate the relationship between device capacitances and the harmonic levels at the gate. The impact of the gate to drain capacitance, C gd, is particularly important as it provides feedback from the output to the input. The feedback, combined with imperfect output harmonic termination impedances, can lead to the injection of both odd and even harmonics to the gate terminal. The model is also used to investigate the sensitivity of the design to nonlinear device capacitances. A comparison is made between a model with linear capacitances and a model with nonlinear capacitances. 70

87 3.2. Class-F Amplifier Simulation Experiments Table 3.3: Class-F amplifier designs with input harmonic termination networks. Ref. Type Device Input Harmonics Approach [91] class-f GaN f o, 2f o harmonic tuning class-f 1 [92] class-f PHEMT f o, 2f o device level class-b [93] class-f AlGaAs/GaAsN f o, 2f o phase relationship class-f 1 [98] class-f GaAs MESFET f o, 2f o power balance class-e [95] class-f Power MESFET f o, 2f o load/source pull [96] class-f Power MESFET f o, 2f o, 3f o phase relationship [97] class-f PHEMT f o, 2f o, 3f o load/source pull This class-f GaN HEMT f o, 2f o, 3f o device level work Class-F Amplifier Design The complete level 3 simulation model with provisions up to third harmonic termination impedances at the gate is shown in Figure The amplifier is designed for a fundamental frequency of 990 MHz. The drain bias (V DD ) is 30 V and the gate bias (V GG ) is -2.6 V. The optimal load and source impedances at the fundamental frequency were found using source and load pull [99] test benches in the simulator. The transmission line elements TL101 and TL102 in Figure 3.10 implement the fundamental frequency input match, and transmission lines TL109 and TL110 implement the fundamental frequency output match. The output matching circuit consists of three other transmission lines, TL106, TL107, and TL108, which create a second harmonic short and third harmonic open at the drain. The input matching circuit also has three transmission lines, TL103, TL104 and TL105, which are used to experiment with different input harmonic terminations at the gate. Further optimization of the third harmonic output stub TL108 can be made to compensate for the output reactance of the device at the third harmonic frequency. However, the optimization of the output matching network with the level 3 device model is not the primary focus here and we constrain the output network topology to be the same for all design studies of the input matching network (see Figure 3.11). Instead, here we adjust the length of the output harmonic stubs and vary C gd to create different harmonic injection levels that are fed back to the gate. In this way, the significance of the input harmonic terminations versus power efficiency can be swept for different harmonic injection levels at the gate. 71

88 3.2. Class-F Amplifier Simulation Experiments Var Eqn Var Eqn Var Eqn VAR VAR_wavelengths Lambda0=360 Lambda2=Lambda0/2 Lambda3=Lambda0/3 VAR VAR_network1 ELharmonic1=Lambda0/4 ELharmonic2=Lambda2/4 ELharmonic3=Lambda3/4 ELinputmatching1=80.25 ELinputmatching2=47.3 VAR VAR_signal f=0.990 Pindbm=24.5 Var Eqn gate HARMONIC BALANCE Ref gate Var Eqn Var Eqn drain drain DAC Var Eqn Ref Ref Ref Ref TLIN TL102 Z=Z0 Ohm E=ELinputmatching2 F=f GHz TLOC TL104 Z=Z0 Ohm E=ELharmonic3 F=f GHz VAR VAR_bias V_DC VGG=-2.6 SRC1 Rdamp=5 Vdc=VGG V C C1 C=Cb pf TLIN TL105 Z=Z0 Ohm E=ELharmonic1 F=f GHz L L3 L=Lch nh R= R R3 R=Rdamp Ohm DC_Block DC_Block1 Ref TLOC TL101 P_1Tone Z=Z0 Ohm PORT1 E=ELinputmatching1 Num=5 F=f GHz Z=50 Ohm P=dbmtow(Pindbm) Freq=f GHz HarmonicBalance HB1 Freq[1]=f GHz Order[1]=10 TLOC TL103 Z=Z0 Ohm E=ELharmonic2 F=f GHz L L1 L=Lg ph R= R R1 R=rg Ohm NonlinC Cgs VAR VAR_parameters rg=0.6 rd=0.6 Lg=92 Ld=88 NonlinC Cgd SDD2P SDD2P1 I[1,0]=(_v1)*0 I[2,0]=ids C[1]= Cport[1]= R R2 R=rd Ohm NonlinC Cds VAR VAR3 vds=_v2 vgs=_v1 L L2 L=Ld ph R= DataAccessComponent DAC1 InterpMode=Linear InterpDom=Rectangular ExtrapMode=Interpolation Mode ivar1="vgs" ival1=vgs ivar2="vds" ival2=vds VAR VAR_IDS ids=file{dac1, "IDS"} TLIN TL106 Z=Z0 Ohm E=ELharmonic1 F=f GHz TLOC TL108 Z=Z0 Ohm E=ELharmonic3 F=f GHz TLIN TL109 Z=Z0 Ohm E=ELoutputmatching1 F=f GHz V_DC SRC2 Vdc=VDD V C L C2 L4 C=Cb pf L=Lch nh R= DC_Block DC_Block2 R R4 R=RL Ohm Var Eqn VAR VAR_network2 ELoutputmatching1=65.1 ELoutputmatching2=54.3 RL=Z0 Z0=50 TLOC TL107 Z=Z0 Ohm E=ELharmonic2 F=f GHz TLOC TL110 Z=Z0 Ohm E=ELoutputmatching2 F=f GHz Figure 3.10: Schematic for the class-f PA [reproduced courtesy of The Electromagnetics Academy]. 72

89 3.2. Class-F Amplifier Simulation Experiments TL out3 (λ o /12) Z OMN TL out1 (λ o /4) TL out2 (λ o /8) TL out4 TL out5 50 Ω Figure 3.11: Output matching network (OMN) structure [reproduced courtesy of The Electromagnetics Academy] Harmonic Input Impedances and Sensitivity to Device Capacitances For the first simulation experiment, the device model consists of fixed (linear) device capacitance values. The fixed capacitance values are selected to be the expected value of the nonlinear capacitances over the operating range of the circuit. The fixed capacitance values are: C gs = 6.17 pf, C ds = 0.92 pf and C gd = 0.36 pf. When the device capacitances are linear, the only mechanism for generating harmonics at the gate is feedback from the output circuit to the input circuit through C gd. The effect of feedback through C gd is illustrated by comparing the harmonic spectrums at the drain and gate. In Figure 3.12, the spectrums are shown for the case where C gd is zero. The drain spectrum for the voltage has DC, fundamental and third harmonic components. The second harmonic is zero because the harmonic is shorted in the output circuit. The corresponding gate spectrum has only a DC and fundamental frequency component as expected because there is no feedback from the drain to gate. On the other hand, when C gd is not zero, harmonic components from the drain voltage are fed back to the gate. An example is shown in Figure 3.13 for C gd = 0.36 pf. The amount of harmonic feedback from the output to the input of the device depends not only on the size of C gd but also on the harmonic levels in the output circuit. Figure 3.12: Spectrum for the case where C gd = 0 pf: drain voltage (left) and gate voltage (right) [reproduced courtesy of The Electromagnetics Academy]. In the next set of simulation experiments, the device model with linear capacitances is used to compare the power efficiency of three different class-f amplifier designs where each design 73

90 3.2. Class-F Amplifier Simulation Experiments Figure 3.13: Spectrum for the case where C gd = 0.36 pf: drain voltage (left) and gate voltage (right) [reproduced courtesy of The Electromagnetics Academy]. has a different harmonic input matching network. The input matching circuits are shown in Figure In the first design (Design 1), the gate is matched only for the fundamental frequency. In the second design (Design 2), the input matching circuit provides a fundamental frequency match and a short at the second and third harmonics. In the third design (Design 3), the input matching circuit provides a match at the fundamental frequency, a short at the (a) in gate TL in2 TL in1 (b) in TL in3 (λ o /12) TL in2 gate TL in1 TL in4 (λ o /8) (c) in TL in3 (λ o /12) TL in2 TL in5 (λ o /4) gate TL in1 TL in4 (λ o /8) Figure 3.14: Input matching network circuits: (a) Design 1, (b) Design 2 and (c) Design 3 [reproduced courtesy of The Electromagnetics Academy]. 74

91 3.2. Class-F Amplifier Simulation Experiments Table 3.4: IMN transmission line lengths for a device model with linear capacitances. Design Harmonic input impedances f o 2f o 3f o T L in1 T L in2 T L in3 T L in4 T L in5 Γ in,2fo Γ in,3fo 1 Z S,opt Z S,opt Short Short Z S,opt Short Open second harmonic and an open at the third harmonic. Table 3.4 summarizes the input matching network (IMN) designs. As shown in Figure 3.13, odd harmonics in the drain voltage are fed back to the gate through C gd. With linear device capacitances, and an ideal second harmonic short in the output, there are no even harmonics at the gate. However, when device capacitances are nonlinear or when imperfect second harmonic terminations in the output circuit are considered, there are even harmonic components at the gate as well. In the next simulation experiment, the same device model with linear capacitances is used except the level of second harmonic distortion at the gate is swept over a large range by tuning the length of TL107 to create an imperfect second harmonic short in the output circuit; in other words, the second harmonic phase at the drain is swept from 150 to 180 degrees. An imperfect second harmonic short is created in practical class-f amplifier designs as soon as the frequency is shifted from the design frequency. The results of the second harmonic sweep for the three different input matching circuit designs is summarized in Figure It can be seen that the input matching circuit design is significant when the second harmonic level at the drain is high for example greater than -20 db relative to the fundamental frequency component. For a second harmonic level of -11 db, going from Design 1 (fundamental match only) to Design 2 the power efficiency increases by 5.5%. A small but measurable improvement in power efficiency is obtained with Design 3 when a third harmonic open is added to the gate matching network. If the second harmonic level is low, for example less than -30 db, the power efficiency of the different designs are similar which is expected. From these results it is clear that incremental improvements in power efficiency can be obtained with harmonic terminations at the gate and the most significant improvement is gained by a second harmonic short with a smaller improvement gained by adding a third harmonic open. As discussed earlier, the amount of harmonic feedback from the drain to the gate depends on the size of C gd. When there is no feedback, the gate signal has only a fundamental frequency component and the performance of the three designs are similar. On the other hand, as C gd is increased, the significance of harmonic input impedance becomes increasingly important. In the next set of simulations, the results for a device model with linear capacitances are compared with simulation results for a device model with nonlinear capacitances. With reference to Figure 3.1, a level 3 device model is used with the nonlinear device capacitance characteristics shown in Figure 3.5. Similar to the simulations for linear capacitances, the effect of nonlinear devices capacitances is evaluated for three different amplifier designs, each with a different input harmonic matching circuit as shown in Figure The output match- 75

92 3.3. Class-F Amplifier Experimental Results Table 3.5: Summary of simulation results for a device model with nonlinear capacitances. Design Harmonic input impedances f o 2f o 3f o T L in1 T L in2 T L in3 T L in4 T L in5 η d (%) 1 Z S,opt Z S,opt Short Short Z S,opt Short Open ing circuit in these simulations has perfect harmonic terminations at the second and third harmonic. A comparison of the three different designs with nonlinear device capacitances is shown in Table 3.5. The results are consistent with the results shown in Figure 3.15 for linear capacitances in that the biggest improvement in power efficiency results from adding a second harmonic short at the gate and a small improvement of less than 1% is obtained by adding a third harmonic open at the gate. Also, the improvement in power efficiency going from Design 1 to Design 2 with nonlinear device capacitances is larger than the result with linear capacitances. For example, for linear device capacitances and a second harmonic level of approximately db in Figure 3.15, the power efficiency of Design 1 is about 77.5%, similar to the power efficiency of Design 1 with nonlinear capacitances (Table 3.5). If Design 2 values are compared, the result for the linear capacitance model is about 79.5% or an increase of 2% compared to Design 1, while the result for the nonlinear capacitance model is 83.2%, an increase of 5.7% compared to Design 1. The device level modeling work also shows that the performance of an amplifier with linear device capacitances has a power efficiency within a few percent of an amplifier with nonlinear device capacitances. In other words, the harmonic injection by C gd is very significant. Also, the simulation experiments show that a second harmonic short at the input is very significant in terms of improving power efficiency in a class-f amplifier. The second harmonic short at the gate node desensitizes the design to second harmonic injection from both feedback through C gd as well as second harmonic components created by nonlinear device capacitances. A small but slightly higher power efficiency can be obtained with an additional input third harmonic termination. 3.3 Class-F Amplifier Experimental Results A class-f amplifier with third harmonic input matching and output matching circuits was built. The design uses a packaged Cree 10 W device and the level 3 model including the package model was used for the preliminary design. Final optimization of the design used the Cree large signal model Physical Circuit Design The device package introduces parasitic inductance and capacitance that modifies the optimal harmonic termination impedances at the terminals of the device. The required harmonic 76

93 3.3. Class-F Amplifier Experimental Results Efficiency (%) Design 3 Design 2 Design Second / First Harmonic Ratio at Drain (db) Figure 3.15: Simulated drain efficiency as a function of second harmonic level for a device model with linear capacitances [reproduced courtesy of The Electromagnetics Academy]. Second / First Harmonic Ratio at Gate (db) impedances at the terminal planes of the device were determined from a load pull test bench in the simulator. The results are shown in Table 3.6 for a fundamental frequency of 990 MHZ with a bias of V DD = 30 V and V GG = 2.6 V. The harmonic matching networks for the class-f amplifier are shown in Figure 3.16 and are designed using the impedance buffer methodology described in [100]. With reference to Figure 3.16, the output matching network at reference plane A should provide optimal load impedances of Z L (f 0 ) at f 0, Z L (2f 0 ) at 2f 0 and Z L (3f 0 ) at 3f 0. The corresponding load reflection coefficients at these frequencies are given in Table 3.6. In the design, all transmission lines have a characteristic impedance of 50 Ω except for T L in5 and T L out3 which have a characteristic impedance of 36 Ω. The synthesis of the output match begins with the second harmonic network. The transmission line T L out2 is 90 at the second harmonic frequency and creates a short at plane B. Consequently the reflection coefficient looking to the right of plane B at the second harmonic is The addition of the series transmission line T L out1 modifies the phase to provide the match Γ L (2f o ) at plane A. The next step in the synthesis of the output circuit is to add transmission lines T L out3 and T L out4 to create the third harmonic match. Transmission line T L out4 is 90 at the third harmonic frequency creates a short at reference plane C. The short is transformed through transmission line T L out3 to create the required reflection coefficient Γ L (3f o ) at plane A. Also, the characteristic impedance of T L out3 is reduced from 50 Ω to 36 Ω and selected to improve the bandwidth of the fundamental frequency match by transforming the lower output impedance at the device terminal plane to a higher impedance close to 50 Ω. The fundamental frequency output match is implemented with a double stub circuit consisting of T L out5, T L out6, and T L out7. For this design the double stub circuit results in a 77

94 3.3. Class-F Amplifier Experimental Results Table 3.6: Source and load pull harmonic impedances for the class-f amplifier. P in (dbm) P out (dbm) P AE(%) Γ L (f 0 ) Γ L (2f 0 ) Γ L (3f 0 ) Γ S (f 0 ) Γ S (2f 0 ) Γ S (3f 0 ) Z F Z E V GG C 0 Z A Z B Z C V DD C 0 V in TL in1 TL in3 (λ o /12) TL in2 TLin4 F TL in5 Harmonic Input Matching Network E TL in6 (λ o /8) TLin7 D C in Z D L GG Rg A TL M out1 1 B TL out4 (λ o /12) TL out3 TL out2 (λ o /8) I DC TL out6 TL out5 Harmonic Output Matching Network C L DD Cout TL out7 V out Figure 3.16: Schematic of the class-f power amplifier with output and input matching circuits and bias networks [reproduced courtesy of The Electromagnetics Academy]. more compact fundamental frequency match than a single stub matching circuit. A similar design methodology is used for the input matching circuit design with the exception of a series resistor R g added to improve the stability of the device. The stability of the device is evaluated using Rollet s stability factor [101] k = 2 Re(Z 11) Re(Z 22 ) Re(Z 12 Z 21 ). (3.7) Z 12 Z 21 A series gate resistance increases the real part of Z 11 to improve stability. Since R g also reduces gain, the choice of R g is a compromise between stability and gain. In this design, a value of 2 Ω is selected. The class-f circuit design in Figure 3.16 is transformed into a physical circuit design using microstrip lines for the transmission line structures. The design was fabricated using copper tape transmission lines on a mm Rogers 4350 substrate with dielectric constant of The final design values for the matching networks are summarized in Table 3.7. The simulated drain and gate waveforms for the final class-f amplifier design are shown in Figure For these simulations, the current and voltage are shown referenced to the terminal planes of the packaged device. The shape of the waveforms are modified relative to the waveforms at the intrinsic device plane of the device because of the package parasitics. 78

95 3.3. Class-F Amplifier Experimental Results Table 3.7: Transmission line lengths for load and source matching networks. T L out1 T L out2 T L out3 T L out4 T L out5 T L out6 T L out7 in mm in degree T L in1 T L in2 T L in3 T L in4 T L in5 T L in6 T L in7 in mm in degree Figure 3.17: Simulated drain voltage and drain current waveforms (left) and gate voltage and drain current waveforms (right)[reproduced courtesy of The Electromagnetics Academy] Experimental Results The experimental class-f amplifier design is shown in Figure 3.18 and a picture of the experimental test bed is shown in Figure The amplifier design was tested with both continuous wave (CW) and modulated signals. The results for each test signal are described in the following subsections CW Performance The power efficiency of the class-f amplifier for a CW input signal is shown in Figure The measured power efficiency reaches a maximum value of 78.8% at an output power of 40.5 dbm. At maximum efficiency, the quiescent drain current is 19% of the maximum DC current. The figure also includes simulation results for the same test conditions. Although good agreement between simulation and measurement results are obtained, the discrepancy at high power may be related to the self-heating in the device. At low output power, the differences between simulated and measured performance may be related to the switch mode operation of the model [102, 103, 104]. The power efficiency and output power as function of frequency are shown in Figure Power efficiency is greater than 60% over a frequency range of approximately 120 MHz. The 79

96 3.3. Class-F Amplifier Experimental Results Figure 3.18: Photograph of the 10 W class-f power amplifier. Rectified Voltage Power Meter Class-F PA 40 db Attenuator Driver RF signal generator Cooler Figure 3.19: The class-f amplifier test bench. bandwidth is primarily limited by the impedance variation of the input harmonic stubs near the fundamental frequency. Although a double stub input match is added to compensate for the harmonic stub impedances at the fundamental frequency, the network is inherently narrowband. This illustrates the trade-off between bandwidth and power efficiency which can result by shaping the gate waveform with harmonic terminations at the input. 80

97 3.3. Class-F Amplifier Experimental Results Modulated Performance The power efficiency of the class-f amplifier for a CW input signal was shown in Figure After characterizing the amplifier with CW test signals, the amplifier was tested with a 5 MHz WCDMA test signal. The WCDMA signal had a 8.8 db peak-to-average (PAR) power ratio and was generated using a Tektronix AWG70002A arbitrary waveform generator. Performance of the amplifier was measured without linearization. The measured output spectrums for the WCDMA signals are shown in Figure 3.22 with a resolution bandwidth (RBW) of 30 KHz. A summary of the adjacent channel leakage ratio (ACLR) and power efficiency as function of output power is shown in Figure In the figures, three different output power levels are identified for comparison. At point (a), the average output power is 35.1 dbm. The CW saturated output power is approximately 40.5 dbm (see Figure 3.20); therefore the peak power of the modulated signal at point (a) is compressed by about 3.4 db. The corresponding ACLR is dbc (decibels relative to the carrier) and the power efficiency is 46.1%. With the addition of digital predistortion, improvements in linearity of 15 db or more could be expected [105, 106]. The other two points, (b) and (c), are measured under back-off conditions and as expected linearity improves at the expense of power efficiency. 90 Solid: Measurement Dash: Simulation 41 Efficiency (%) Output Power (dbm) Input Power (dbm) Figure 3.20: Measured and simulated drain efficiency and output power as a function of input power for a CW test signal [reproduced courtesy of The Electromagnetics Academy]. 81

98 3.3. Class-F Amplifier Experimental Results Solid: Measurement Dash: Simulation Efficiency (%) Output Power (dbm) Frequency (MHz) Figure 3.21: Measured and simulated drain efficiency and output power as a function of frequency for a CW test signal [reproduced courtesy of The Electromagnetics Academy]. 10 Power spectrum density (db/rbw) a b c Frequency (MHz) Figure 3.22: Measured output spectrums for a WCDMA signal at three different output power levels: (a) 35.1 dbm (b) 33.4 dbm and (c) 31.6 dbm [reproduced courtesy of The Electromagnetics Academy]. 82

99 3.3. Class-F Amplifier Experimental Results (a) 32 Efficiency (%) (c) (b) (b) (a) ACLR (dbc) 10 (c) Output Power (dbm) 42 Figure 3.23: Measured drain efficiency and ACLR as a function of output power for a WCDMA signal [reproduced courtesy of The Electromagnetics Academy]. 83

100 3.4. Inverse Class-F Power Amplifier Table 3.8: Source and load pull harmonic impedances for the class-f 1 amplifier. P in (dbm) P out (dbm) P AE(%) Γ L (f 0 ) Γ L (2f 0 ) Γ L (3f 0 ) Γ S (f 0 ) Γ S (2f 0 ) Inverse Class-F Power Amplifier Although a class-f power amplifier has high power efficiency, the current switched class- F 1 amplifier can have even higher power efficiency because capacitive switching losses are reduced. In the class-f amplifier, the waveform shaping creates a switched voltage signal, while in the class-f 1 amplifier, the voltage waveform across the device is a half-sinusoid. The current switched class-f 1 can also have a larger dynamic range than the voltage switched class-f amplifier in terms of maintaining higher power efficiency under back-off conditions. This feature is shown later in Chapter 4 where class-f and class-f 1 rectifiers are compared. The main disadvantage of a class-f 1 amplifier compared to a class-f amplifier is the device utilization is slightly lower which means the maximum available power that can be delivered by a device is slightly higher in the class-f configuration Design Methodology A current switched class-f 1 amplifier is designed for the same 10 W Cree GaN device used in the class-f amplifier. Similar to the class-f design, harmonic matching networks are implemented in the input and output matching circuits to control the gate and drain waveforms. A second harmonic input match and a third harmonic output match are implemented as shown in Figure The required harmonic impedances at the device planes were determined from load pull test benches using the Cree large signal device model. The load pull results are summarized in Table 3.8 for a bias of V DD = 24 V and V GG = 2.8 V. The synthesis of the output match begins with the third harmonic network. The transmission line T L out2 is 90 at the third harmonic frequency and creates a short at plane B. Consequently the reflection coefficient looking to the right of plane B at the third harmonic is The addition of the series transmission line T L out1 modifies the phase to provide the match Γ L (3f o ) at plane A. The next step in the synthesis of the output circuit is to add transmission lines T L out3 and T L out4 to create the second harmonic match. Transmission line T L out4 is 90 at the second harmonic frequency which creates a short at reference plane C. The short is transformed through transmission line T L out3 and ideally maps to an open circuit at the device. However, the line length needs to be modified to compensate for the impedance contributions of the third harmonic network and to create the required reflection coefficient Γ L (2f o ) at plane A. The fundamental frequency output match is implemented with a single stub circuit consisting of T L out5 and T L out6. For the input matching network, a second harmonic termination impedance of Γ S (2f o ) is required at the gate reference plane (plane D in Figure 3.24). The second harmonic impedance is created by transmission line T L in3, with a length of 90 at the second harmonic frequency, 84

101 3.4. Inverse Class-F Power Amplifier and transmission line T L in4. The fundamental frequency input match is implemented with a single stub circuit consisting of T L in1 and T L in2. Finally, a series resistor (R g ) of 3.5 Ω is added to improve the stability of the device. V GG C 0 V DD C 0 TL in3 (λ o /4) TL in4 C in TL out2 (λ o /12) I DC TL out3 L DD Cout V in TLin1 TL in2 Rg TL M out1 1 TL out4 (λ o /8) TL out5 TL out6 V out E D A B C Harmonic Input Matching Network Harmonic Output Matching Network Figure 3.24: Schematic of the class-f 1 PA with output and input matching circuits and bias networks Experimental Results An experimental prototype of the class-f 1 amplifier was fabricated on a mm Rogers 4350 substrate with a dielectric constant of The transmission lines were implemented in microstrip and the dimensions were optimized using numerical simulations in ADS. The final design values for the matching networks are summarized in Table 3.9. The simulated drain voltage and drain current waveforms for the final class-f 1 amplifier design are shown in Figure Table 3.9: Microstrip transmission line lengths for the class-f 1 amplifier. T L out1 T L out2 T L out3 T L out4 T L out5 T L out6 T L in1 T L in2 T L in3 T L in4 in mm in degrees A photograph of the class-f 1 power amplifier is shown in Figure The performance of the amplifier was measured in a test bed similar to the class-f amplifier test bed shown in Figure The power efficiency of the amplifier for a CW input signal is shown in Figure 3.27 and reaches a maximum value of 83% at an output power about 40 dbm. These results are compared with the CW measurements for the class-f amplifier (see Figure 3.21) where the peak power efficiency is 78.8% at an output power of 40.5 dbm. The results confirm that the power efficiency of the class-f 1 is higher than the class-f amplifier. The results also shows that the power utilization in the class-f amplifier is slightly higher than class-f 1 and delivers 0.5 db more power at peak efficiency. 85

102 3.5. Wideband Inverse Class-F Power Amplifier Figure 3.25: Simulated drain voltage (solid) and drain current (dash) waveforms for the class- F 1 power amplifier. The waveforms are shown for the drain terminal of the packaged device. Output Inverse Class-F Power Amplifier Input Figure 3.26: Photograph of the class-f 1 power amplifier. 3.5 Wideband Inverse Class-F Power Amplifier The class-f and class-f 1 power amplifiers described in the previous sections are inherently narrowband. The harmonic impedance matching networks are designed for a specific frequency and the design process does not consider the synthesis of broadband matching networks. Interest in wideband power amplifiers is high because most modern wireless communication systems such as long term evolution (LTE), wideband code division multiple access (WCDMA) and world wide interoperability for microwave access (WiMax) have services on multiple frequency bands. For example, the Rogers Communication LTE wireless network in Canada 86

103 3.5. Wideband Inverse Class-F Power Amplifier Efficiency (%) Output Power (W) Input Power (dbm) Figure 3.27: Drain efficiency and output power as a function of input power for the fabricated class-f 1 PA. uses frequency bands spanning a frequency range from 700 MHz to 2600 MHz. Therefore, high efficiency power amplifiers are required to meet multi-band operation requirements. Another application of wideband power amplifiers is in the design of wideband RF rectifiers for wireless power and RF energy recycling circuits [107]. In this work, the RF rectifier application is the primary motivation for designing a wideband class-f type amplifier. Different techniques have been proposed to design wideband power amplifiers. These techniques include amplifiers with lossy matching networks[108], feedback amplifiers [109, 110], traveling-wave amplifiers (TWA) [111, 112], continuous mode power amplifiers [113, 114] and harmonically tuned methods [104]. Although lossy matching networks and feedback techniques are established methods of implementing wideband designs they usually lead to low power efficiency. Traveling wave amplifiers use a chain of device in a transmission line structure to create wideband responses but the area, size, and cost and can be high. Continuous mode amplifiers and harmonically tuned methods are more recent and examples of designs using these techniques are summarized in Table For this work, the harmonically tuned design approach [104] is selected as it is retains the underlying characteristics of the amplifier topology with the added goal of synthesizing wideband matching networks. These synthesis of wideband networks for switch-mode amplifiers also has other applications such as outphasing amplifiers where signals with broad bandwidth need to be amplified efficiently. Table 3.10: Wideband class-f/family amplifier designs comparison. Ref. BW (GHz), (%) P out (W) η d (%) Type 2008 [115] 0.8-4, Class-F 2010 [104] , Class-F [21] , Class-F 2012 [116] , Class-F 2014 [114] , Class-F This work , Class-F 1 87

104 3.5. Wideband Inverse Class-F Power Amplifier Design Methodology Fano [117] first presented fundamental design equations for the synthesis of wideband matching networks in The equations are transcendental and must be solved numerically. Recently, Dawson [118] has presented analytical closed-form solutions for alternate equations that can be used to synthesize wideband networks. Dawson s method to synthesize wideband lumped element matching circuits is used to design a wideband class-f 1 power amplifier. After the lumped element circuit is designed, it is transformed into a distributed matching network [104]. The steps in the synthesis of the matching circuits are as follows: 1. The network synthesis begins by specifying the bandwidth of the amplifier. If f 1 and f 2 are the lower and upper band edge frequencies, then the centre frequency is the bandwidth is and the fractional bandwidth is f 0 = f 1 f 2, (3.8) f = f 2 f 1, (3.9) F B = f 2 f 1 f 0. (3.10) For this design: f 1 is 650 MHz, f 2 is 1150 MHz, f 0 is 865 MHz, f is 500 MHz, and the fractional bandwidth is 58%. 2. Use load pull measurements at the fundamental frequency over the operating frequency range to construct an equivalent output circuit of the device. The circuit consists of a shunt resistance R 0 and shunt capacitance C out. The resistance is the best fit load line and the capacitance is the best fit to the output capacitance of the device. 3. Based on the fractional bandwidth and the impedance transformation ratio from the device load line to the output load resistance (R L ), select a lowpass filter prototype. For this design, the fractional bandwidth is 58% and an odd order prototype with n = 3 is selected. The π network configuration is also selected such that the first shunt capacitance in the lowpass prototype can be associated with the output capacitance of the device. See Figure 3.28(a). 4. Use equations in [118] to calculate the normalized admittance values for the lowpass filter prototype. The values depend on the terminal resistances of the network, the device capacitance, and the relative bandwidth of the network. 5. Frequency and impedance scale the lowpass prototype. After scaling, the input terminal resistance is R 0 at the device port and the first shunt element C 1 is equivalent to the device capacitance C out. Note that the output port impedance is not 50 Ω because the impedance scaling is done to match the input port resistance to the device load line. The output port impedance is adjusted by creating in step 7 using a capacitive impedance transformer. 88

105 3.5. Wideband Inverse Class-F Power Amplifier 6. The lowpass network is transformed into a bandpass network with a centre frequency f 0. See Figure 3.28(b). 7. Use a Norton transformation in the filter to shift the output terminal impedance to 50 Ω. See Figure 3.28(c). The transformation creates a capacitive impedance transformer which can be adjusted to match the output port. 8. Convert lumped element resonators into equivalent transmission line resonators. The final network consists of microstrip lines and one discrete capacitance. 9. Verify that the input port impedance at the second harmonic has high impedance and is not a short circuit. The current switched class-f 1 amplifier has odd harmonic current components and even harmonic voltage components. Therefore, the voltage requires an open impedance at the second harmonic. Since the network is broadband, it is difficult to predict and control the second harmonic impedance. However, based on work by Saad [104], he shows that the power efficiency of the amplifier remains high providing the second harmonic impedance has a reflection coefficient far away from a short circuit. 10. The same procedure is repeated for the input matching network. With this design procedure, a wideband F 1 amplifier with fundamental and second harmonic matching is implemented Lumped Element Output Matching Network From Dawson s paper [118], the normalized admittances in the lowpass filter prototype are found from the following equations: Q = R 0 C 1 ω 0 (3.11) ω 0 = 2πf 0 (3.12) g j = g 0 = 1 (3.13) g 1 = 1 ( 1 Q ω 0 ) g 0 (3.14) 1 g j 1 (k j 1,j ) 2 for j = 2 to n (3.15) g n+1 = 1 D( 1 Q ω 0 )g n (3.16) For these equations, n is the order of the lowpass prototype, and k i,j and D are given by (long) equations in [118]. In Equation (3.11), R 0 is the load line resistance and C 1 is the device output capacitance. Values for R 0 and C 1 can be found from load and source pull simulations at different frequencies. The load pull at the fundamental frequency includes a second harmonic open and a 89

106 3.5. Wideband Inverse Class-F Power Amplifier g 0 g 1 g 2 g 3 g 4 1 L 2 2 Load Line R 0 Device Model Device Capacitance C 1 C 3 (a) R L 1 L 2 C 2 2 R 0 L 1 C 1 C 3 L 3 R L (b) Device Model Impedance Transformer L C 2 R 0 L 1 C 1 C 4 C 3 L 3 (n 2 T L (n 2 T R L) 3) R L (c) Norton Figure 3.28: Different steps for design of a lumped element matching network: (a) lowpass network with normalized admittances g j ; (b) bandpass matching network; (c) Norton transformation to increase output impedance. third harmonic short. Once the load pull data is extracted, mean values for R 0 and C 1 must be found. The real part of the load pull data can be averaged to find R 0 and a linear fit to the imaginary part can be used to find C 1 [119]. Another method is to directly use midband load pull data [104]. The latter method is used here and the input and output impedances are summarized in Table Focusing on the synthesis of the output match, the conjugate impedance of Z L,opt is used to estimate the equivalent device model. The equivalent circuit values are R 0 = 52.3 Ω and C 1 = 4.31 pf. Equations (3.11) through (3.16) are evaluated for n = 3 to give normalized lowpass prototype filter values in Table The normalized lowpass prototype admittances g k are then impedance and frequency scaled to admittances gf IS k. The scaled values and the corresponding lowpass element values are shown in Table 3.12 and Figure In order to prepare the lumped element network for conversion into a distributed network, the value of C 1 = 5.13 pf is increased to be slightly larger than C out. Capacitance C 1 is partitioned later into C out and a second shunt capacitance which is combined into a shunt resonator. 90

107 3.5. Wideband Inverse Class-F Power Amplifier Table 3.11: Results of the load/source pull simulations for Z Lopt and Z Sopt. Freq. (MHz) P in (dbm) P out (dbm) P AE(%) Z Lopt (Ω) Z Sopt (Ω) j j18 Table 3.12: Admittance parameters and extracted values for a third order network. g 1 ( ) g 2 ( ) g 3 ( ) g 4 ( ) gf IS 1 gf IS 2 gf IS 3 gf IS e e e R 0 (Ω) C 1 (pf) L 2 (nh) C 3 (pf) g 0 1 g g g g L R C C R L 47.6 Figure 3.29: Impedance and frequency scaled lumped element lowpass network for synthesizing a wideband output match. After impedance and frequency scaling, the lowpass network is transformed into a bandpass network using a center frequency of f 0 and bandwidth f. The lumped element bandpass network is shown in Figure C pF 1 L nH 2 R Ω C pF L nH C pF L nH R L 47.6Ω Figure 3.30: Lumped element output network after applying a lowpass to bandpass transformation. 91

108 3.5. Wideband Inverse Class-F Power Amplifier As a final step in the lumped element synthesis procedure, the output resistance of 47.6 Ω needs to be increased to 50 Ω. Through a Norton transformation applied to C 2 and C 3, an impedance transformer can be constructed with a transformation ratio of n T. With reference to Figure 3.31(a), after using the capacitive network in Figure 3.31(b), the modified output load resistance R L is n2 T R L. For the output matching circuit an impedance transformation ratio (n T ) of is required. The transformed component values for the output matching network are shown in Figure L 3 R L n 2 T L 3 n 2 T R L Z L (a) n 2 T Z L Z 1 n T Z 1 (n T 1) n T Z 1Z 2 Z 1 + (1 n T )Z 2 Z i Z i n T Z 1 Z 2 Z o n 2 T Z o (b) Figure 3.31: Impedance transformed output network (top) and the corresponding Norton transformation to create the impedance transformation (bottom). L nH C pF 1 2 R Ω C pF L nH C pF C pF L 3 8.7nH R L 50Ω Norton Figure 3.32: Bandpass output matching network with an impedance transformer to match the output to 50 Ω. A similar design procedure can be followed to constructed the input matching network. For the input network, the optimal source impedance at the fundamental frequency is Z Sopt = j18 Ω (see Table 3.11). The corresponding normalized lowpass prototype admittances and the frequency and impedance scaled admittances are summarized in Table The final input matching network is shown in Figure

109 3.5. Wideband Inverse Class-F Power Amplifier Table 3.13: Admittance parameters for low-pass network and extracted values for the final band-pass structure corresponding to the input matching network. g 1 g 2 g 3 g 4 gf IS 1 gf IS 2 gf IS 3 gf IS 4 ( ) ( ) ( ) ( ) e e e R 0in C 1in C 2 C 3 C 4 L 1 L 2 L 3 (Ω) (pf) (pf) (pf) (pf) (nh) (nh) (nh) L nH C pF 1 2 R 0in 96Ω C pF L nH C 4 0.2pF C pF L nH R L 50Ω Figure 3.33: Bandpass input matching network by Norton transformation (n T = ) Distributed Matching Networks At this point, lumped element matching networks have been synthesized for the amplifier and the remaining step is to convert the networks into distributed structures using transmission lines. The first step is to divide capacitance C 1 into three parallel capacitances consisting of C out, C 11 and C 12 as shown in Figure The lumped elements can then be grouped with adjacent circuit elements to create circuit networks that can be replaced with equivalent transmission line structures. There are two shunt resonators in the circuit: 1) C 11 and L 1 and 2) C 3 and inductor L 3. The LC shunt resonators can be implemented as 90 short circuit transmission lines as shown Figure 3.35 [120]. The π-network consisting of C 12, L 2 and C 4 is equivalent to a short transmission line with characteristic impedance Z o = L 2 /C 4 [121]. The only lumped element component which cannot be incorporated into a transmission line structure is C 2, but this can serve as a DC blocking capacitor which is required in the circuit. The final output matching network is shown in Figure The same procedure can be used for the input matching circuit and the final transmission line input matching circuit is shown in Figure Microstrip transmission lines are designed to implement the distributed matching networks. The substrate is a Rogers RO4350 dielectric with a thickness of mm and a dielectric constant of The final microstrip dimensions for each transmission line are shown in Table Before proceeding to the fabrication of an experimental prototype, it is important to verify the matching network designs and ensure the networks provide the required impedances at the fundamental, second and third harmonic frequencies. The matching network designs 93

110 3.5. Wideband Inverse Class-F Power Amplifier L nH C pF 1 2 R Ω C out 4.31pF C pF L nH C pF C pF C pF L 3 8.7nH R L 50Ω Transistor T L 1 T L 2 T L 3 Figure 3.34: Dividing the capacitance C 1 into three parallel capacitances to reform the output structure as a distributed network. L C TL θ = 90 Z 0 = (π/4)ωl Figure 3.35: Equivalent transmission line circuit for a shunt resonator. Drain TL 2 C 2 50 Ω TL 1 TL 3 Figure 3.36: Distributed output matching network. 50 Ω C S2 TL S2 Gate TL S3 TL S1 Figure 3.37: Distributed input matching network. are verified in a simulator and the device plane impedances seen looking into the matching networks are measured. Beginning with the fundamental frequency, a comparison of the network impedances versus the load pull impedances are shown for the input and output matching networks in Figure The load pull measurements correspond to the points and the simulated results correspond to the contours. As shown, the networks synthesize fundamental load impedances that are close to the load pull values. Next, the second harmonic impedances are simulated. The results are shown in Figure Since this is a current switched class F 1 amplifier, the second harmonic is ideally a 94

111 3.5. Wideband Inverse Class-F Power Amplifier Table 3.14: Microstrip transmission line lengths and widths for load and source matching networks. T L 1 T L 2 T L 3 T L S1 T L S2 T L S3 Length (mm) Width (mm) Figure 3.38: The fundamental frequency impedances of the input and output matching networks. open circuit. Other references on wideband amplifier designs [104] show that power efficiency is relatively insensitive to an exact second harmonic impedance providing the impedance falls outside a region around a short circuit. The simulated results for this design show that the second harmonic impedances fall on the open circuit side of the Smith chart well away from short circuit impedances and therefore the second harmonic impedance is satisfactory. As a final check on the matching networks, the third harmonic impedance is evaluated. The results for the output matching network are shown in Figure Over the third harmonic frequency range, the network should present a short circuit and the contour lies in the short circuit region of the Smith chart. The plot includes a wide frequency sweep range and includes the fundamental and second harmonic frequency ranges as well. The harmonic impedance data shown in Figure 3.40 is consistent with the design goal of implementing a wideband class F 1. A similar result is obtained for the input matching network. 95

112 3.5. Wideband Inverse Class-F Power Amplifier Figure 3.39: The second harmonic impedances of the input and output matching networks. Figure 3.40: Wide frequency range sweep of the impedances of the output matching network. Fundamental, second harmonic and third harmonic frequency ranges are shown. 96

113 3.5. Wideband Inverse Class-F Power Amplifier Experimental Results A photograph of the wideband class F 1 power amplifier is shown in Figure Similar to all the other amplifier designs, a 10 W Cree GaN HEMT is used (model CGH40010F). Figure 3.41: Photograph of the wideband class-f 1 power amplifier. The simulated and measured power efficiency of the wideband class-f 1 amplifier for a CW input signal at different frequencies are shown in Figure The measured power efficiency reaches a maximum value of 79.2% with an output power of 8.83 W. Power efficiency is greater than 60% over a frequency range of approximately 600 MHz Measurement Simulation 80 Efficiency (%) Frequency (MHz) Figure 3.42: Measured and simulated drain efficiency of the wideband class-f 1 PA as a function of frequency for a CW test signal. 97

114 3.6 Chapter Summary 3.6. Chapter Summary In this chapter, the design methodology, simulation results and experimental results were shown for three different class-f power amplifiers. The designs were for a narrowband switched voltage class-f amplifier, a narrowband switched current class-f 1 amplifier, and a wideband class-f 1 amplifier. All the experimental results use a packaged Cree 10 W GaN HEMT device which makes comparison of experimental results insightful. In the voltage switched class-f amplifier, a comprehensive study of the harmonic input matching circuit was made. A level 3 device model was used for this work, and from the study, it is concluded that input matching for the second harmonic is very important while the third harmonic has little effect on the overall power efficiency of the amplifier. An experimental prototype of the amplifier was built which included third harmonic input and output matching circuits which is the first work to report third harmonic input matching in a class-f amplifier. The experimental results of the voltage switched class-f amplifier are compared with a similar current switched class-f 1 amplifier. The results show that the current switched amplifier has higher peak power efficiency, which is attributed to lower capacitive switching losses compared to the voltage switched amplifier. Conversely, the current switched power amplifier delivered slightly less power at peak efficiency, about 0.5 db less, which shows that the device utilization is slightly higher in a voltage switched topology. A wideband current switched class-f 1 amplifier design was also built using a network synthesis technique that implements a wideband fundamental frequency match. It was also shown that the wideband network has a high second harmonic impedance and a low third harmonic impedance over the bandwidth of the design. In the next chapter, the theory of time-reversal duality is applied to reconfigure these amplifier designs into RF rectifiers. The experimental results presented in this chapter for the amplifier configuration will be used to compare with experimental results for the RF rectifier configuration. 98

115 Chapter 4 Class-F RF Synchronous Rectifiers This chapter focuses on the design and implementation of high efficiency and high power GaN HEMT class-f and class-f 1 synchronous rectifiers. The work provides new bench marks for high power RF synchronous rectifiers operating at a frequency of 1 GHz and power levels of approximately 10 W. The chapter begins with a brief overview of the time reversal duality principle which is used to convert switch-mode power amplifier circuits into equivalent synchronous rectifier circuits. Time reversal duality concepts have been used for several decades in power electronic circuit applications, but the application to RF circuits is much more recent. There are also interesting questions raised when applying time reversal duality to circuits with loss and the implication of loss in terms of constructing circuit duals is investigated. The clarification of these subtle points has not been discussed in the literature and the primary implication is related to the operating point of the device when comparing amplifier and rectifier duals. Applying the principle of time reversal duality to class-f switch-mode amplifiers, three different RF synchronous rectifiers were designed using a 10 W GaN HEMT device from Cree. These rectifiers are a narrowband class-f rectifier, a narrowband class-f 1 rectifier, and a wideband class-f 1 rectifier. In all cases, the rectifier is compared to the amplifier dual and the work provides new references for comparing circuit duals. Most literature references describing implementations of RF rectifiers typically use the principle of duality to create rectifiers without providing direct comparisons with the amplifier circuit under equivalent measurement conditions. Other highlights of the research work include a comparison of class-f and class-f 1 rectifiers under constant load conditions. The optimal load resistance which maximizes RF to DC conversion efficiency is dependent on the RF input power to the rectifier. A comparison of the class-f and class-f 1 rectifiers shows that the class-f 1 is more robust in terms of operation with a fixed load compared to a class-f rectifier. 4.1 The Principle of Time Reversal Duality The concepts of duality are commonly used in circuit theory. Examples include transformations from Thévenin to Norton equivalent circuits and the synthesis of equivalent networks with series or parallel circuit elements. Another example is the duality between voltage and current waveforms. This is illustrated by comparing (a) and (b) in Figure 4.1; these figures are based on the work of Hamill [74]. The network N can be transformed into a network dual N vc where the current and voltage waveforms are duals. The duality between current and voltage waveforms is commonly used in switch-mode power amplifiers designs; for example, class-f amplifiers are designed to switch voltage, while class-f 1 are designed to switch current. 3 Parts of Chapter 4 have been published in two articles. Reprinted with permission from ELEX and EuMC [75, 76]. 99

116 4.1. The Principle of Time Reversal Duality N I V V I t t (a) N vc I vc V vc V vc I vc t t (b) N tr I tr V tr V tr I tr t t (c) Figure 4.1: (a) Network N and its current and voltage, (b) network N vc, a voltage and current dual of N, and (c) network N tr, a time reversal dual of N. Another duality was recognized by Hamill [74, 122] which he called time reversal duality. The time reversal (TR) concept is illustrated by comparing the current-voltage relations for network N in Figure 4.1(a) with the current-voltage relations for the TR dual, network N tr in Figure 4.1(c). In the TR dual, the voltage across the network is V tr = V ( t) and the current into the network is I tr = I( t). As a consequence of the sign change in the current, power flow is reversed at the terminals of network N tr relative to the original network N. More generally, for an n-port network, power flow is reversed at all n terminals. An example of a two port network is shown in Figure 4.2. If network N is an amplifier, the primary input power is the DC drain supply P 1 and the output is the amplified RF signal P 2. The TR dual, network N tr, is a rectifier circuit where RF input power P 2 is converted into a DC power P 1. A general method of constructing a TR dual can be established [74, 122] and a summary of the circuit relations is shown in Table 4.1. Capacitor and inductors are assumed to be lossless and the circuit elements are unchanged in a TR dual. Resistance on the other hand is 100

117 4.1. The Principle of Time Reversal Duality P 1 N P 2 P 1 N P 2 tr Figure 4.2: The direction of energy flow in a network and its TR dual. Table 4.1: Time reversal relations for circuit components. Original Network (N) TR-dual Network (N tr ) Voltage V (t) V tr (t) = V ( t) Current I(t) I tr (t) = I( t) Power P (t) P tr (t) = P ( t) Inductance L L tr = L Capacitance C C tr = C Resistance R R tr = R dissipative and because power flow is reversed, the circuit dual must have negative resistance. Obviously negative resistance is not physically realizable except with active circuits, and therefore the most common application of TR duality is in circuits where dissipative losses are small. Examples include power electronic circuits which usually operate with very high efficiency. At microwave frequencies, dissipative losses are more significant and power loss can be substantial. This then motivates the question: how should losses be handled in constructing circuit duals? More will be said about this later. The other implication of TR duality is that active devices must be bidirectional and operate under time reversed conditions. For an active device like a MOSFET or HEMT, this means that a device which operates in quadrant I of the IV plane in an amplifier circuit, must operate in quadrant III in a rectifier circuit [73]. The IV symmetry is not perfect in practical devices, but in theory they have symmetry because the designations of source and drain nodes are made relative to the polarity of the drain supply. The quadrant I versus quadrant III device operation is discussed in more detail in the next section. 101

118 4.2. Definitions of Equivalence for Amplifier and Rectifier Duals 4.2 Definitions of Equivalence for Amplifier and Rectifier Duals Using the principle of time reversal duality, a switch-mode power amplifier circuit can be transformed into a synchronous rectifier circuit as shown in Figure 4.3. In the rectifier mode, the output port of the amplifier becomes an input port and the DC supply port of the amplifier is replaced by a DC load, R DC. If the amplifier and rectifier were 100% efficient, then R DC would be the equal to V DD /I DC in the amplifier circuit. For lossy circuits, the value V DD /I DC is an approximation and the value of R DC needs to be swept to find the optimal load resistance for a specific input power. When loss is present in the amplifier and rectifier, we need to re-evaluate how the two circuits are compared in the context of time reversal duality and relate this to measurements of power and efficiency. In the amplifier, a source power of P DC is required to deliver a RF load power of P out, and in the rectifier circuit, a RF source power of P in is required to deliver a DC load power of P DC. Now consider two different test conditions. In the first case, the rectifier efficiency is measured under the condition where the RF powers are matched: the output power P out of the amplifier is the same as the input power P in of the rectifier. The matched RF power condition falls out naturally from a test configuration where the amplifier and rectifier are arranged as a series cascade. In this case, the RF output of the amplifier is connected to the RF input of the rectifier dual and RF powers are equal (P out = P in ). The disadvantage of this test condition is that the DC input power to the amplifier and the DC output power from the rectifier differ by the product of the efficiencies of the amplifier and the rectifier. A second method is to measure the two circuits under conditions where the input source powers are identical. In this case, the DC source power for the amplifier (P DC ) is equal to the RF input power (P in ) for the rectifier. Under conditions of equal source powers, the amplifier and rectifier should have similar power efficiencies and the power delivered to the loads should be similar. The consequence of matching source powers is that the RF input power to the rectifier is scaled relative to the RF output power delivered by the amplifier. The advantage of the second method is that the operating points of the devices in the amplifier and rectifier are closer than in the first method where the losses in the amplifier and rectifier are accumulated. In this work, we use method two as a benchmark for comparing the amplifier and rectifier based on the goal of minimizing the difference in the operating points of the active device. The difference between the two test conditions can also be illustrated in terms of the dynamic IV characteristics of the amplifier and rectifier. With reference to Figure 4.4(a), the dynamic IV curve is shown for the class F amplifier described in Chapter 3. The expected value of the drain voltage is equal to V DD and the expected value of the drain current is equal to I DC. The corresponding DC operating point is denoted as point A on the IV curve. In the rectifier circuit, as shown in Figure 4.4(b), the on-state is in quadrant III instead of quadrant I as in the amplifier circuit. The average DC current flow is out of the drain terminal when the device is on; therefore the device must operate in quadrant III to deliver negative drain current. Similar to the amplifier, the expected value of the drain voltage is V DC and the average value of the drain current is I DC. Since V DC is positive and I DC is negative, the corresponding DC operating point for the rectifier falls in quadrant IV. We now consider the two test conditions described earlier. If the RF powers of the amplifier and rectifier are matched, the corresponding DC operating point for the rectifier is at point B shown in the inset of Fig. 4.4(b). On the other hand, if the input source powers of the amplifier 102

119 4.2. Definitions of Equivalence for Amplifier and Rectifier Duals V GG V DD R DC = V DD /I DC (a) I DC P DC V s R s L GG Input Matching L DD M 1 Output Matching P out R L VL V s (b) R s Input Matching V GG P DC I DC R DC P L GG L in DD M 1 V DC Output Matching R L V RFin (c) V GG P DC V DC I DC R DC Sampler P in Input Matching M 1 L GG L DD Output Matching R L V RFin Phase Shifter Figure 4.3: Block diagrams of (a) a power amplifier, (b) synchronous rectifier dual, and (c) synchronous rectifier with feedback to provide gate drive. and rectifier are equal, then the corresponding rectifier operating point is point C. If circuit losses were identical for the amplifier and rectifier, the DC operating point for the rectifier would be point D which mirrors the amplifier DC operating point obtained by changing the sign of I DC. A comparison of the operating points shows that point C is closer to point D which is the operating point dual of the amplifier. Therefore, a comparison of the amplifier and rectifier are made under the condition of equal input source power conditions rather than equal RF power conditions. As a final remark on the dynamic IV curves for the amplifier and rectifier, it is noted that 103

120 4.2. Definitions of Equivalence for Amplifier and Rectifier Duals A 1 A I ds (A) 0 1 I ds (A) B C D 2 (a) 2 (b) V ds (V) V ds (V) Figure 4.4: Dynamic load lines for: (a) a class-f amplifier (b) a class-f rectifier. the effective on resistance of the rectifier is lower than in the amplifier. In quadrant III, the reverse biased drain supply flips the gate control of the device to depend on the drain supply. Therefore, in quadrant III, the device effectively turns on more as the drain swings more negative. This observation is consistent with measured IV device characteristics reported by other researchers for quadrant III device behaviour [123]. From the DC device characteristics we therefore conclude that the effective on resistance of the rectifier in quadrant III is expected to be slightly less than the amplifier on resistance in quadrant I. Also, the loop area under the dynamic IV curve for the amplifier is larger in quadrant I than for the rectifier which means current/voltage overlap losses are slightly higher in the amplifier than the rectifier. These factors lead to the hypothesis that the rectifier efficiency is expected to be higher than the equivalent amplifier efficiency. At this point we have established a duality between the amplifier in Figure 4.3(a) and the synchronous rectifier in Figure 4.3(b). Although a rectifier dual has been constructed from the amplifier, the circuit in (b) requires a separate input gate drive similar to the amplifier. The separate gate drive is inconvenient for rectification purposes and instead a feedback path which samples the RF input signal is usually used to generate the gate drive signal. This is shown in circuit (c). Since the gate must be switched with the correct phase relative to the drain voltage and drain current waveforms, a delay line or phase shift circuit is required. When the gate drive is derived from the RF input signal, the circuit is called a synchronous rectifier circuit [73]. Another variation of synchronous rectifiers is a self-synchronous rectifier where the intrinsic device capacitance C gd is used in conjunction with a gate termination impedance to create the required feedback signal for switching the gate [78]. In all the circuits shown in this work, a directional coupler is used to sample the RF input signal and a delay line is used as a phase shift circuit. In this way, any amplifier can be converted into a synchronous rectifier by generating the appropriate gate drive signal from the RF input. 104

121 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Table 4.2: Some recently published results for RF synchronous rectifiers Ref. Type Device f (GHz) P DC η (%) [73] class-e E-PHEMT mw 83 synch. [78] class-c GaN HEMT W 64.4 self-synch. MMIC [78] class-c GaN HEMT W 63.9 self-synch. MMIC [82] class-f 1 GaN HEMT W 85 self-synch. [79] class-e E-PHEMT mw 88 self-synch. [79] class-e E-PHEMT mw 77 self-synch. [80] class-e GaAs PHEMT mw 77 self-synch. [81] class-f GaAs PHEMT mw 68 self-synch. [83] class-f E-PHEMT mw 85.4 self-synch. [124] class-ab GaN HEMT W 52 self-synch. MMIC This class-f GaN HEMT W 81.3 work synch. 4.3 High Efficiency GaN HEMT Class-F Synchronous Rectifier As will be shown, the power efficiency of a rectifier circuit is similar to the power efficiency of an amplifier circuit providing they are tested under equivalent conditions where the input power to the circuits is the same. Therefore, a high efficiency rectifier design begins with a high efficiency amplifier design. In this section we present experimental results for the implementation of a 10 W synchronous class-f rectifier. The rectifier design is derived from the class-f amplifier described earlier in Chapter 3. Other researchers have reported on GaN class-f 1 rectifier designs or low power class-f rectifiers using phemts, and this appears to be the first work for a high power class-f design. A comparison of this design with other published results is given in Table 4.2. Experimental results are also shown to compare the performance of the amplifier and the rectifier dual under equivalent input power conditions. In this way, conclusions can be made about the relative power efficiencies of the dual circuits Rectifier Test Bench and Efficiency Definitions For comparison with the rectifier, the class-f PA in Chapter 3 (and Appendix-A) was first re-tested. The device was biased with a 27 V drain supply and a gate bias of -2.6 V. At a frequency of 985 MHz and for a sinusoidal input signal of 24.5 dbm (282 mw), the amplifier delivers 8.3 W to a 50 Ω load. Under these conditions, the drain current is A and the 105

122 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Rectified Voltage Power Meters B A Couplers Class-F PA Class-F Rectifier RF signal generator Figure 4.5: The class-f rectifier test bench. corresponding drain efficiency is 77.5%. The equivalent Thévenin source impedance of the drain supply, R DC, is 67 Ω and the DC supply provides a source power of 10.7 W. After testing the amplifier circuit, the amplifier was reconfigured as a synchronous class-f rectifier. A photograph of the rectifier test bench is shown in Figure 4.5. An explicit feedback loop is added to the amplifier to provide a gate drive signal from the RF input port as shown in Figure 4.3(c). A directional coupler (A) samples the RF input signal and a variable delay line is used to adjust the phase of the sampled signal to synchronously switch the GaN power device. The measured sampling level of coupler A is db. The second port of coupler A is connected to a power meter and calibrated to measure the reflected power at the input of the rectifier. Since the input RF power is high and cannot be delivered by standard test equipment, another class-f power amplifier is used to generate the RF source signal. A second directional coupler (B) is placed in series between the rectifier and amplifier to measure the available RF input power (P in ) delivered to the rectifier. The input power is calibrated to measure power at the interface between the two couplers. Two definitions of RF to DC conversion efficiency which have been used in the literature to report results for RF rectifiers are [80, 81] η r = P DC P in P ref (4.1) and [82] η r = P DC P in. (4.2) In these equations, P in is the incident or available power from the RF input source and P ref is the amount of power reflected back from the input port because of mismatch loss. The 106

123 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier difference in the power efficiency measures is that in (4.1), the power efficiency accounts for mismatch loss at the input of the rectifier, while in (4.2) the power efficiency is burdened by input mismatch loss. From a system perspective, equation (4.2) is preferred because it includes mismatch loss which is inherently present in the design of the rectifier circuit. If mismatch loss is reduced by improving the design, then the corresponding power efficiency will be improved. On the other hand, the efficiency measure in equation (4.1) accounts for mismatch loss and gives insight into the maximum available power efficiency which can be obtained provided the input is perfectly matched. Both measures of power efficiency are used in the literature and it is important to identify which power efficiency measure is used for comparing results. Unless otherwise stated, equation (4.1) which includes mismatch loss is used in this work as it is deemed to be more appropriate for practical circuits where the terminal interface impedances are usually specified and circuits must inherently include matching Experimental Results As a starting point for evaluating the rectifier, the initial conditions were configured to be the dual of the class-f amplifier where the input source powers of the amplifier and rectifier are equal. The RF input power was set to 10.7 W (40.3 dbm) at a frequency of 985 MHz, the same as the DC source power for the amplifier. The DC load resistance, R DC, and phase shifter are adjusted to optimize the power efficiency of the rectifier. The corresponding DC load power is 8.7 W and the RF to DC conversion efficiency is 81.3% for an optimal load resistance of 58 Ω. These numbers are compared to the equivalent class-f amplifier under identical input source power conditions which showed a slightly lower power efficiency of 77.5% with an equivalent DC source resistance (R DC ) of 67 Ω, slightly higher than R DC in the rectifier dual. This shows that even under equivalent source power conditions where the DC power supplied to an amplifier is equal to the RF power supplied to a rectifier, there are small differences attributed to device operation in quadrant I versus quadrant III. The rectifier power efficiency of 81% was calculated using (4.2) which includes input mismatch loss. The effect of mismatch loss on the overall rectifier power efficiency can be found by comparing the efficiency without mismatch loss using equation (4.1). Under the stated test conditions, the reflected RF power at the input port of the rectifier is 28.2 dbm and the input reflection coefficient is db. The corresponding RF to DC power efficiency without mismatch loss is 86.5%, about 5% better. A summary of the class-f amplifier and rectifier circuit duals tested under identical source power conditions are shown in Table 4.3. Other test results for the rectifier are shown in Figures 4.6 through 4.8. In Figure 4.6, the measured power efficiency and DC load power are shown as a function of the DC load resistance R DC. These measurements are made at a frequency of 985 MHz with a RF input power of 10.7 W. As shown, the optimal load resistance (R DC ) is approximately 58 Ω. Figure 4.7 shows the power efficiency of the rectifier as a function of the RF input power. It shows that power efficiency peaks for an input RF power of 10.7 W (40.3 dbm). Power efficiency remains above 50% for input power above 34 dbm and the maximum power delivered by the rectifier is 11.3 W at an efficiency of 78%. Compared to other published work, this result appears to be the highest reported DC power which has been measured for a RF synchronous class-f rectifier circuit. The rectifier performance as a function of frequency is shown in Figure 4.8. Efficiency and load power peak at a frequency of 985 MHz. The bandwidth of the rectifier is dependent on the bandwidth of the original amplifier design. In this case, the multiharmonic matching 107

124 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Table 4.3: Comparison of class-f amplifier and rectifier experimental results. Parameter Amplifier Rectifier Frequency 985 MHz 985 MHz Gate bias -2.6 V -2.6 V DC supply/load resistance R DC = 67 Ω R DC = 58 Ω Input source power P DC = 10.7 W P in = 10.7 W Load power P out = 8.3 W P DC = 8.7 W Power efficiency η a = 77.5% η r = 81.3% Power efficiency without mismatch loss - η r = 86.5% networks are narrowband and a power efficiency of 50% is maintained over a frequency range of about 50 MHz. The power efficiency measurements shown in Figures 4.7 and 4.8 include mismatch loss. If mismatch loss were reduced by improving the input match, then power efficiency would increase. Measurements of mismatch loss were made over frequency and the results are shown in Figure 4.9. The results show that mismatch loss reduces power efficiency by approximately 5% at 985 MHz and the loss increases as the frequency deviates from center frequency of the design. The mismatch loss is directly related to the bandwidth of the output match in the amplifier and improvements in the bandwidth of the matching circuit will reduce mismatch loss over frequency. This is not any different than an amplifier which also has reduced efficiency when the load match deviates from the optimum match. Later, in Section 4.5, results for a wideband class-f amplifier and rectifier are shown. 108

125 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Efficiency (%) Output DC Power (W) Resistance (Ohm) Figure 4.6: Measured RF to DC conversion efficiency and output DC power as a function of load resistance for a class-f rectifier. Efficiency (%) PRF-in (dbm) Figure 4.7: Measured power efficiency and output DC power as a function of RF input power for a class-f rectifier Output DC Power (W) 109

126 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Efficiency (%) DC Power (W) Frequency (MHz) Figure 4.8: Measured power efficiency and output DC power as a function of frequency for a class-f rectifier Efficiency (%) Without mismatch loss With mismatch loss Frequency (MHz) Figure 4.9: Class-F rectifier power efficiency with and without mismatch loss. 110

127 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Class-F Amplifier and Rectifier Power Efficiency Analysis Further insight into the small differences between the power efficiency of the amplifier and rectifier duals can be obtained through analysis. It will be shown that switch losses do not lead to perfect duality and dissipation inherently modifies the voltage waveform in the rectifier relative to the amplifier. Also, device operation in quadrant I versus III modifies the overlap losses in the amplifier and rectifier. For the analysis, consider the class-f amplifier shown in Figure 4.10 and the waveforms shown in Figure 4.11(a). In class-f, the ideal drain voltage, v d,p A (θ), is a square wave waveform with a 50% duty cycle. The Fourier series for the waveform consists of a fundamental frequency component at f 0 and only odd harmonics. The ideal current waveform, i d,p A (θ), is a half sinusoidal signal and the Fourier series for the waveform has a fundamental frequency component at f 0 and only even harmonics. V DD I DC Z L (f0) L DD i d,p A (θ) Vg v d,p A (θ) d i C (θ) M 1 C out C B TL 1 (λ o /4) L 0 C 0 Z L V out Output Matching Network Figure 4.10: A class-f power amplifier with a series quarterwave transmission line. The shape of the voltage and current waveforms in the circuit depends on the harmonic impedances presented to the switching device at the drain node, d. The tank circuit is antiresonant at the fundamental frequency f 0 which forces the fundamental frequency component of the drain current to pass through the load, R L. If the Q of the tank circuit is sufficient high (Q > 5), then the impedance of the tank is small (ideally a short) at all the harmonic frequencies. The transmission line is a quarter wavelength long at the fundamental frequency, and the transmission line transforms the harmonic short created by the tank circuit into a short circuit at the drain node d for even harmonics, and an open circuit at node d for odd harmonics. Together, these conditions create impedance conditions at node d that lead to the class-f waveforms. The series transmission line also serves as a matching circuit, and the characteristic impedance of the line, Z o, can be used to transform the load resistance, R L, to a fundamental frequency load line resistance, R f0, where R f0 = Re[Z L (f o )]. The load line resistance R f0 is used later in the power efficiency equations and is usually obtained from a load pull simulation of the device. The class-f amplifier has three primary loss factors which are analyzed. 1. P Ron : conduction losses due to finite switch resistance; 2. P cap : capacitive switching losses resulting from the discharge of the voltage stored on 111

128 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier i d,p A I d,max V d,max v d,p A and 0 π 2π θ (a) i d,rec V d,max v d,rec and 0 π 2π θ (b) I d,max Figure 4.11: Drain voltage and drain current waveforms for: (a) a class-f power amplifier and (b) a class-f rectifier. the output capacitance of the device, C out ; 3. P overlap : losses created during switching transitions when the drain voltage and drain current waveforms overlap. Each of these loss mechanisms modifies the ideal drain and current waveforms in the class- F amplifier, and non-ideal waveforms are analyzed from the superposition of the different loss mechanisms. Therefore, each loss mechanism is assumed to be independent and the losses are combined to estimate the overall power efficiency of the class-f amplifier. The corresponding losses in the rectifier dual are also analyzed. In the rectifier dual, it will be shown that conduction losses are slightly less than the amplifier, and unlike the amplifier, there are no overlap losses in the rectifier. 112

129 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier A. Conduction Losses If the switch has finite on resistance, R on, then the ideal voltage waveform is modified by the voltage drop across the device during the on-state. Since the current is a half sine pulse, the corresponding voltage drop is a half sine pulse. The on-state conduction loss is evident in the voltage waveform shown in Figure 4.11(a). Based on this figure, the class-f amplifier voltage and current waveforms including conduction losses are v d,p A (θ) = { Ron I d,max sin(θ) 0 θ < π π θ 2π V d,max (4.3) and i d,p A (θ) = { Id,max sin(θ) 0 θ < π 0 π θ 2π. (4.4) In these equations, V d,max is the maximum voltage across the device and equal to two times that of the DC supply voltage, V DD. The current, I d,max, is the peak amplitude of the current flowing through the device, and θ is a normalized time variable where θ = 2 π f 0 t. Using these equations, it is easy to calculate the conduction loss associated with the half sine voltage drop: P Ron = 1 2π ( ) 2 R on i 2 d,p A 2π (θ) dθ = R Id,max on (4.5) 0 2 The conduction loss is dissipated in the switching device M 1. Now consider the time reversal dual of the amplifier circuit to construct an equivalent rectifier. According to TR theory (see Table 4.1), the rectifier drain voltage waveform v Rec (t) is equal to v P A ( t) and the rectifier drain current waveform i Rec (t) is equal to i P A ( t). The corresponding waveforms are shown in Figure 4.11(b). The current waveform is time reversed and flipped, while the voltage waveform is only time reversed. For the on-state in the rectifier, an exact time reversed voltage waveform would include the positive oriented half sinusoidal pulse shown by the dashed line in Figure 4.11(b). However, positive voltage and negative current during the on-state would imply negative power which is not physically present in the switch. Therefore, in a dissipative switch, the dual of the voltage waveform is modified during the on-state and includes a negative sinusoidal pulse as shown by the solid line in Figure 4.11(b). From this, we conclude that the rectifier dual with losses is not an exact TR dual, and the voltage waveform is modified by considering the dissipation associated with finite switch resistance. The drain voltage and drain current waveforms for the class-f rectifier assuming an onstate switch resistance, R on, are: v d,rec (θ) = { Vd,max 0 θ < π R on I d,max sin(θ) π θ 2π (4.6) and i d,rec (θ) = { 0 0 θ < π I d,max sin(θ) π θ 2π. (4.7) 113

130 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier The corresponding conduction loss in the rectifier is P R on = 1 2π R on i 2 d,rec 2π (θ) dθ = R on 0 ( Id,max 2 ) 2 (4.8) where the prime terms denote measures for the rectifier. The conduction loss in the rectifier is similar to the amplifier except the on-state resistance, R on, corresponds to device operation in quadrant III instead of quadrant I, as in the amplifier. Since on-state resistances in quadrant I and III are similar, conduction losses in the amplifier and rectifier duals are similar and P R on P Ron. B. Capacitive Switching Losses All physical switching devices have output capacitance and this is modeled in the circuit as C out (see Figure 4.10). When the switch M 1 is off, the DC drain inductor L DD charges C out to V d,max, and when the switch is on, the capacitor is discharged through M 1 and the energy stored in the capacitor is dissipated in the device creating a capacitive switching loss. Therefore, the power loss is associated with the falling edge of the drain voltage waveform in Figure 4.11(a). The energy stored in C out is 1 2 C out Vd,max 2. The discharge occurs with a frequency f 0; therefore the total power dissipated is P cap = 1 2 C out V 2 d,max f o. (4.9) We now consider the capacitive switching loss in the rectifier dual. With reference to the drain voltage waveform in the rectifier circuit shown in Figure 4.11(b), it is clear that the capacitor C out is charged to V d,max and discharged to zero similar to the amplifier circuit. However, one constraint on the discharge waveform is that it must occur prior to the switch turning on. During the discharge (falling edge of the voltage waveform), the voltage is positive, and consequently, the discharge current must also be positive to create positive dissipation otherwise negative power would be generated. Therefore, the total power dissipated by discharging the capacitor C out is the same as for the amplifier; hence, P cap = P cap. C. Overlap Power Loss The third loss mechanism that is important to consider in the class-f amplifier and rectifier is overlap loss. In order to analyze overlap loss, the ideal waveforms shown in Figure 4.11 need to be modified to include the rise and fall time of the voltage waveforms. The modified waveforms are shown in Figure For analysis, it is assumed that the rise and fall times change linearly over a time interval τ. At this point, before continuing with the analysis, it is insightful to consider a qualitative comparison of overlap in the amplifier and the rectifier dual. In the amplifier, the drain current and drain voltage are always in quadrant I of the IV plane for the device. This means that overlap loss is primarily determined by the harmonic impedances in the matching network and the gate waveform. The situation for the rectifier dual is different. When the device is off, the current and voltage waveforms are in quadrant I, and when the device is on, the current and voltage are in quadrant III. The implication of the on-state in quadrant III means that the voltage waveform in the off-state has to fully discharge to zero before the current can flow in quadrant III. Another way to describe the current and voltage constraints 114

131 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier i d,p A V d,max I d,max v d,p A and I τ 0 π τ (a) τ 2π θ i d,rec V d,max v d,recand 0 τ τ π 2π θ I d,max (b) Figure 4.12: Drain voltage and drain current waveforms with overlap loss for the class-f amplifier and rectifier duals. is that the dissipation must be positive since negative power cannot be generated in the device. Therefore, the only voltage waveform that can co-exist with the negative on-state drain current is a negative drain voltage waveform. The quadrant III constraints in the rectifier dual lead to the modified voltage and current waveforms shown in Figure The waveforms show that unlike the amplifier, the rectifier dual does not have overlapping current and voltage waveforms during the transition intervals. From this observation we conclude that there is no overlap power loss in the rectifier dual. In the class-f amplifier, the voltage and current waveforms overlap during the transition intervals. Overlap loss during a switch transition is defined as the power loss associated with the cross-over of the current and voltage waveforms as shown in Figure 4.12(a). Using a linear 115

132 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier approximation over a transition time of τ, the overlap loss is P overlap = 1 2π 2π 0 = 2 1 2π v d (θ) i d (θ) dθ ( ) [ Vd,max Iτ θ τ τ τ 0 = V d,max I d,max 6π τ sin(τ). ] (θ τ) dθ (4.10) The overlap power loss is consistent with the condition that the loss is zero when τ is zero. Factors which affect the shape of the current and voltage waveforms will determine the length of the transition interval and consequently the amount of overlap loss dissipated in the amplifier. An important factor which affects waveshapes are the harmonic termination impedances in the output and input matching networks. The transition time can also be affected by the size of the output device capacitance, C out, because the device has a maximum available current to discharge the capacitance. However, it should be noted that the amount of power dissipated to discharge the capacitance is in addition to the overlap loss calculated above because the waveforms in Figure 4.12 do not include the current required to discharge the capacitor. Therefore, the total power loss in a class-f amplifier includes conduction loss, capacitive switching loss and overlap loss, while the total power loss in the rectifier dual only includes conduction and capacitive switching losses. Based on these losses, we expect the rectifier dual to have higher power efficiency compared to the amplifier. D. Power Efficiency Equations to predict the power efficiency of class-f amplifiers and the corresponding rectifier TR dual are derived next using the three loss mechanisms. For the amplifier, the input source power is the DC source power, P DC. The DC power source power must equal the sum of the output power delivered to the load, P out, and the power dissipated in the switching device: P DC = P out + P loss = P out + P Ron + P cap + P overlap. (4.11) For the rectifier, the source power is the input RF power, P in, and the source power must equal the sum of the DC power delivered to the load P DC plus the power dissipated in the rectifying device: P in = P DC + P loss = P DC + P R on + P cap. (4.12) Using these expressions, the drain efficiency of the amplifier is η a = P out P DC = and the RF to DC conversion power efficiency of the rectifier is η r = P DC P in = P out P out + P Ron + P cap + P overlap (4.13) P DC P DC + P R on + P cap. (4.14) Expressions for all the terms in the power efficiency equations have been found except for P out and P DC. These terms are found from the Fourier series expansions of the waveforms in Figure

133 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier The amplitude of the fundamental frequency component of the drain voltage v d,p A (θ) is V f0 = 2 π V d,max R on I d,max 2 (4.15) and the amplitude of the fundamental frequency component of the drain current i d,p A (θ) is I f0 = I d,max. (4.16) 2 The fundamental frequency components are in-phase across the load and the total load power is P out = V fo I fo 2 = V d,max I d,max 2π R on 2 ( Id,max 2 ) 2. (4.17) The equation can also be written in terms of the fundamental frequency load line impedance at the drain. Define R f0 as the ideal load line resistance at the drain assuming a perfect switch (R on = 0). Then, and another expression for P out is R f0 = V f0 I f0 = 4 Ron=0 π P out = 1 2 (R f0 R on ) V d,max I d,max (4.18) ( Id,max 2 ) 2. (4.19) Using expressions for P out, P Ron, P cap, and P overlap, the power efficiency of the class-f amplifier is η a = = P R on P out + P cap P out + P overlap P out 1 + 2R on + π2 Rf0 2 C out f o + τ sin(τ) R f0 R on 4 R f0 R on 3 1 R f0 R f0 R on. (4.20) For the class-f rectifier, we need an expression for P DC to evaluate equation (4.14). Similar to the amplifier, the DC terms of the Fourier series for the rectifier waveforms in Figure 4.11(b) are and V DC = V d,max 2 R on I d,max π (4.21) The DC output power of rectifier is therefore I DC = I d,max. (4.22) π 117

134 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier P DC = V DC I DC = V d,max I d,max R on 2π [ ] ( ) π 2 2 = 8 R f0 R on Id,max. π ( ) 2 Id,max π (4.23) Using this expression for P DC, the power efficiency of the class-f rectifier can be expressed as η r = = P R on P DC P cap P DC 1 2 R on R f0 8 + π2 R π 2 on 4 R 2 f0 C out f o R f0 8 π 2 R on. (4.24) A comparison of the power efficiency equations for the class-f amplifier and rectifier shows that the primary difference between the circuit duals is that the rectifier does not have overlap loss. Therefore, we expect the power efficiency of the rectifier to be higher than the amplifier. E. Expressions for R DC and R DC Analytical expressions for the Thévenin equivalent resistance of the DC power supply in the amplifier, R DC, and the DC load resistance in the rectifier R DC are derived next. Since the power loss is different for the amplifier and rectifier, these two resistances are slightly different. For the class-f amplifier, the DC components of the Fourier series for the class-f waveforms in Figure 4.11(a) are and V DC = V d,max 2 + R on I d,max π (4.25) I DC = I d,max (4.26) π where the sign of I DC is chosen to be consistent with notation in Figure 4.3. The Thévenin resistance of the DC supply is then R DC = V DC = π ( ) Vd,max + R on I DC 2 I d,max (4.27) = π2 8 R f0 + R on. The DC components for the rectifier waveforms were given earlier in equations (4.21) and (4.22). Using these expressions, R DC = V DC I DC = π2 = π 2 V d,max I d,max R on (4.28) 8 R f0 R on. Comparing this equation with the Thévenin equivalent resistance of the amplifier DC supply, we expect that the optimal load resistance for the rectifier to be less than the amplifier. 118

135 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Simulation Results The analytical equations are verified by comparing predicted performance with simulation results for the class-f power amplifier model in Figure For the simulation, a level 2 device model is used without device capacitances. Instead, the total effective output device capacitance is modelled as C out in Figure 4.10, the same capacitance used to analyze capacitive switching losses. The gate drive for the amplifier consists of a 24.5 dbm sinusoidal source at a frequency f o of 985 MHz and a gate bias of -2.6 V. The drain supply voltage, V DD is 27 V and the effective on resistance of the device for these bias conditions is estimated to be 2.2 Ω. The resonant tank circuit is chosen to have a Q of 5 for a load resistance of 50 Ω Efficiency (%) Analytical model for amplifier 60 Analytical model for rectifier 55 Simulation model for amplifier Simulation model for rectifier C out (pf) Figure 4.13: Estimated drain efficiency of class-f PA and rectifier as a function of output capacitance. R on for both the amplifier and rectifier are 2.2 Ω. Under these conditions, time-domain simulations were run for both a class-f amplifier and the rectifier dual as C out is swept over a range of 0 to 1.6 pf. A comparison of the simulated and analytical results is shown in Figure As C out changes, the switching losses in the amplifier change and the drain current/voltage overlap changes. The overlap interval, τ, was obtained from the simulated drain voltage and drain current waveforms and varied from π to 0.15 π radians, as C out varied from 0.2 to 1.6 pf, respectively. Although a simplified device model is used to validate the analytical power efficiency relations, a good reference point for comparison with the experimental results shown in section 4.3 is to consider the case of C out equal to 1 pf. The effective output capacitance of the Cree CGH40010 device used in the experimental work is approximately 1 pf. The corresponding simulated and analytical results are summarized in Table 4.4 and can be compared with the experimental results in Table 4.3. Although not an exact match, the analytical results show that the optimal DC load (R DC ) for the rectifier is expected to be less than the equivalent Thévenin resistance (R DC ) of the DC supply which is consistent with the experimental results. The analytical and simulated results predict a slightly higher power efficiency for the rectifier 119

136 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Table 4.4: Comparison of class-f amplifier and rectifier circuit duals. Parameter Amplifier Rectifier Frequency (f o ) 985 MHz 985 MHz Peak drain voltage (V d,max ) 52 V 52 V Peak drain current (I d,max ) 1.3 A 1.3 A Fundamental frequency load resistance (R f0 ) Output device capacitance (C out ) 1 pf 1 pf Current/voltage overlap (τ) 0.12 π rad 0 Gate bias -2.6 V -2.6 V DC supply/load resistance R DC = 64.6 Ω R DC = 60.3 Ω Input source power P DC = 12 W P in = 12 W Load power P out = 9.5 W P DC = 9.8 W Power efficiency η a = 79% η r = 81.7% Conduction loss (analytic) 0.93 W 0.93 W Capacitive switching loss (analytic) 1.33 W 1.33 W Overlap loss (analytic) 0.49 W - Power Efficiency (analytic) 79.6% 82.1% (3% in this case) which is similar to the experimental results where the rectifier efficiency was 4.8% higher than the amplifier. Also, the analytic, simulation and experimental results for power efficiency are all within 2% of each other which demonstrates good agreement between theory and experiment. One of the advantages of constructing an analytical model is that it provides a way to explore the contribution of different loss mechanisms to the overall power efficiency of the amplifier and rectifier duals. A breakdown of losses are shown in Figures 4.14 and 4.15 for the class-f amplifier and rectifier, respectively. Conduction losses are independent of C out and contribute a fixed loss to both the amplifier and rectifier. On the other hand, capacitive switching losses increase as C out increases for both the amplifier and rectifier. For a capacitance of 1 pf, conduction losses reduce power efficiency by approximately 8%, while switching losses reduce efficiency by about 10%. In the amplifier, there is an additional power loss from the overlap of the drain voltage and current waveforms, and for a capacitance of 1 pf, overlap loss reduces efficiency by approximately 3%. The figures also include the simulation results which closely follow the analytical results confirming the theory which has been developed to predict power efficiency in the class-f amplifier and rectifier duals. 120

137 4.3. High Efficiency GaN HEMT Class-F Synchronous Rectifier Efficiency (%) P Ron P + P Ron cap 75 P Ron + P cap + P overlap Simulation Results C out (pf) Figure 4.14: Predicted losses in a class-f power amplifier as a function of output capacitance Efficiency (%) P Ron 75 P Ron + P cap Simulation Results C out (pf) Figure 4.15: Predicted losses in a class-f rectifier as a function of output capacitance. 121

138 4.4. High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier 4.4 High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier The class-f synchronous rectifier is a voltage switched rectifier. The class-f rectifier can also be implemented in an inverse configuration where the current is switched. In this section, experimental results for a class-f 1 synchronous rectifier are presented for the time reversed dual of the class-f 1 amplifier described in Chapter 3. The class-f 1 uses the same Cree 10 W GaN device used in the class-f rectifier design, and the performance of these two rectifier designs are compared. In Section (3.4) of Chapter (3) a 10 W class-f 1 amplifier was designed and implemented. In this section, the amplifier is reconfigured as a high power GaN RF synchronous class- F 1 rectifier by adding feedback from the output to the input. The rectifier is tested under identical source power condition associated with the dual amplifier. The measurement results for the class-f 1 rectifier are also compared with measurement results for the class-f rectifier design presented in Section (4.3) in terms of performance and dynamic range. The test bench for the class-f 1 rectifier is shown in Figure Similar to the class-f rectifier, a db input coupler (coupler A) and a phase shifter are used to create a gate drive to synchronously switch the device. The other port of coupler A is connected to a power meter to measure the reflected input power. The high power RF input signal (P in ) from the rectifier is generated by a 10 W class-f amplifier, the same amplifier used to implement the class-f synchronous rectifier. A second coupler, coupler B, is inserted between the rectifier and amplifier to measure the available RF input power (P in ) delivered to the rectifier. Rectified Voltage Power Meters Class-F PA B A Couplers RF signal generator Inverse Class-F Rectifier Figure 4.16: Test bed for the class-f 1 rectifier. A class-f amplifier is used as a high power RF input source. As an initial test, the performance of the rectifier is compared with the performance of the amplifier under equivalent test conditions. From Chapter 3, the amplifier had a power efficiency of about 83% for a DC source power of 11.9 W. When the RF input power to the rectifier has the same source power as the amplifier (11.9 W), the rectifier has an RF to DC 122

139 4.4. High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier conversion efficiency of 85%, slightly higher than the amplifier. The results are consistent with observations made for the class-f amplifier which also shows a slightly higher efficiency for the rectifier configuration. The corresponding equivalent Thévenin resistance of the DC supply for the amplifier, R DC, is 48.4 Ω compared to the optimum DC load resistance, R DC, which was found to be 47 Ω. Again, the observation that the DC load resistance for the rectifier is slightly less than the Thévenin resistance of the amplifier is consistent with the class-f experiments. The input reflection coefficient under these test conditions is db and if efficiency is calculated without mismatch loss, the efficiency of the rectifier is 88%. A summary of the test results for the class-f 1 amplifier and rectifier duals are given in Table 4.5. Table 4.5: Comparison of class-f 1 amplifier and rectifier experimental results. Parameter Amplifier Rectifier Frequency 910 MHz 910 MHz Gate bias -2.8 V -2.8 V DC supply/load resistance R DC = 48.4 Ω R DC = 47 Ω Input source power P DC = 11.9 W P in = 11.9 W (40.8 dbm) Load power P out = 9.8 W P DC = W Power efficiency η a = 83% η r = 85% Power efficiency without mismatch loss - η r = 88% Other test results for the rectifier are shown in Figures 4.17 and In Figure 4.17, it is seen that the optimal DC load resistance, R DC, is about 47 Ω, while in Figure 4.18, it is seen that peak efficiency is obtained at a frequency of 910 MHz. As with the class-f rectifier, the bandwidth of the class-f 1 is fundamentally limited by the bandwidth of the multiharmonic matching network in the amplifier. For this design, power efficiency remains above 70% over an 80 MHz frequency range. The most interesting experimental results for the class-f 1 rectifier relate to the relative dynamic range of the rectifier compared to the class-f rectifier. These results are shown in Figure Two observations are made. First, the peak efficiency of the class-f 1 rectifier is higher than the peak efficiency of the class-f rectifier for the same RF input power conditions. This suggests the switching losses are lower in the class-f 1 circuit; this can be explained by the difference between zero voltage switching in class-f 1 as opposed to hard switching in class-f. The second observation is that the dynamic range of the class-f 1 rectifier is much larger than the class-f rectifier. For example, for a minimum power efficiency of 60%, the class- F rectifier has a 6 db dynamic range compared to the class-f 1 rectifier which has a 16 db dynamic range, 10 db higher than class-f. From this comparison, which uses identical devices in two different circuit topologies, it shows that the class-f 1 RF rectifier has significantly better overall performance compared to a class-f RF rectifier. Therefore, it is concluded that a class-f 1 is the preferred circuit topology, a result which does not appear to be clearly 123

140 4.4. High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier Efficiency (%) Output Power (W) R DC (Ω) Figure 4.17: Measured RF to DC conversion efficiency and output DC power versus load resistance for the rectifier. The measurements conditions are for an input RF source power of dbm at a frequency of 910 MHz. Efficiency (%) Output Power (W) Frequency (MHz) Figure 4.18: Measured power efficiency and output power as a function of frequency for the rectifier. The measurements conditions are for an input RF source power of dbm. presented in the existing literature. 124

141 4.4. High Efficiency GaN HEMT Inverse Class-F Synchronous Rectifier Efficiency (%) Class F 1 Rectifier Class F Rectifier Input Power (dbm) Figure 4.19: Power efficiency comparison of a class-f and class-f 1 synchronous rectifier. Experimental results are shown. 125

142 4.5. High Efficiency GaN HEMT Wideband Inverse Class-F Synchronous Rectifier 4.5 High Efficiency GaN HEMT Wideband Inverse Class-F Synchronous Rectifier The class-f and class-f 1 synchronous rectifier designs presented so far are inherently narrowband because of the design of the multiharmonic matching networks in the amplifier. In some applications, such as in energy recycling, the spectrum of the RF input signal can be spread over a large bandwidth and wideband rectifier designs are of interest. In other applications, such as wireless power and RF energy harvesting, wideband rectifiers are also useful. In this section, experimental results for a wideband class-f 1 are presented. The same test bench for the narrowband class-f 1 rectifier shown in Figure 4.16 is used for measuring the performance of the wideband rectifier. Frequency errors introduced by the bandlimited response of the power amplifier are compensated by measuring the RF input power at each frequency using coupler B. The power meter connected to coupler B measures the incident RF input power, while the power meter connected to coupler A measures the reflected input power. The power efficiency of the rectifier as a function of frequency is shown in Figure The results show that power efficiency remains above 60% over a bandwidth of approximately 500 MHz ranging from 600 MHz to 1150 MHz. The peak efficiency is 80.1% at a frequency of 650 MHz. For these measurements, the DC load resistance is 34 Ω and the RF input power is 10 W. Also, in these measurements, the phase shifter has been tuned at each frequency to maximize power efficiency Efficiency (%) Frequency (MHz)) Figure 4.20: Measured drain efficiency as a function of frequency for the wideband class-f 1 rectifier. The rectifier performance as a function of the RF input power is shown in Figure Results are shown for frequencies of 650 MHz, 850 MHz and 1050 MHz and compared with the narrowband rectifier measurements in Figure The wideband rectifier has good efficiency and dynamic range over a wide frequency range, while the narrowband designs have good 126

143 4.5. High Efficiency GaN HEMT Wideband Inverse Class-F Synchronous Rectifier performance at a specific frequency. Therefore, the bandwidth of the rectifier can be designed to match the bandwidth of the RF input spectrum which is to be rectified. Efficiency (%) Wideband: 650 MHz Wideband: 850 MHz Wideband: 1050 MHz Input Power (dbm) Figure 4.21: Measured drain efficiency as a function of input power for the wideband class-f 1 rectifier at frequencies of 650 MHz, 850 MHz and 1050 MHz. Efficiency (%) Class F 1 Rectifier Class F Rectifier Wideband: 650 MHz Wideband: 850 MHz Wideband: 1050 MHz Input Power (dbm) Figure 4.22: Measured drain efficiency as a function of input power for class-f, class-f 1 and wideband class-f 1 synchronous rectifiers. 127

144 4.6 Chapter Summary 4.6. Chapter Summary The design of class-f RF synchronous rectifiers based on the application of time reversal duality has been demonstrated. The implications of loss in the switch-mode amplifier prototype were considered and a set of equivalent conditions were proposed to evaluate the rectifier dual. A direct comparison was then made between the amplifier and rectifier circuits using the class-f amplifiers described in Chapter 3. The experimental results provide new benchmarks for high power class-f synchronous rectifiers including a wideband rectifier design. The RF synchronous rectifiers described in this chapter are used in an energy recycling switch-mode power amplifier described in the next chapter. 128

145 Chapter 5 Switch-mode Power Amplifier with Energy Recycling 5.1 Energy Recycling in Outphasing Power Amplifiers The concept of energy recycling in power amplifiers was first introduced in 1999 for outphasing amplifiers [125]. In outphasing amplifiers, the modulated source signal is mapped to two constant envelope signals, amplified, and after amplification, the signals are combined to reconstruct the original modulated source signal. The primary motivation behind outphasing schemes is to exploit the high efficiency operation of amplifiers that can be obtained when amplifying constant envelope signals. The signal mapping commonly used in outphasing amplifiers is called LINC, linear amplification using nonlinear components. Although the outphasing concept is conceptually attractive as a way to implement high efficiency amplifiers, the practical difficulties of signal combining and reconstruction at the output of the amplifier have been difficult to solve. Two approaches have been used in implementing outphasing amplifiers. The first approach is to reactively combine the output of the two branches. This method is called Chireix outphasing based on the original invention of the outphasing amplifier which was described in 1935 [2]. By reactively combining the amplifiers, there is no isolation between the two amplifier branches and the primary design challenge is to maintain efficient combining over a large dynamic range to accommodate the amplification of signals with high peak to average power ratios. A block diagram of a Chireix outphasing amplifier is shown in Figure 5.1(a). The second approach to outphasing that has been proposed uses an isolating signal combiner [125, 126]. In this method, the interaction between the two amplifier branches is minimized and both amplifier branches can operate with very high efficiency. The disadvantage of isolated combining is that significant power is dissipated in the combiner especially for signals with high PAPR. Therefore, the overall power efficiency of the amplifier is reduced significantly by the isolated combiner. As a way to offset the power loss in an isolated combiner, energy recycling has been proposed. Rather than dumping the RF power in the combiner to an internal load, the power is rectified and returned to the DC supply of the amplifier. A block diagram of this method is shown in Figure 5.1(b). The published work on energy recycling in outphasing amplifiers includes simulation work, measurements of RF to DC rectification efficiency, and some implementations of complete systems [125, 126, 127, 128]. 5.2 Energy Recycling in RF Switch-mode Amplifiers In an analogous way, the two approaches which have been taken in exploring implementations of outphasing amplifiers can also be applied to switch-mode power amplifiers using pulse modulation techniques. The reactive signal reconstruction approach has been the mainstay 129

146 5.2. Energy Recycling in RF Switch-mode Amplifiers c 1 (t) s i (t) Modulated Source Signal (a) Signal Mapping Constant Envelope Signals c 2 (t) V DD Saturated or Switch-mode PA s Non-isolated combining (load modulation) Reactive Signal Combiner s o (t) c 1 (t) s i (t) Modulated Source Signal (b) Signal Mapping Constant Envelope Signals c 2 (t) V DD Saturated or Switch-mode PA s Energy Recycling a(t) Isolated Signal Combiner s o (t) Figure 5.1: Outphasing amplifiers: (a) reactive signal combining and (b) isolated signal combining with energy recycling. of switch-mode amplifier work where a filter (a reactive structure) is used to reconstruct the output signal from the pulse modulated signal while trying to simultaneously create out-ofband impedances that lead to high efficiency switching in the amplifying device. A block diagram for this type of switch-mode power amplifier is shown in Figure 5.2(a). Similar to Chireix outphasing, the reactive approach is in practice difficult to implement and much work remains to be done to implement high efficiency switch-mode amplifiers with reactive signal reconstruction. A second approach to switch-mode power amplifiers is to employ energy recycling in the amplifier by terminating the switch in a broadband load instead of a reactive out-of-band load. The disadvantage of this approach is that power is now dissipated in the out-of-band spectrum. As a way to recapture this power, energy recycling has been proposed as an efficiency enhancement for this type of amplifier [129]. If energy recycling is to be implemented in a switch-mode power amplifier, the signal reconstruction block must include signal separation to isolate the out-of-band power. One way to implement signal separation is to use a complementary diplexer [129, 84]. The diplexer is a three port filter structure where the input port is split into two complementary filter branches. One branch is a bandpass filter that isolates the in-band signal spectrum that is transmitted to the antenna, while the other filter branch isolates the out-of-band signal spectrum which can then be rectified to recapture out-of-band power. The insertion loss of the diplexer is critical to the overall performance of the amplifier and a stripline design reported in [84] has 130

147 5.3. Spectral Shaping to Enhance Energy Recycling Efficiency a loss of approximately 2 db in the in-band path and 0.8 db in the out-of-band path. Another way to implement signal separation is to use a circulator and a bandpass filter. A block diagram of a switch-mode amplifier with this type of signal separation is shown in Figure 5.2(b). The circulator is a non-reciprocal device and out-of-band power reflected by the in-band bandpass filter is reflected back to the circulator and coupled to an isolated port. The isolated port, port C in Figure 5.2(b), can then be connected to a RF rectifier to recover power from the out-of-band spectrum. As with the complementary diplexer, the insertion loss of the isolator is critical to the overall power efficiency of the architecture. Later, in Section (5.5), experimental results are presented for a switch-mode power amplifier using a circulator for signal separation. V DD (a) s i (t) Modulated Source Signal Pulse Encoder Signal Mapping p(t) Switch-mode PA Out-of-band reactive termination In-band power BPF s o (t) Output Signal Reconstruction Filter s i (t) Modulated Source Signal Pulse Encoder Signal Mapping p(t) V DD Switch-mode PA Energy Recycling A a(t) C Circulator Out-of-band power B In-band power BPF s o (t) Output Signal Reconstruction Filter (b) Figure 5.2: Switch-mode power amplifiers (a) with reactive output filter and (b) with energy recycling. 5.3 Spectral Shaping to Enhance Energy Recycling Efficiency If energy recycling is employed in a switch-mode amplifier, it is desirable to shape the outof-band spectrum to improve rectification efficiency. The out-of-band spectrum generated by the encoding process usually has a very large bandwidth which is created by quantizing the source signal. Implementing a high efficiency broadband RF rectifier is more challenging than a narrowband rectifier, therefore spectral shaping to concentrate out-of-band power in a reduced frequency range could improve rectification efficiency of out-of-band energy. 131

148 5.3. Spectral Shaping to Enhance Energy Recycling Efficiency As an example of out-of-band spectral shaping, a noise shaped pulse position modulator with an adaptive sinusoidal dither signal has been implemented. The block diagram of the encoder is shown in Figure 5.3. The encoder consists of a negative feedback loop with a noise shaping filter H(s) and a pulse generator. The pulse generator creates a pulse width equal to the half the period of the carrier frequency of the source signal (T c /2). The zero-crossings of the error signal e(t) determine the delay (position) of the pulse and a rising edge triggers the pulse generator. The pulse generator creates an amplitude quantized output pulse train and the quantization noise is shaped by the noise shaping filter H(s). In this way, the loop is very similar to a sigma-delta modulator except that the timing of pulse edges are asynchronous rather than synchronous as in sigma-delta modulation. s(t) Modulated Source Signal Dither Amplitude Control H(s) Noise Shaping Filter e(t) d(t) f dither T/2 Pulse Generator p(t) Encoded Signal Amplitude 1 p(t) s(t) 0-1 t/t Figure 5.3: Block diagram of a noise shaped PPM encoder with dither (top) and example input and output waveforms (bottom). The noise shaping loop includes a sinusoidal dither signal d(t) which is added to the error signal e(t). The amplitude of the dither signal is controlled by the source signal envelope. When the source envelope has a small amplitude, the out-of-band quantization noise has much higher power than the signal and the dither amplitude is large. Conversely, when the source signal envelope is at peak envelope power, then the dither amplitude reduces to zero because most of the power in the output pulse train is signal power. The exact amplitude mapping function used to control the dither amplitude depends on a compromise between signal to noise ratio (SNR), frequency of the dither signal, and loop stability. Examples of the output spectrums from the encoder with and without spectral shaping are shown in Figure

149 5.3. Spectral Shaping to Enhance Energy Recycling Efficiency Relative Power Spectral Density (db) without spectral shaping signal encoded in noise well Frequency (MHz) Relative Power Spectral Density (db) with spectral shaping adaptive dither to improve out of band rectification efficiency Frequency (MHz) Figure 5.4: Power spectrum of a noise shaped PPM signal without out-of-band spectral shaping (top) and with spectral shaping (bottom). 133

150 5.4. Analysis of Power Efficiency Enhancement using Energy Recycling 5.4 Analysis of Power Efficiency Enhancement using Energy Recycling An RF power amplifier with energy recycling is shown in Figure 5.5. The block diagram is sufficiently general to capture the primary concepts of recycling in both outphasing and switch-mode power amplifiers. A modulated RF carrier s(t) is mapped to a set of signals c k (t) with reduced amplitude variation; for example, constant envelope signals. The signal mapping generates N input signals for the high efficiency amplifier block. For the cases considered here, a switch-mode amplifier has N = 1 and LINC has N = 2. P DC η er P er Energy Recycling P add G 31 s(t) Signal Mapping P in c k (t) N P DC η d0 High Efficiency Amplifier(s) N P sig + P add G G 21 2 Signal Combiner / Separator P sig G 21 R L Figure 5.5: Block diagram of a power amplifier with energy recycling. The outputs of the amplifier are combined in a signal reconstruction block. The signal reconstruction block also has signal separation and spectral power added by the signal mapping function can be isolated. An example of a signal combiner/separator in an outphasing amplifier design is a 180 degree hybrid which provides sum and difference output signals. For switch-mode amplifiers, the signal reconstruction and separation can be implemented by either a complementary diplexer or the combination of a circulator and bandpass filter. The power loss associated with signal reconstruction is modeled by the gain term G 21 from port 1 to port 2, and power loss associated with signal separation to recover dissipated power is modelled by the gain term G 31 from port 1 to port 3. The output path gains are lossy and consequently the path gains are less than unity: 0 < G 1. An expression for the overall drain efficiency of the amplifier with energy recycling is derived next. The native drain efficiency of the power amplifier is defined as the power efficiency of the amplifier block when amplifying the signals c k (t) under a load condition equivalent to the input impedance of the signal combining network at port 1. The output power spectrum from the amplifier can be partitioned into the desired signal power (P sig ) and power added by the signal mapping function (P add ). Therefore, the native drain efficiency of the amplifier is η d0 = P sig + P add P DC (5.1) where P DC is the DC input power to the amplifier. After signal reconstruction, the total output power delivered to the load at port 2 is equal to P sig G 21. The signal combiner also outputs residual power which is created by the signal reconstruction process. The total residual power available at port 3 is P add G 31. The residual 134

151 5.4. Analysis of Power Efficiency Enhancement using Energy Recycling power is rectified to generate an auxiliary DC supply that is summed with the main supply. The return of output RF power back to DC supply power implements an energy recycling loop. The DC power provided to the amplifier consists of an external source of power P DC and recycled power P er. The available recycling power depends on both the efficiency of the energy recycling block (η er ) as well as the loss G 31 in the signal reconstruction block. Therefore, P er = P add G 31 η er. (5.2) The overall power efficiency of the amplifier can then be written as η d = P sig G 21 P DC = P sig G 21 P DC P er. (5.3) The equation for overall power efficiency can be expanded to write it in terms of the native power efficiency η d0. Using (5.2) in (5.3), η d = P sig G 21 P DC P add G 31 η er P add + P sig P add + P sig = P add + P sig P sig/(p add + P sig ) G 21 P DC 1 (P add /P DC ) G 31 η er P sig /(P add + P sig ) G 21 = η d0 1 [(P sig + P add )/P DC ] [P add /(P sig + P add )] G 31 η er P sig /(P add + P sig ) G 21 η d0 =. 1 [P add /(P sig + P add )] G 31 η er η d0 (5.4) A more concise expression for the overall power efficiency of the energy recycling amplifier can be obtained by adopting the concept of coding efficiency. Coding efficiency is commonly used as metric to evaluate how efficient the pulse encoder is in a switch-mode power amplifier. However, coding efficiency can be applied more broadly to any class of signals that adds power to the original source signal spectrum. The definition of coding efficiency is CE = in-band signal power total power = P sig P sig + P add (5.5) and it gives a measure of how much signal power is added by the signal mapping block to create a set of output signals. For LINC, the RF modulated source signal, s(t), is mapped to two constant envelope signals, c 1 (t) and c 2 (t), and the signal mapping adds power to the source signal. Therefore, coding efficiency can be applied to LINC in the same way as it is used as a metric to quantify the efficiency of pulse encoders in switch-mode amplifiers. Using the definition of coding efficiency and equation (5.5), we also get the relation P sig = (P sig + P add )CE. Therefore the overall power efficiency of an amplifier with energy recycling is η d = η d0 G 21 CE 1 η d0 η er G 31 (1 CE). (5.6) Equation (5.6) is very useful for exploring the theoretical bounds of power efficiency for different power amplifier scenarios. A number of examples are shown in Figure 5.6. As a first example, consider the upper bound for a power amplifier with a native power efficiency, 135

152 5.5. Experimental Implementation of a Switch-mode Power Amplifier with Energy Recycling η d0, of 80% and with perfect energy recovery and lossless signal separation. 3 Perfect energy recovery is defined as an RF to DC rectification efficiency, η er, of 100%, and lossless signal separation means G 21 and G 31 are both 0 db. For this case, if the coding efficiency of the constant envelope signal were 25%, then the corresponding power efficiency of the amplifier is 28% without energy recycling and 50% with energy recycling. Under these conditions, energy recycling boosts power efficiency by 78% compared to an amplifier without energy recycling: (50% - 28%)/28% x 100% = 78%. For this scenario, energy recycling clearly provides a significant boost in the power efficiency of the amplifier. For a second example, consider the same constant envelope power amplifier efficiency of 80% with -1 db loss for the output path, G 21, and -0.5 db for the G 31. The losses are practical values that could be obtained with an optimized output network consisting of either a circulator and bandpass filter or a complementary diplexer. The third example shown in the figure corresponds to measured values that model the experimental test-bed described later in the following section. A comparison of these three examples shows that it is significant to minimize losses in the signal separation block to maximize the efficiency enhancement that is obtained from energy recycling. 5.5 Experimental Implementation of a Switch-mode Power Amplifier with Energy Recycling An experimental test-bed was implemented to evaluate energy recycling in a switch-mode power amplifier. A photo of the test-bed is shown in Figure 5.7. The system consists of an arbitrary waveform generator to generate pulse encoded input signals, a class-f 10 W amplifier, a circulator and bandpass filter for a signal reconstruction and signal separation, and a wideband class-f 1 rectifier. The class-f 10 W amplifier design and the wideband class-f 1 rectifier design were described earlier in Chapters 3 and 4, respectively. All the pulse train waveforms were generated in Matlab using the noise shaped PPM pulse encoder with out-of-band spectral shaping described earlier in section 5.3. The carrier frequency of the source signal is centered at 930 MHz and the sinusoidal dither signal has a frequency of 986 MHz. The clock rate of the arbitrary generator is Gs/sec. A two stage circulator and a bandpass filter are used for signal separation and signal reconstruction. The bandpass filter is a cavity filter with a center frequency of 930 MHz and bandwidth of 10 MHz. The path gain from the input port (port 1) to the load port (port 2) is db (G 21 ) and the path gain from the input port (port 1) to the recycling power port (port 3) is -2.1 db (G 31 ). The native power efficiencies of the amplifier and rectifier were first measured independently of other components. For the pulse encoded waveforms the class-f amplifier power efficiency (η d0 ) is approximately 50%. The power efficiency does vary slightly depending on the amplitude of the source signal and the amplitude of the dither signal. For the rectifier, the peak RF to DC conversion efficiency (η r ) is approximately 80% and the efficiency reduces as the input power is backed off. Since the amplitude of the dither signal in the pulse train spectrum is inversely proportional to the amplitude of the source signal, we expect the rectifier will have high power efficiency for low input amplitude source signals and reduced efficiency for high amplitude input source signals. The dependence of rectification efficiency on power is an important observation and an optimized energy recycling system would adjust 3 A saturated or switch-mode power amplifier with a drain efficiency of 80% is considered to be a very good amplifier and in alignment with the best performance that is obtained from experimental amplifiers. 136

153 5.5. Experimental Implementation of a Switch-mode Power Amplifier with Energy Recycling Overall Efficiency (%) Coding Efficiency (%) η d0 = 80%; η ER = 100%; G 21 = 0dB; G 31 = 0dB η d0 = 80%; η ER = 0%; G 21 = 0dB; G 31 = 0dB η d0 = 80%; η ER = 80%; G 21 = 1dB; G 31 = 0.5dB η d0 = 80%; η ER = 0%; G 21 = 1dB; G 31 = 0.5dB η d0 = 50%; η ER = 80%; G 21 = 1.12dB; G 31 = 2.1dB η d0 = 50%; η ER = 0%; G 21 = 1.12dB; G 31 = 2.1dB Figure 5.6: Examples of amplifier power efficiency with energy recycling. peak efficiency to coincide with the average amplitude level of the source signal. However, in this design, peak rectification efficiency is obtained at the lowest source amplitude level. The test results for the energy recycling switch-mode power amplifier are shown in Figures 5.8 and 5.9. In Figure 5.8, the in-band power measured at the output of the filter is shown as a function of the modulator drive level. The modulator drive level is expressed in terms of coding efficiency which gives the ratio of the signal power relative to the total power in the pulse train spectrum (see equation (5.5)). Therefore, low coding efficiency corresponds to a low amplitude source signal and conversely high coding efficiency corresponds to a high amplitude source signal. Since the encoded pulse train has constant amplitude, the total power in the pulse train is constant and the therefore the sum of signal power (P sig ) and added power P add is equal to a constant. The figure shows the relative distribution of power as the coding efficiency of the signal changes. From this graph, we expect energy recycling to be most effective for low amplitude source signals. In Figure 5.9, the power efficiency of the in-band signal component relative to the total DC power supplied to the amplifier is shown as function of coding efficiency. Since the encoded signal is a constant power signal, the power efficiency decreases as the amplitude of 137

154 5.5. Experimental Implementation of a Switch-mode Power Amplifier with Energy Recycling Attenuator Driver Powermeter Voltmeter Phase shifter Class-F PA Coupler Rectifier Circulator BPF RF arbitrary signal generator Figure 5.7: Test bed with a class F amplifier and a class-f 1 rectifier to recover out-of-band energy. The system implements the block diagram shown in Figure 5.2(b). 7 6 In band Power Recovered Power 5 Power (W) Coding Efficiency (%) Figure 5.8: Measured in-band and recovered power as a function of the coding efficiency for encoder of the noise shaped PPM modulator. the source signal decreases. A second trace on the plot shows the in-band power efficiency of the amplifier with the energy recovery system. At high input levels to the modulator, the energy recovery system does not offer any benefit because the out-of-band dither power is low. However, as the RF signal level drops, the energy recovery system can significantly 138