Chireix s / LINC Power Amplifier for Base Station Applications Using GaN Devices with Load Compensation

Transcription

1 Chireix s / INC Power Amplifier for Base Station Applications Using GaN Devices with oad Compensation by Jijun Bi TU-Delft Mentors: Dr. ing..c.n. de Vreede Jawad Qureshi, Marco Pelk NXP Mentors: John Gajadharsing Mark van der Heijden Delft University of Technology, September 008. A thesis submitted to the Electrical Engineering, Mathematics and Computer Science Department of Delft University of Technology in partial fulfillment of the requirements for the degree of Master of Science.

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3 Approval Name: Degree: Jijun Bi Master of Science Title of Thesis: Chireix s / INC Power Amplifier for Base Station Applications Using GaN Devices with oad Compensation Committee in Charge of Approval: Chair: Department of Electrical Engineering Committee member: Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering

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5 Abstract New generations wireless communication systems require linear efficient RF power amplifiers for higher data transmission rates. However, conventional RF power amplifiers are normally designed for peak efficiency under maximum output power condition. Consequently, when the power is backed-off from its maximum point, the amplifier efficiency drops sharply. As a result, the mean amplifier efficiency is much lower than the efficiency at peak power level. The Chireix outphasing power amplifier is one of the most promising techniques that can simultaneously provide high efficiency and high linearity. Such approach was the origin of the term INC (Inear amplification using Nonlinear Components), a technique that allows the power amplifiers to continuously operate at their peak power efficiency while providing an almost undistorted output signal. In this project, a Chireix outphasing amplifier for.14 GHz with load compensation has been fabricated using GaN HEMTs delivered by CREE. A considerable efficiency improvement has been achieved. The simulation result shows that the drain efficiency of 74% is obtained at 49 dbm peak output power, and the efficiency is kept above 55% over 10 db power back-off range. The drain efficiency of 70% is measured at 48.5 dbm output power. To meet an increasing demand for wireless communication terminals to handle multi-band multi-mode operation, multi-band multi-mode power amplifiers are urgently needed. An investigation into how to implement multi-band Chireix s outphasing amplifiers has been carried out. Two proposals for implementing potential dual-band Chireix s amplifiers have been presented. In addition, a comparison of the efficiency under the condition of static load modulation has been made between GaN HEMT devices and DMOS devices. The result of the comparison is that GaN HEMT devices conspicuously outperform DMOS devices in terms of drain efficiency under static load modulation.

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7 Acknowledgements First, I would like to express my sincere gratitude to my mentor Dr. eo de Vreede for granting me such a good opportunity to conduct this interesting research and for his guidance and encouragement during the project. Second, I would like to thank the members of HiTeC Group for their assistance, cooperation, and encouragement. Special thanks are given to Mr. Jawad Qureshi for his continuous help throughout the whole project, to Mr. Marco Pelk for providing the input stabilization network, valuable discussions, and timely help in the final phase of my project, and to Mr. W. C. Edmund Neo for helping me in simulations. Next, I would also like to thank NXP Semiconductors for offering me a traineeship opportunity during 007 and 008. Finally, My family and my friends have always given me strong support and encouragement in my studies and in other aspects of my life in the Netherlands. Without them, this work would never have been accomplished.

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9 Contents Chapter 1 Introduction Project motives and objectives Thesis structure... Chapter Chireix s outphasing amplifier Outphasing operation A mathematical description of Chireix's outphasing operation Theoretical efficiency of Chireix's outphasing amplifier...8. A practical common-mode topology of Chireix's outphasing system A summary of Chireix s outphasing operation... Chapter 3 Design of a Chireix's/INC amplifier Design strategies and procedure Amplifier and power combiner choices Power amplifier cell design Device characterization and bias points Device stabilization Partially compensating the parasitic effects of the package oad-pull determining the optimum load impedance Functionality verification with ideal components Implementation with realistic components Chireix's outphasing system design Power combiner design Chireix s outphasing system without load compensation oad adjustment for Chireix s/inc operation oad compensation Ideal implementation of Chireix s outphasing system Practical implementation of Chireix s outphasing system ayout implementation and measured results Summary...68 Chapter 4 Potential solutions to multi-band Chireix's/INC amplifier A review of several current multi-band PA implementation Proposals for implementing multi-band Chireix s amplifiers Dual-band Chireix s amplifier based on resonators Dual-band Chireix s amplifier based on transmission lines Summary...76

10 Chapter 5 Efficiency comparison under static load modulation between GaN HEMT and DMOS Research motivation Device models Simulation procedures of static load modulation GaN HEMT 45-watt model Harmonic termination Optimum load Static load modulation DMOS 45-watt model Harmonic termination Optimum load Static load modulation Comparison and conclusion...91 Chapter 6 Conclusions and suggestions Conclusions Suggestions...94 References...95

11 Chapter 1. Introduction Chapter 1 Introduction 1.1 Project motives and objectives The boom of the wireless market, combined with the intense competition of the past two decades, has stimulated unprecedented interest in the performance of low-cost and physically compact radio frequency (RF) power amplifiers. Interest in performance was induced by the significant impacts that power amplifiers have on wireless communication systems. As far as base station applications are concerned, power amplifiers affect them primarily in two aspects. Firstly, as the final stage in the transmitter chain, the power amplifier (PA) has a significant impact on the total power consumption of the base station. Here low power consumption will result in low operation costs, something that is a substantial market advantage. Consequently, to achieve low operation costs the PA should have high efficiency, not only for the peak-power levels but also for signal with varying envelopes yielding high peak-to-average power ratios. Secondly, PA nonlinearity can cause spectral spreading of the amplified signal, resulting in channel-to-channel interference. To avoid this, the PA must be as linearly as possible. Figure 1.1: Efficiency and linearity trade-off in RF power amplifiers Therefore, two specifications efficiency and linearity need to be dealt with. Unfortunately, instead of being independent, PA efficiency and linearity are usually 1

12 Chapter 1. Introduction conflicting requirements. For instance, for those systems that employ envelope-varying modulation schemes, a direct trade-off exists between the linearity and efficiency of the power amplifier. E.g. conventional PAs that operate in class-a, class-ab, and class-b can be linear, but are typically inefficient, not only in terms of peak efficiency, but even more in power back-off when amplifying envelope-varying signals. Switch mode PAs like class-d, class-e, and class-f can have high efficiency, but they are usually nonlinear in nature yielding intermodulation distortion (IMD) which results in spectral spreading. Consequently, the main question is how to achieve high efficient amplification with sufficient linearity for envelope varying signals. To tackle this problem up to date (Figure 1.1), several methods have been proposed. An interesting but somewhat neglected concept to solve for the efficiency-linearity trade-off is Chireix's outphasing amplifier, also referred to as "linear amplification using nonlinear components" (INC). Within NXP progress has already been made with this amplifier concept yielding encouraging results and some patent applications. Meanwhile, a prior M.Sc. study by R. iu at the TUDelft for application of this amplifier concept in handset PAs has yielded new insights and concepts to further improve the original Chireix's concept. One objective of this project is to combine these existing insights to a new high power amplifier implementation facilitating high efficiency and linearity for base station applications. For this purpose use will be made from state-of-the-art Gallium Nitride (GaN) devices from CREE. In addition, there is an increasing demand for wireless communication terminals to handle multi-band multi-mode operation with a single Power Amplifier. Consequently, to address this need multi-band PAs are needed that do not require extensive filter banks. So the second objective of the project is to review potential implementations of multi-band PAs and to evaluate the feasibility of realizing a multi-band Chireix's outphasing amplifier. As a supplementary topic, the drain efficiencies in class-b mode operation under static load modulation have been investigated for GaN HEMT devices and DMOS devices. Simulation results show that under static load modulation GaN HEMT devices demonstrate much better drain efficiencies than do DMOS devices. 1. Thesis structure Chapter describes the concept of Chireix's outphasing amplifier. First, based on a differential topology, the principle of Chireix s outphasing operation is introduced. Then, for two types of power combiner topologies, the varying load seen by the PA and the ideal drain efficiency are derived. These theoretical results convincingly prove the advantage of

13 Chapter 1. Introduction Chireix s outphasing amplifier as an efficiency enhancement technique. Chapter 3 discusses the design procedure of a Chireix's outphasing amplifier in detail. Section 3.1 and 3. outline the methodology and strategies that have been adopted in the design of Chireix's outphasing amplifier. Section 3.3 gives details related to the design of the PA cell, including device evaluation, choice of operation class, load-pull simulation, and the realization of the input and output matching network. Section 3.4 describes the design of the overall Chireix's outphasing system. Close attention is paid to the compensation of the parasitic reactance in device package, the realization of the power combiner, and the load adjustment for outphasing operation. A detailed design process has been described by presenting circuit schematic and simulation results in every step from concept verification with ideal devices and components to the real implementation with actual active devices and practical components. Section 4.5 shows the actual layout implementation of the Chireix amplifier and its measured results. A summary of Chapter 3 is given in the last section. Chapter 4 presents the research on potential multi-band amplifiers. This research comprises two parts. The first part is a review of current multi-band PA implementations. In the second part several suggestions on how to implement a multi-band Chireix's outphasing amplifier are proposed. Chapter 5 describes the comparison of the drain efficiency under static load modulation between GaN HEMT devices and DMOS devices. Chapter 6 concludes the thesis by giving some suggestions on the future work of Chireix s outphasing amplifier. 3

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15 Chapter. Chireix s outphasing amplifier Chapter Chireix s outphasing amplifier.1 Outphasing operation Outphasing operation is a technique with a long history that was first proposed by Henri Chireix in 1935 to improve average efficiency and linearity of AM broadcast transmitters. This idea has been revived and applied to various wireless applications since it was reinvented by D. C. Cox, who introduced the term INC (Inear amplification using Nonlinear Components) in INC was invented to realize a linear amplifier where the intermediate stages of RF power amplification could employ highly nonlinear devices. Figure.1: Simplified block diagram of an outphasing system Figure.1 illustrates a simplified diagram of an outphasing system. The concept itself is very simple. An amplitude modulated (AM) signal is first separated by the signal component separator (SCS) into two phase modulated (PM) signals that have equal constant envelopes and opposite modulated phase variations. These two constant-envelope PM signals are then amplified separately by two independent identical PAs. Finally, these two amplified signals are combined at the output of the PAs to produce an amplified replica of the original AM signal. The key element in a Chireix s outphasing system is the SCS, which converts the input AM signal into two outphased component PM signals that have constant envelopes. It is exactly such modulation conversion that brings the possibility of highly efficient and highly 5

16 Chapter. Chireix s outphasing amplifier linear amplification. Because the envelopes of the signals to be amplified are now fixed and the magnitude of the envelopes contains no information (all the amplitude information of the original AM signal is contained in the phase of the component PM signals), we can employ PA cells in the branches which have an extremely high peak efficiency. Consequently, the Chireix s outphasing amplifier system can act as an interesting efficiency enhancement technique. Meanwhile, also thanks to the fixed envelope in the branch amplifiers, the nonlinearity of the input-output power characteristic as present in most high-efficiency PA implementation will have very little influence on the overall input-output transfer function of the Chireix s outphasing system. As a result, the total system can be highly linear over a wide range of signal levels, provided the SCS and the power combiner do not introduce nonlinear signal distortion. In practice, for the branch amplifiers, the most high-efficiency PAs or even constant-amplitude phase-locked oscillators can be used to realize linear amplification, which explains the acronym INC that is typically used for these types of amplifiers. In summary, theoretically Chireix s outphasing operation provides a clear, simple, and promising solution for simultaneously achieving high efficiency and high linearity in a power amplifier system. However, as explained later, practical implementation aspects of a Chireix s outphasing amplifier can be complicated..1.1 A mathematical description of Chireix's outphasing operation The whole process of Chireix s outphasing operation consists of three steps signal component separation, signal amplification, and signal combination, which are realized respectively by the SCS, the PAs, and the power combiner. The topology of the power combiner has an influence on the signal component separation that should be implemented. The principle of Chireix s outphasing operation will be described for the case of a nonisolating power combiner with a differential topology, as shown in Figure.. Figure.: A Chireix outphasing system with a differential-topology power combiner 6

17 Chapter. Chireix s outphasing amplifier The input AM signal, which may also include phase modulation, is denoted by S () t = Et () cos[ ωt + ϕ()]; t 0 Et () E (Equation.1) in where Et () is the real envelope and ϕ() t represents the original phase modulation in the input AM signal. This input signal is separated by the SCS into two constant-envelope PM signals having equal envelopes and opposite modulated phase variations m Em S1() t = sin[ ωt + ϕ() t + φ()] t Em S() t = sin[ ωt + ϕ() t φ()] t (Equation.) SCS is where Em is the maximum value of Et () and the outphasing angle φ () t produced by the Et () π φ( t) = arcsin[ ]; 0 φ( t) (Equation.3) E m S () t and 1 S () t are related to Sin() t as follows: Em S1() t S() t = {sin[ ωt+ ϕ() t + φ()] t sin[ ωt+ ϕ() t φ()]} t = Em sin[ φ( t)] cos[ ωt + ϕ( t)] = Et () cos[ ωt+ ϕ()] t = Sin() t (Equation.4) S () t S () in t S () t φ() t φ () t S () t 1 j () t e ϕ Figure.3: A complex phasor representation of Chireix s outphasing operation Figure.3 illustrates this relationship expressed by the corresponding complex phasors. 7

18 Chapter. Chireix s outphasing amplifier The real signals are related to the corresponding complex phasors as follows: Sin( t) = Re{ Sin( t) exp( jωt)} where Sin( t) = E( t) exp[ jϕ( t)] Em π S1( t) = Re{ S1( t) exp( jωt)} where S1( t) = exp{ j[ ϕ( t) + φ( t)]} Em π S( t) = Re{ S( t) exp( jωt)} where S( t) = exp{ j[ ϕ( t) φ( t)]} (Equation.5) These two constant-envelope PM signals are separately amplified by two independent identical PAs. The output signals from the PAs are Em S`( 1 t) = G S1( t) = G sin[ ωt + ϕ( t) + φ( t)] Em S`() t = G S() t = G sin[ ωt + ϕ() t φ()] t (Equation.6) where G is the identical amplifier gain. Because of the differential topology of the power combiner, the final output at the load resistor R is Sout () t = S`() 1 t S`() t = G [ S1() t S()] t = G Sin() t = G E() t cos[ ωt+ ϕ()] t (Equation.7) This final differential signal at the load resistor shows full recovery of the original AM signal. Meanwhile, the original phase modulation ϕ(t) in the input AM signal passes through the system unmodified..1. Theoretical efficiency of Chireix's outphasing amplifier As mentioned before, in Chireix s outphasing system, nonlinear PAs can be employed to realize linear amplification. These amplifiers can be so heavily saturated that the device will have rail-to-rail voltage swing. Under these conditions, the device can be approximated as a fixed RF voltage source. In the case of shorted harmonics (class-b), the amplitude of the RF voltage source can be approximated by the dc supply voltage. In this section, the efficiency of Chireix s outphasing amplifier will be derived based on the following assumptions: Heavily saturated class-b amplifiers are used for signal amplification so that the PAs are approximated as ideal voltage sources that have an amplitude equal to dc supply voltage. 8

19 Chapter. Chireix s outphasing amplifier Harmonic shorts at the output ensure that the output voltage is a pure fundamental tone having a sinusoidal form. A differential-topology lossless power combiner is used for signal combination Figure.4: Simplified output schematic of Chireix s outphasing system Based on these assumptions, the output of the Chireix s outphasing system can be simplified into a diagram shown in Figure.4. The voltages of those two voltage sources can be expressed in the following phasor notation: + jφ V = V e = V (cosφ+ jsin φ) 1 o o jφ V = V e = V (cosφ jsin φ) o o π with Vo = Vdc and 0 φ (Equation.8) The voltage across the RF load resistor R is V = V V = V j sinφ (Equation.9) 1 o Recall (Equation.3 and (Equation.5, in the form of voltage signal they become Et () φ() t = arcsin[ ] E m V (t) = Vt ()exp{ jϕ ()}; t 0 Vt () V in Vm π V(t) 1 = Av exp{ j[ ϕ( t) + φ( t)]} = Vo exp[ + jφ( t)] Vm π V(t) = Av exp{ j[ ϕ( t) φ( t)]} = Vo exp[ jφ( t)] where A is the voltage gain of the PAs and V o v Vm π = Av exp{[ j ϕ() t ]} Then the differential output voltage is given by m (Equation.10) 9

20 Chapter. Chireix s outphasing amplifier V (t) = V j sinφ Vm π π V() t = Av exp{ j[ ϕ( t) ]} exp( j ) V = A V( t)exp[ jϕ( t)] v = A V (t) v o in which is exactly an amplified recovery of the original input voltage. m (Equation.11) The impedances seen by each of the voltage sources are Z Z 1 V1 cosφ+ jsinφ R = = R = (1 jcot φ) V1 V jsinφ R V cosφ jsinφ R * = = R = (1+ jcot φ) = Z V1 V ( ) jsinφ R (Equation.1) 1 The corresponding admittances are 1 sin sin φ φ Y1 = = + j = Go + jbo Z R R Y 1 sin sin * = = j = Go jbo = Y1 Z R R where 1 G o φ sin φ sinφ = and Bo = R R φ (Equation.13) The RF power delivered to the load is 1 * 1 * 1 PRF1 = Re{( VY 1 1) V1} = V1 Re{ Y1} = Vdc Go P V G P P = P + P = V G * * RF = Re{( VY ) V} = V Re{ Y} = dc o = RF1 RF RF1 RF dc o (Equation.14) For a class-b amplifier, the dc current I dc is related to the fundamental current component I 1 as follows: 10

21 Chapter. Chireix s outphasing amplifier Idc = I1 = Ifund = VY 1 1 = Vdc Y1 = Vdc Y Vdc Y π π π π π π (Equation.15) The total DC power dissipated by the PAs is 4 Pdc = IdcVdc = Vdc Y (Equation.16) π Consequently, the theoretical efficiency of the Chireix s outphasing amplifier is given by PRF π Go π Go η= = = = ηb cos( Y) P 4 Y 4 G + B where dc o o η B π = is the theoretical efficiency of a class B amplifier 4 (Equation.17) Therefore, the theoretical efficiency of the Chireix s outphasing amplifier is the efficiency of a class-b amplifier multiplied by the cosine of the phase angle of the load (either admittance or impedance) presented to either voltage source. This conclusion is a direct result from the symmetrical topology of the Chireix s outphasing system that consists of two PA branches, and it does not depend on the topology of the power combiner as long as it is lossless. For the differential-topology power combiner, the final efficiency expressed in the form of the outphasing angle is Because η= η cos( Y) = η sinφ (Equation.18) B B sin φ Go R cos( Y) = = = sinφ G o + Bo sin φ sinφ + R R (Equation.19) 11

22 Chapter. Chireix s outphasing amplifier (a) (b) Figure.5: Theoretical efficiency of the Chireix s outphasing amplifier (without load compensation); (a) Efficiency versus outphasing angle (b) Efficiency versus normalized output power Consequently, the efficiency significantly drops as the outphasing angle φ decreases, which is shown in Figure.5. The degradation of the efficiency is caused by the increase impact of the susceptance component on the admittance presented to each PA. To address this problem, Chireix proposed the load compensation method; the basic idea of this method is to compensate the susceptance component by adding a proper shunt reactance. where sin φ sinφ Go = and Bo = R R Figure.6: oad admittances presented to each outphasing PA; (a) upper branch (b) lower branch (a) (b) Figure.7: Normalized conductance and susceptance seen by the PA versus outphasing angle (a) normalized conductance (b) normalized susceptance According to (Equation.13, the admittance presented to each PA consists of a conductive part G o and a susceptive part B o or -B o, as illustrated in Figure.6. As mentioned 1

23 Chapter. Chireix s outphasing amplifier before, the culprit for the degradation of the efficiency is the susceptance, which is a function of the outphasing angle. If we add a shunt susceptance with the opposite sign to the existent susceptance at a particular outphasing angle, we can cancel the susceptance and therefore obtain a maximum efficiency η Β at that outphasing angle. Additionally, as a function of the outphasing angle, the susceptance B o is symmetrical around φ = 45 ο (Figure.7). Due to this property, if we compensate the susceptance at a particular outphasing angle φ comp (0<φ comp <45 ο ), which will be referred to as the compensation angle, the susceptance at the outphasing angle (90 o -φ comp ) will be also automatically compensated. This load compensation process is shown in Figure.8. Figure.8: oad compensation; (a) upper branch (b) lower branch After the compensating components being added, the new load admittances presented to each PA become sin φ sin φ sin φ Y 1 = Y1 + j( Bcomp) = Go + j( Bo Bcomp) = + j R R sin φ sin φ sin φcomp Y = Y + j( + Bcomp) = Go j( Bo Bcomp) = j = ( Y 1) R R where B comp sin φ = R comp comp (Equation.0) Similar to (Equation.17, the efficiency of the Chireix s outphasing amplifier with load compensation is given by * 13

24 Chapter. Chireix s outphasing amplifier η = η cos( Y ) = η = η B B B sin G + ( B B ) o o comp ( sin φ) + ( sin φ sin φcomp) φ G o (Equation.1) The output RF power remains the same as that in (Equation.14 because the added compensating reactance or susceptance is lossless. Figure.9: Normalized efficiency of the Chireix s outphasing system at three compensation angles (φ comp =10 o, 0 o, and 45 o ) Figure.10: Normalized efficiency versus normalized output power at three compensation angles (φ comp =10 o, 0 o, and 45 o ) 14

25 Chapter. Chireix s outphasing amplifier Apparently, a zero compensation angle (φ comp =0 o ) corresponds to the case without load compensation (η =η B* sinφ). The normalized theoretical efficiencies for three different compensation angles (φ comp =10 o, 0 o, and 45 o ) of the Chireix s outphasing amplifier are plotted in Figure.9. As can be seen from these curves, the choice of compensation angle significantly influences the overall efficiency of the Chireix s outphasing amplifier over the whole outphasing angle range. If the compensation angle is too small, due to the long distance between the two efficiency peaks, the overall efficiency in the higher range of the outphasing angle is very high but the overall efficiency at the lower range of the outphasing angle will be rather low despite one of the efficiency peaks achieved at the compensation angle. If the compensation angle is too large, the efficiency peaks move very close to each other, and except the middle range of the outphasing angle both the efficiency for the lower range and for the higher range of the outphasing angle drop quickly from the peak value, especially in the lower range. Only when we choose a proper compensation angle can we achieve the optimum overall efficiency of the Chireix s outphasing amplifier. Nevertheless, theoretically, a combination of Chireix s outphasing operation and load compensation makes it possible to realize very high efficiency over a wide range of the outphasing angle, which corresponds to a wide range of output power back-off (Figure.10). This is exactly the main advantage of the Chireix s outphasing operation as an efficiency enhancement technique.. A practical common-mode topology of Chireix's outphasing system The Chireix s outphasing amplifier with a differential-topology power combiner can achieve very high overall efficiency by using proper load compensation. A power combiner with such a topology, however, is less practical since the amplifier load the antenna will have a ground connection. Consequently, for practical implementations of the Chireix s outphasing amplifier, a common-mode power combiner realized by quarter-wavelength transmission lines is usually adopted, which is illustrated in Figure.11. Figure.11: A practical Chireix s outphasing amplifier with a common-mode power combiner 15

26 Chapter. Chireix s outphasing amplifier For this topology, we will show that it can perform an equivalent function as that of the differential topology. Except the topology of the power combiner, other assumptions remain the same as those in Section.1.. Under these conditions, we will derive the theoretical efficiency of this Chireix s outphasing amplifier in the following section. Figure.1: Schematic of the output part of the practical Chireix s outphasing amplifier (without load compensation) Without load compensation, the schematic of the output part of this Chireix s outphasing amplifier is shown in Figure.1. First, the load admittance presented to each outphasing PA is obtained by using the transmission matrix of the lossless quarter wavelength line. Then, based on the varying admittance, the theoretical efficiency is derived. The transmission matrix of a lossless transmission line having a characteristic impedance Z 0 and an electrical length θ is cosθ jz sinθ = jsinθ C D cosθ Z 0 A B 0 (Equation.) For a quarter-wavelength line (θ =90 o ) having a characteristic impedance Z 0, its transmission matrix is 0 jz 0 A B = j C D 0 λ 4 Z 0 (Equation.3) Then we have the input-output relations of the quarter-wavelength lines in the two branches: 16

27 Chapter. Chireix s outphasing amplifier V = jz I and V = jz I 1 0 o1 0 o j j I = V I = V 1 Z0 Z0 The voltage sources remain the same as in (Equation.8, thus (Equation.4) + jφ jφ V1+ V Vo( e + e ) Vocosφ I = Io1+ Io = = = jz jz jz V Vo cosφ = IR = R jz o j V cosφ Vocosφ Z I = I = V = R = where R = Z Z R R Therefore, the load admittances presented to the PAs are 0 (Equation.5) Vo cosφ I R 1 cos φ sinφ Y1 = = = j = G j o jb + φ o V V e R R where 1 o cos φ sinφ G o = and B o = R R Vo cosφ I R cos φ sinφ * Y = = = + j = G o + jb o = ( Y ) jφ V V e R R 1 o which are illustrated in Figure.13. (Equation.6) Figure.13: oad admittances presented to each PA in the practical Chireix s outphasing amplifier; (a) upper branch (b) lower branch 17

28 Chapter. Chireix s outphasing amplifier According to (Equation.17, the efficiency of this Chireix s outphasing amplifier without load compensation is given by (Equation.7. The efficiency as a function of the outphasing angle is plotted in Figure.13(a). cos φ G o R η= ηb cos( Y) = ηb = η B G o + B o cos φ sinφ ( ) + ( ) R R = η cosφ B Recall (Equation.14, the output RF power of the amplifier is given by (Equation.7) V P = V G = φ (Equation.8) dc RF dc o cos R The efficiency versus the normalized output RF power is plotted in Figure.13(b). This curve is identical to that in Figure.5 but now with an inverse dependence on the outphasing angle, which proves this practical topology is an equivalence of that differential topology discussed in Section.1.. (a) (b) Figure.14: Theoretical efficiency of the practical Chireix s outphasing amplifier; (a) Efficiency versus outphasing angle (b) Efficiency versus normalized output power 18

29 Chapter. Chireix s outphasing amplifier Figure.15: oad compensation in the practical Chireix s outphasing amplifier; (a) upper branch (b) lower branch The load compensation in the practical Chireix s outphasing amplifier is shown in Figure.15. After the load compensation components being added into the branches, the load admittances presented to each PA in the practical Chireix s outphasing amplifier are cos φ sinφ sinφ Y 1 = Y1 + j( + B comp ) = G o j( B o B comp) = j R R cos φ sinφ sinφcomp Y = Y + j( B comp) = Go + j( B o B comp) = + j = ( Y 1) R R where sin φ B comp = R comp comp (Equation.9) Also according to (Equation.17, the theoretical efficiency of the practical Chireix s outphasing amplifier with load compensation is given by * η = η cos( Y ) = η = η B B B G + ( B B ) cos o o comp ( cos φ) + ( sin φ sin φcomp) φ G o (Equation.30) The output RF power remains the same as that in (Equation.8 because the added compensating reactance or susceptance is lossless. The normalized efficiency for three different compensation angles (φ comp =10 o, 0 o, and 45 o ) of the Chireix s outphasing amplifier is plotted in Figure.16. Note the opposite phase dependency with respect to the earlier found results (Figure.9) The normalized efficiency can also be plotted as a function of the 19

30 Chapter. Chireix s outphasing amplifier normalized output RF power, which is illustrated in Figure.17. Figure.16: Normalized efficiency versus outphasing angle of the practical Chireix s outphasing amplifier at three compensation angles (φ comp =10 o, 0 o, and 45 o ) As shown in Figure.17, the dependence of the efficiency on the output power back-off is identical to that of the differential topology depicted in Figure.10. This is additional evidence that the common-mode topology is the equivalent of the differential topology for the Chireix s outphasing operation. Because of the indispensable ground connection needed by the load antenna, the common-mode topology is chosen for the practical implementation of the Chireix s outphasing amplifier. Figure.17: Normalized efficiency versus normalized output power of the practical Chireix s outphasing amplifier at three compensation angles (φ comp =10 o, 0 o, and 45 o ) As mentioned before, the topology of the power combiner determines how the SCS should be realized. For a common-mode topology of power combiner, the Chireix s outphasing system needs a different realization of the SCS from that of the differential topology. For the original input signal 0

31 Chapter. Chireix s outphasing amplifier V in( t ) = Vt ( )exp{ jϕ ( t)}; 0 Vt ( ) Vm The SCS for the common-mode topology should convert it into two PM signal components in the following forms: Vm V in1( t) = exp{ j[ ϕ( t) + φ( t)]} Vm V in( t) = exp{ j[ ϕ( t) φ( t)]} Vt () where φ( t) = arccos[ ] V m (Equation.31) Assuming the voltage gain of the PA is A v, the amplified signals at the output of the PAs are: Vm V(t) 1 = Vo exp[ + jφ( t)] = Av exp{ j[ ϕ( t) + φ( t)]} Vm V(t) = Vo exp[ jφ( t)] = Av exp{ j[ ϕ( t) φ( t)]} Vm where Vo = Av exp[ jϕ ( t)] According to (Equation.5, the output voltage at the load is (Equation.3) Vm V() t Av exp[ jϕ( t)] Vo cos[ φ( t)] Vm V() t = R = R jz 0 0 jz0 R π = Av V in( t) exp[ j ] Z (Equation.33) Which is a full recovery of the original input signal, except that a phase shift of 90 degrees is introduced which is caused by the quarter-wavelength transmission line. The phasor representation of the Chireix s outphasing operation for the common-mode topology is illustrated in Figure.18. 1

32 Chapter. Chireix s outphasing amplifier V ( t) in1 φ () t φ() t V ( t) in j () t e ϕ V ( t) Figure.18: A complex phasor representation of the Chireix s outphasing operation for the common-mode topology power combiner.3 A summary of Chireix s outphasing operation In this chapter, based on a few assumptions, the principle of the Chireix s outphasing operation is formulated for the case of a direct differential-topology power combiner as well as for a practical common-mode topology power combiner. Table.1 presents a comparison of Chireix s outphasing operation between these two cases. While there are some differences in the expressions, the underlying principle is identical for these two cases. Finally, the normalized theoretical efficiency of the Chireix s outphasing amplifier versus the normalized output RF power at four different outphasing angles 0 o, 10 o, 0 o, and 45 o is plotted in Figure.19, which is applicable to both the differential and common-mode topology. As can be seen from this figure, a proper selection of the load compensation can significantly enhance the efficiency of the Chireix s outphasing amplifier over a considerable range of the output RF power back-off. The next chapter will describe a practical implementation of the Chireix s outphasing amplifier based on the common-mode topology with load compensation. in Figure.19: Theoretical efficiency of the Chireix s outphasing system at four different compensation angles (0 o, 10 o, 0 o, and 45 o )

33 Chapter. Chireix s outphasing amplifier Table.1: A comparison of the Chireix s outphasing operation between a differential topology power combiner and a common-mode topology power combiner Input signal V ( t) in component signals V ( t) in1, oad voltage V() t oad admittances Y RF power P RF Efficiency η ( φ) Differential topology Vt ( )exp{ jϕ ( t)}; 0 Vt ( ) Vm Common-mode topology Vm π Vm exp{ j[ ϕ( t) ± φ( t)]} exp{ j[ ϕ( t) ± φ( t)]} Vt () Vt () where φ( t) = arcsin[ ] where φ( t) = arccos[ ] Vm Vm V1+ V Vocosφ V = R = R V = V1 V = Vo j sinφ jz0 jz0 = Av V in( t) R π = Av V in( t) exp[ j ] Z0 sin φ sin φ sin φcomp cos φ sin φ sin φcomp Y 1, = ± j Y 1, = j R R R R P dc RF = V Re{ Y } sin φ cos φ Z0 Vdc Vdc where R = R R R η ( φ) = η B cos( Y ) sin φ cos φ ηb η B sin φ sin φ sin φ cos φ + sin φ sin φ ( ) + ( comp ) ( ) ( comp ) 3

34 4 Chapter. Chireix s outphasing amplifier

35 Chapter 3. Design of a Chireix s/inc amplifier Chapter 3 Design of a Chireix's/INC amplifier 3.1 Design strategies and procedure As discussed in Chapter, a Chireix s/inc amplifier consists of three parts the SCS, the PAs, and the power combiner, and they respectively accomplish signal component separation, signal amplification, and amplified signal component recombination in the Chireix s outphasing operation. Such outphasing amplifier architecture allows for the use of nonlinear PAs driven by constant envelope signals, which can lead to dramatically higher efficiency than linear amplifier operation. These nonlinear PAs exhibit very high efficiency but they don t affect the final distortion levels at the system output because they operate at constant envelope signals. The major factors contributing to the linearity degradation include the SCS, realized either by an analog method or by a digital method, and the path imbalance between the two PA branches. Having an influence both on the efficiency and on the linearity, the power combiner is a place where the efficiency-linearity tradeoff needs to be dealt with. As an AM-PM converter, the SCS is conceptually clear, a practical realization of the SCS, however, is complex and difficult because the generation of the two component signals involves memoryless nonlinear signal processing that requires a high degree of accuracy. Various approaches have been proposed to achieve this function, but difficulties remain in terms of factors, such as implementation complexity, bandwidth, and power consumption, owing to the stringent distortion and noise requirements. A study of this topic alone for a operational hardware implementation needs considerable time and effort. Therefore, instead of striving to realize an analog hardware implemented SCS, we aim for a digital SCS implementation and focused our efforts on the design and implementation of the PAs and the power combiner. For this digital SCS implementation we will rely on arbitrary waveform generators and I/Q (In-phase/Quadrature) up-converting modulators to generate the two phase modulated RF input signals. Software will be used to implement the AM-PM signal conversion. Our final goal is to create an amplifier that provides high efficiency and excellent linearity simultaneously. It seems natural that we carry out the design of the outphasing amplifier in two steps first the design of the efficient PA cells and then that of the power 5

36 Chapter 3. Design of a Chireix s/inc amplifier combiner. The first thing in the PA cell design, is to choose a suitable amplifier operation m ode. Depending on the operation mode that is selected, the power combiner design has to be adjusted accordingly because different operations need different output terminations from the power combiner. Consequently, the amplifier mode choice and the power combiner choice must be made together, which should be done before stepping into the PA cell design and the power combiner design. 3. Amplifier and power combiner choices Basically there are two kinds of power combiners: isolating power combiners and nonisolating lossless power combiners. An isolating power combiner provides isolation between its input ports. In a classical INC system that employs isolating power combiners, the inherent high linearity of the INC operation can be preserved, but the considerable power loss in the combiners results in significant efficiency reduction. By contrast, a non-isolating lossless power combiner in the PA output yields significant interaction between the amplifiers, which leads to AM-AM and AM-PM distortion, however it provides a much better efficiency. Therefore, both types of power combiners have advantages and disadvantages when applied in a INC system. For an outphasing system implemented with an isolating power combiner, the amplifier mode choice is relatively unrestricted because the isolated inputs of the matched combiner provide fixed output terminations at the output of the PAs. For a system using a non-isolating lossless power combiner, however, the output interactions must be carefully designed because the overall output impedance of each component PA is established by the outputs of both PAs. If the PAs act as voltage sources, the overall impedance presented to the amplifier by the power combiner must not be zero for any possible phase difference between the two PAs. In contrast, for the PAs acting as current sources, the overall admittance must not be zero. In a Chireix s outphasing system, as discussed in the previous chapter, the Chireix s power combining technique employs a three-port, non-isolating lossless power combiner implemented by two quarter-wavelength transmission lines. This non-isolating Chireix s combiner introduces significant interaction between the two PAs, which generates timevarying loads that are presented to the output of each PA. The Chireix s outphasing operation requires the two PAs to resemble a behavior that approximates a voltage source. Relevant work has shown that saturated class-b, class-f, and voltage-mode class-d PAs have an output current-voltage relationship that is similar to that of a voltage source. As a result, we 6

37 Chapter 3. Design of a Chireix s/inc amplifier can choose either of them to implement a high-performance Chireix s outphasing amplifier. In our design, we chose to implement saturated class-b PAs because the practical achievable efficiency of saturated class-b amplifiers is close to that of class-f amplifiers or voltagemode class-d amplifiers while saturated class-b amplifiers are comparatively easy to realize. 3.3 Power amplifier cell design The design of a class-b PA cell is to find the conditions under which the given active device can operate in class-b mode and to realize these conditions also in the circuit. These conditions include bias points, input conditions, output terminations, and stabilization conditions. In order to determine these conditions, first we need to know what is a saturated class-b mode. The power amplifiers are loosely divided into two categories based on how the active device behaves. One is the linear (or transconductance mode) PAs and the other is nonlinear (or switch mode) PAs. Depending on the conduction angle, defined as the part of the RF signal period during which the transistor is carrying current, the linear PAs can be classified into several classes, such as class-a, class-b, class-ab, and class-c. The corresponding output current and voltage waveforms are shown in Figure 3.1. Table 3.1 lists the bias point and conduction angle for each corresponding operation mode. Figure 3.1: Current and voltage waveforms of PA in different classes of operation In a class-b mode, the gate bias voltage equals the pinch-off voltage, resulting in a conduction angle of half the RF signal period (π), and a halfwave-rectified sinewave for the drain current. Therefore, the transistor consumes less dc power than class-a and is more 7

38 Chapter 3. Design of a Chireix s/inc amplifier efficient. With all the harmonics shorted, the output voltage across the load only has a fundamental component and therefore has a perfect sinusoidal waveform. An appropriate choice of the load can make the amplitude of the output voltage equal to the dc supply voltage. Based on these assumptions, the theoretical maximum efficiency of class-b operation is π/4 (or 78.5%). Table 3.1: Classical model of operation Mode Normalized bias Normalized Conduction angle point quiescent current class-a π class-ab π-π class-b 0 0 π class-c <0 0 0-π In a saturated class-b mode, also referred to as an overdriven class-b, the sinewave amplitude of the drain current is increased over the maximum linear swing by raising the input drive level. If the load resistor is assumed to have the ideal linear loadline value that would be designed for optimum class-a operation, a symmetrically clipped voltage waveform will be generated because of the clipping of the current waveform. Such a clipped voltage waveform closely approximates a harmonically synthesized squarewave and therefore brings benefits to efficiency. Both the input condition (the drive level) and the output terminations (including the choice of the load) significantly influence how well a saturated class-b mode can be realized. These conditions can be determined through the load-pull simulation. The squaring of the voltage waveform can effectively enhance the efficiency, in practice, however, due to the transistor knee effect, the clipped waveform will cause a lower peak current swing and, consequently, lower RF power. Therefore, there is a tradeoff between efficiency and power and we have to make a proper compromise when determining the drive level and the load impedance in a load-pull simulation. After knowing what really constitutes a saturated class-b amplifier, we can start designing the saturated class-b PA cell. We follow the following procedures to perform the PA cell design: 1) Check the characteristics of the active device and determine the bias points. ) Make the device unconditionally stable by introducing a proper input stabilization 8

39 Chapter 3. Design of a Chireix s/inc amplifier network. 3) Partially compensate the parasitic effects of the device package. 4) Determine the input conditions and the optimum load impedance by load-pull simulation 5) Use ideal components to verify the functionality of the PA cell. 6) Implement the PA cell by using realistic components Device characterization and bias points Various power amplifier technologies are competing for market share like Si-DMOS (ateral-diffused MOS), bipolar transistors, GaAs MESFETs (Metal Epitaxial Semiconductor FET), GaAs (or GaAs/InGaP) HBTs (Hetero-junction Bipolar Transistors), SiC MESFETs, and GaN HEMTs. The properties of GaN HEMT compared to the competing technologies is shown in Table 3.. Table 3.: Attributes of various power amplifier technologies Attribute Si GaAs SiC GaN Energy Gap (ev) Breakdown E-Field (V/cm) Saturation Velocity (cm/s) Electron Mobility (cm /V s) Thermal Conductivity (W/cm K) Maximum Temperature ( C) JFOM BFOM The GaN material has much better BFOM (Baliga s figure of merit for power transistor performance) and JFOM (Johnson s figure of merit for power transistors performance) than its competitors. This outstanding performance is attributed to the following advantages it has: 1. The room temperature energy gap of 3.4 ev enables GaN devices to support internal electric fields about five times higher than Si or GaAs, which means GaN has a higher breakdown voltage, a desirable attribute of power devices.. As a member of HEMT family, the GaN device also inherits the feature of HEMT high electron mobility. In the RF/Microwave domain, high electron speeds are required to minimize internal device delays. 3. Benefiting from the excellent thermal conductivity of its SiC substrate, the GaN 9

40 Chapter 3. Design of a Chireix s/inc amplifier HEMT is very suitable for high power devices with reduced cooling requirements. Therefore, we employ GaN HEMT as the active device in our PA cell design. (a) (b) Figure 3.: GaN HEMT large signal models; (a) package model CGH40045F (b) bare die model CGH40060D (a) (b) Figure 3.3: The circuit model for package parasitics and the bare die model; (a) package parasitics and bare die model (b) a simplified symbol for both The active device used in the PA cell is the 45 watt GaN HEMT delivered by Cree. Two sets of large signal models CGH40045F and CGH40060D (Figure 3.) have been provided for this device. CGH40045F is the large signal model of the whole device package, which models both the die transistor and the package parasitics, whereas CGH40060D is the large signal model for the bare die transistor alone, along with which a circuit model for the package parasitics has also been provided (Figure 3.3). Using the DC simulation in ADS, we can check the DC characteristics of the package model CGH40045F. The I D -V GS and the I D -V DS relationships are plotted respectively in Figure 3.4 and Figure

41 Chapter 3. Design of a Chireix s/inc amplifier Figure 3.4: I D versus V GS (V DS =8V) Figure 3.5: I D versus V DS (V GS =-3.0V::0.5V::1V) As can be seen from these figures, the DC characteristics of the GaN device are listed in the following table. Table 3.3: DC characteristics of Cree GaN HEMT CGH40045F Device DC characteristics Typical Value Conditions Pinch-off voltage -.9V V DS = 8V Drain-Source breakdown 10V V GS = -3V~1V Transconductance 4000mS V DS = 8V, I D =6A Saturated drain current 1.5A V DS = 8V For a class-b operation, the gate bias voltage should be set at the pinch-off point. The valid drain voltage for this device is from 8V to 48V. We chose the lowest one as the drain bias voltage so that the device would stay in the saturation during most of the half RF signal period even when the input power backs off. In such a way, the device can better 31

42 Chapter 3. Design of a Chireix s/inc amplifier approximate an ideal voltage source. As a result, the bias points for the active device are: V G =.9V and V = 8V 3.3. Device stabilization Stability is of great importance for an amplifier because all the design goals, such as efficiency and gain, will be lost once oscillation occurs. Therefore, it is essential to check and ensure the stability of the active device before starting the PA cell design. Here we used the single parameter μ criterion to judge the stability of the device. The μ criterion is actually an analysis of the small signal S-parameters of the device. For small signal S-parameter simulation, the device should be biased at the linear class-a operation. The schematic used to check the device s stability and the simulation result are shown in Figure 3.6. D (a) (b) Figure 3.6: Device stability checking; (a) circuit schematic (b) simulation result The design frequency for our Chireix s outphasing amplifier is.14 GHz. Apparently, this device is not unconditionally stable around the design frequency and it is necessary to make the device stable. Because the load of the outphasing amplifier is modulated by the 3

43 Chapter 3. Design of a Chireix s/inc amplifier outphasing angle, the load impedance varies as the envelope of the original AM signal alters. Furthermore, under extreme circumstances the antenna may be even short-circuited or become open-circuit, which may lead to unexpected load impedance presented to the output of the amplifiers. Therefore, to avoid disastrous consequences the safest way to handle the stability problem is making the device unconditionally stable over the whole smith chart by introducing into the circuit a proper stabilization network. Earlier a stabilization network was developed by Mr. Marco Pelk to stabilize the same kind of device in another amplifier design. We also used this stabilization network (Figure 3.7) in our Chireix s outphasing amplifier design. The schematic and simulation result in Figure 3.8 show the stabilization effect of this network. Figure 3.7: Input stabilization network and its simplified symbol Courtesy of Marco Pelk (a) 33

44 Chapter 3. Design of a Chireix s/inc amplifier (b) Figure 3.8: Stabilization effect of the stabilization network; (a) circuit schematic (b) simulation result Partially compensating the parasitic effects of the package As can be seen from Figure 3.3(a), in the circuit model of the package parasitic effects, there are a π-type network and a short transmission line at the drain of the die model. The π- type network also acts like a very short transmission line. Therefore, the overall effect of the π-type network and the short transmission line can be approximated by a parasitic transmission line, which transforms the load impedance presented to it (the fundamental as well as the harmonic ones). Such a parasitic impedance transformer impairs the Chireix s outphasing operation. This impedance transformation effect can be partially compensated by adding a proper transmission line, as shown in Figure 3.9. The principle of this compensation is to make the total electrical length of the added transmission line and the parasitic transmission line roughly equal to π or 180 degrees for the fundamental impedance so that the total phase shift of the impedance produced by these two transmission lines is approximately π or 360 degrees, i.e. on the Smith chart the impedance is rotated a circle and back to the original point. Ideally, with a complete compensation, the impedance seen by port 1 would be exactly the same as R in. Note that only a small shift in the real part is remaining after the insertion of the line which realizes a partial compensation. We will include this line in our subsequent load-pull simulations. Because the compensation is carried out for the fundamental impedance, it is only valid for the fundamental impedance, generally not valid for the higher harmonic impedance because the π-type network is not a transmission line after all. For a special case the even harmonic short, especially for the second harmonic short, however, it remains valid enough. The parasitics compensation effect for the second harmonic short can be seen from Marker in Figure 3.9(b). As can be seen from this simulation result, providing even harmonic shorts after the compensating transmission line is approximately equivalent to providing them at the 34

45 Chapter 3. Design of a Chireix s/inc amplifier internal drain of the bare die inside the package. (a) (b) Figure 3.9: Partial compensation of the package parasitics (a) circuit schematic (b) simulation results oad-pull determining the optimum load impedance As discussed before, both the input conditions and the output terminations influence the efficiency. To maximally transfer power from the source to the active device, an input conjugate match is needed. To achieve excellent efficiency, a proper input drive level and optimum fundamental impedance are needed besides suitable harmonic terminations. The input impedance for the input match can be determined by a large signal S- 35

46 Chapter 3. Design of a Chireix s/inc amplifier parameter simulation. Then, based on this input impedance, an input matching network can be implemented. A rough value of the required source power can be estimated by the rated power and gain of the active device. The rated power of the GaN HEMT we use is 45 watts, which means that the maximum output power realizable in practice for this device is 45 watts. Experience from previous work shows that the 45 watt GaN HEMT has a gain about 10 db. Therefore, a suitable input power level is approximately 4.5 watt or 36.5 dbm. In a load-pull simulation, the fundamental load impedance in a certain region of the Smith chart is swept so that the optimum termination for the maximum efficiency with the maximum practically realizable output power (45W or 46.5dBm) is found. A rough estimate of the optimum real part of the load impedance can be made according to the following loadline equation: R opt Vdc 8 = = = 4.5 Ω (Equation 3.1) I / 1.5/ max which can be used as a starting point of the load-pull simulation. During the whole process of the load-pull simulation, the following steps are carried out: 1) At the input, a 36 dbm power source at.14 GHz is provided as the excitation. The source impedance is set at 50 ohm for all the frequency components. At the output, even harmonic shorting is realized by an SCSS (Short-Circuit Shunt Stub); the load impedance is set at 50 ohm for the higher harmonics and the fundamental load impedance is 50 ohm by default before the load-pull simulation ) A large signal S-parameter simulation is performed to determine the input impedance. The fundamental component of the source impedance is then set at the conjugate of the obtained input impedance to realize an input conjugate match. 3) Perform the load-pull simulation to determine the optimum load impedance under present conditions. 4) Set the fundamental component of the load at the optimum load impedance just obtained. Because of the change of the load, the input impedance also changes, which leads to a slight mismatch at the input. Redo the input match as in step to achieve a new input match. 5) With the new input match, perform the load-pull again to obtain a slightly more accurate value of the optimum load impedance. Because the change of the optimum impedance is 36

47 Chapter 3. Design of a Chireix s/inc amplifier slight, it has little influence on the new input match. Consequently, we can accept this input match and obtain a better value of the optimum impedance as well. (a) (b) Figure 3.10: oad-pull simulation; (a) schematic (b) simulation result The circuit schematic and the simulation results are shown in Figure In this schematic, the microstrip line used for package parasitics compensation has been converted into an ideal transmission line (Tcomp) by using the inecalc in ADS. Table 3.4: Results of the load-pull simulation and the corresponding conditions Performance Conditions Output Power 46.8 dbm Input power 36 dbm Efficiency 78.4% Source impedance 50*(0.031-j*0.17) ohm PAE 71.7% Optimum load admittance j*0.103 S 37

48 Chapter 3. Design of a Chireix s/inc amplifier From the above load-pull simulation, we have determined the input impedance for the input match and the optimum admittance for the maximum efficiency at the maximum output power (Table 3.4). Note that, because power contour and efficiency contour normally have different centers, actually such a load is neither optimum only for the efficiency nor for the output power alone, but is a compromise between high output power and high efficiency. If we choose the load for the maximum output power (48.76 dbm, about 75W), the efficiency will be much lower than 78.5%, the theoretical efficiency of class-b PA. If we choose the load for the maximum efficiency (84.87%), the output power will be much lower than the output power rating of the GaN HEMT (45W or 46.5 dbm). Neither of these two results are desirable for the transmitter in the base station applications. The optimum load we choose is such that the efficiency can be as high as possible while the output power remains slightly above the output power rating, 45 watts. Such a load can be regarded as an optimum one for the maximum efficiency with an output power at the output power rating of the device. In the final Chireix implementation the load will be a varying function of the outphasing angle. However, the data obtained will help us to achieve the peak power conditions for the amplifier to be completed. For this load-pull simulation, one thing needs to explain is the location of the SCSS. As mentioned in Section 3.3.3, the package parasitics compensation is valid enough for even harmonic short, and therefore point B in Figure 3.10(a) is equivalent to the internal drain of the bare die for providing even harmonic short. It is natural that we should put the SCSS at point B to provide nearly perfect even harmonic short for the internal drain. In our load-pull circuit, however, the SCSS was located at point A. The reason is that what the internal drain needs for obtaining maximum efficiency is not a perfect second harmonic short but a second harmonic impedance that is a little bit inductive (a possible explanation for this is that the active device is not an ideal device but a device with inherent parasitics such as parasitic capacitance). It is purely coincident that an SCSS at point A, along with the package parasitics, can provide such a somewhat inductive impedance for the second harmonic. As a result, providing even harmonic shorts at point B or at the internal drain produces rather lower efficiency than at point A. By contrast, the load-pull simulation and results in the case of providing even harmonic shorts at the internal drain are shown in Figure

49 Chapter 3. Design of a Chireix s/inc amplifier (a) (b) Figure 3.11: oad-pull simulation with even harmonic shorts at the internal drain; (a) schematic (b) simulation result In addition, a load-pull simulation aiming for the optimization of the second harmonic short was also performed. With the optimized second harmonic short, the efficiency can be further increased by in percentage, but the price is a drop of the output power. Because the improvement of the efficiency is not significant, we choose not to optimize the second harmonic short. In the following design, we will use the results in Table 3.4 to realize the PA cell Functionality verification with ideal components In this section, the implementation of the class-b PA cell by using ideal components will be described. In order to implement the PA cell, three conditions need to be realized. They are the input match, the even-harmonic shorting, and the output loadline match. 39

50 Chapter 3. Design of a Chireix s/inc amplifier (a) (b) Figure 3.1: Input matching network realized with ideal transmission lines; (a) circuit schematic (b) simulation result Figure 3.13: Output matching network realized with ideal transmission lines; (a) circuit schematic (b) simulation result An input matching network can be realized by using lumped elements or ideal transmission lines to transform the input impedance to the 50 ohm source impedance. The input matching network realized by ideal transmission lines is shown in Figure 3.1. The output matching network can be realized in the same way. Figure 3.13 presents the design of the output matching network. The even-harmonic shorting can be realized by a SCSS. The PA cell realized with ideal components is shown in Figure As can be seen from the simulation results, the efficiency and the output RF power are very close to the values obtained from the load-pull simulation. 40

51 Chapter 3. Design of a Chireix s/inc amplifier (a) (b) Figure 3.14: class-b PA cell realized with ideal components; (a) circuit schematic (b) simulation results Implementation with realistic components While simulation with ideal components can show maximum attainable performance, what we really need is a circuit fabricated with realistic components. The input matching network and the output matching network realized with ideal transmission lines can be transformed into practical realizations of microstrip lines by using the inecalc tool in ADS, so is the SCSS that performs the even harmonic shorting. The input matching network realized with practical microstrip lines and 0603 SMCs (Surface Mounted Components) is illustrated in Figure 3.15 and the output matching network in Figure 3.16 while Figure 3.19 shows the final class-b PA cell realized with realistic components. (a) (b) (b) Figure 3.15: Input matching network realized with SMD capacitor and microstrip lines; (a) circuit schematic (b) simulation result 41

52 Chapter 3. Design of a Chireix s/inc amplifier (a) (b) Figure 3.16: Output matching network realized with SMD capacitor and microstrip lines; (a) circuit schematic (b) simulation results SMCs are the components used in Surface Mount Technology (SMT). In SMT, SMCs are mounted directly onto the surface of printed circuit boards (PCBs) to construct electronic circuits. Electronic devices so made are called surface-mount devices or SMDs. In the industry SMT has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. SMCs are usually smaller than their counterparts with leads, such as through-hole components, because they have either smaller leads or no leads at all. They may have short pins or leads of various styles, flat contacts, a matrix of solder balls, or terminations on the body of the component. SMCs are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes. For example, the two-terminal packages of rectangular passive components (mostly resistors and capacitors) are listed in Table 3.5. Table 3.5: Sizes of two-terminal packages of rectangular passive components (mostly resistors and capacitors) Type Size Typical power rating for resistors (040 metric) 0.016" 0.008" (0.4 mm 0. mm) 1/3 Watt 001 (0603 metric) 0.04" 0.01" (0.6 mm 0.3 mm) 1/0 Watt 040 (1005 metric) 0.04" 0.0" (1.0 mm 0.5 mm) 1/16 Watt 0603 (1608 metric) 0.063" 0.031" (1.6 mm 0.8 mm) 1/16 Watt 0805 (01 metric) 0.08" 0.05" (.0 mm 1.5 mm) 1/10 or 1/8 Watt 106 (316 metric) 0.16" 0.063" (3. mm 1.6 mm) 1/4 Watt 1806 (4516 metric) 0.177" 0.063" (4.5 mm 1.6 mm) 181 (453 metric) 0.18" 0.1" (4.5 mm 3. mm) 1/ Watt 010 (505 metric) 0." 0.1" (5.0 mm.5 mm) 51 (633 metric) 0.5" 0.1" (6.35 mm 3.0 mm) In our design, we use 0603 SMD components. The parasitics of the 0603 SMD capacitors are: 4

53 Chapter 3. Design of a Chireix s/inc amplifier Series resistance: 0.4 Ohm Series inductance: 0.75 nh The parasitics of the 0603 SMD resistors are: Series inductance: 0.8 nh The 0603 SMD pad parasitics are shown in Figure 3.17 and Figure (a) (b) Figure 3.17: 0603 SMD two-capacitor component and its simplified symbol; (a) pad parasitics and capacitors (b) simplified symbol (a) (b) Figure 3.18: 0603 SMD three-capacitor component and its simplified symbol; (a) pad parasitics and capacitors (b) simplified symbol 43

54 Chapter 3. Design of a Chireix s/inc amplifier (a) (b) Figure 3.19: Class-B PA cell realized with realistic components; (a) circuit schematic (b) simulation performance 3.4 Chireix's outphasing system design Based on high efficiency PA cells, a Chireix s outphasing system can be implemented by connecting them with an appropriate power combiner. This section describes the procedure of Chireix s outphasing system design. First the design of the Chireix s power combiner is discussed in detail and special consideration for the bandwidth has been given to the design of the power combiner. Then two branches of PA are combined together to constitute a Chireix s outphasing system. The implementation of the Chireix s outphasing system is performed in three steps. First, ideal voltage sources and ideal components are used to verify the concept of Chireix s outphasing operation. Also, ideal voltage sources are replaced by power sources with source impedance to check the influence of the source impedance on the outphasing operation. Next, actual active device and ideal components are used to realize the outphasing system. Finally, all ideal components are replaced by practical components to finish the implementation of a practical Chireix s outphasing system Power combiner design The Chireix s power combining technique employs the three-port, non-isolating lossless power combiner implemented by two quarter-wavelength transmission lines complemented with Chireix s complex load compensation for a particular compensation angle. When the 44

55 Chapter 3. Design of a Chireix s/inc amplifier outphasing angle is equal to the compensation angle, the efficiency of the total Chireix amplifier should peak. In order to make this efficiency peaking also happen in practice, the impedance offered to the internal device (excluding any parasitics) should be real, this requires that all reactive device elements (e.g. output capacitance) and the susceptance due to outphasing effect must be compensated at these angles. G opt Branch 1 CDS Bopt λ, 4 Z 0 compensation R Branch Figure 3.0: A simplified circuit schematic for one branch of the Chireix s outphasing system at zero outphasing angle without load compensation According to the principle of Chireix s outphasing operation discussed in Chapter 3, before compensating the susceptance due to outphasing effect, the efficiency of the outphasing system peaks at zero outphasing angle because the active device is presented with just a real conductance at this outphasing angle. In order to make this peak efficiency equal to the PA s maximum efficiency obtained from the load-pull simulation, the active device should be presented with the optimum admittance (Y opt = G opt + j*b opt ) determined in the load-pull simulation. This can be realized by making the conductance due to outphasing effect equal to the optimum conductance (G opt ) and compensating the output capacitance with the optimum susceptance (B opt ). The simplified schematic for the circuit at zero outphasing angle without load compensation is shown in Figure 3.0. The characteristic impedance of the quarter wavelength line can be determined by the equal relationship between the conductance due to outphasing effect and the optimum conductance. Such an equal relationship at zero outphasing angle requires: 45

56 Chapter 3. Design of a Chireix s/inc amplifier cos φ 1 φ= 0 opt i.e. φ= 0 R R G = G = = G Z R = = G R opt 0 R 50 Z0 = = = 38.1 Ohm G opt opt (Equation 3.) The resulting power combiner is shown in the simplified circuit schematic illustrated in Figure 3.1. G opt Branch 1 C DS B opt λ, Ohm 4 Z = compensation R = 50 Ohm G opt C DS B opt λ, Ohm 4 Z = Branch compensation Figure 3.1: A simplified schematic of the Chireix s outphasing system without load compensation In this power combiner, the impedance transformation from 50 ohm load to the optimum conductance in each branch is realized by only one stage of matching network one quarter wavelength line. There are various solutions to such a matching problem. The above solution is the most direct and simplest one, but it is not a wide-band matching network and has a limited bandwidth. Theoretically, wide-band matching networks can be realized by cascading multiple stages (the trajectory of each stage on the Smith chart confined in the lowest Q contour). Too many stages, however, require more components and produce a more complex matching network. Here, we made a compromise between the bandwidth and the simplicity of the matching network. We realized this match by inserting another quarter wavelength line, i.e. by cascading two stages of transmission lines in the matching network. Figure 3. presents a simplified schematic of this two-stage power combiner. 46

57 Chapter 3. Design of a Chireix s/inc amplifier G Branch 1 opt CDS Bopt λ, Ohm 4 Z = compensation λ, Ohm 4 Z = G opt CDS Bopt λ, Ohm 4 Z = Branch R = 50 Ohm compensation Figure 3.: A simplified schematic of the Chireix s outphasing system without load compensation with a two-stage power combiner (a) (b) Figure 3.3 Bandwidth of the single-stage power combiner; (a) circuit schematic (b) simulation result 47

58 Chapter 3. Design of a Chireix s/inc amplifier For this two-stage power combiner, we have optimized its 3 db bandwidth by tuning the characteristic impedance of each quarter wavelength line in ADS. Alternatively, we can also make the power transfer of the power combiner a Butterworth type by calculation to obtain an optimum bandwidth. Compared to the simple single-stage realization, the bandwidth has been significantly improved in the two-stage power combiner. Circuit schematic and bandwidth simulation results of the single-stage power combiner and those of the two-stage power combiner are shown respectively in Figure 3.3 and Figure 3.4. (a) (b) Figure 3.4: Bandwidth of the two-stage power combiner; (a) circuit schematic (b) simulation result 3.4. Chireix s outphasing system without load compensation With the power combiner, two branches of PAs can be linked together to construct a Chireix s outphasing system. Before we use the real active device to build the PAs, ideal voltage sources and ideal components are used to verify the functionality of the outphasing 48

59 Chapter 3. Design of a Chireix s/inc amplifier operation. The circuit schematic and simulation results are shown in Figure 3.5. In order to model the maximum output power of the GaN HEMT (45 watts), the voltage of the ideal voltage source is set at 36.1 volts, which can produce 45 watt output power at the optimum conductance (G opt = 0.069) in each branch. From the theoretical derivation for Chireix s outphasing operation in Chapter, recalling (Equation.6, (Equation.7, and (Equation.8, we have: Y 1, cos φ sinφ G = j = G j R R η= η cosφ V B opt opt cos φ sin dc RF = cos φ= GoptVdc cos R P The simulation results of the admittance, output power, and the normalized efficiency shown in Figure 3.5(b) agree with these theoretical predictions pretty well. Note that V dc here represents the amplitude of the ideal voltage source, i.e volts. The reason that it differs from the dc supply voltage (8 volts) is that the PA we have designed is not a perfect class-b mode. For a perfect class-b operation mode, all the higher harmonics should be shorted. In our PA operation, we have only provided even harmonic shorts and left the odd harmonic uncontrolled. φ φ (a) Circuit schematic (b) Admittance in each branch 49

60 Chapter 3. Design of a Chireix s/inc amplifier (c) Output power and normalized efficiency Figure 3.5: Ideal outphasing operation without load compensation; (a) circuit schematic (b), (c) simulation results Such a Chireix s outphasing system has been realized with the actual active devices and ideal components in the schematic shown in Figure 3.6(a). The simulation results are presented in Figure 3.6 (b) and (c). (a) Circuit schematic 50

61 Chapter 3. Design of a Chireix s/inc amplifier (b) Admittance in each branch (c) Output power and efficiency Figure 3.6: Chireix s outphasing system realized with active devices and ideal components (without load compensation); (a) circuit schematic (b), (c) simulation results These curves do not well correspond to those simulation results of the outphasing operation using ideal voltage sources because the actual active devices are, after all, not ideal voltage sources, although they can be approximated by ideal voltage sources to some extent. One significant difference between an ideal voltage source and the actual class-b PA is that the latter has source impedance. If we replace the ideal voltage sources with power sources that have source impedance, the resulting simulation results will become similar to the results of the outphasing system using actual active devices. The outphasing system constructed by using power sources and ideal components is shown in Figure 3.7(a), and the simulation results are presented in Figure 3.7 (b) and (c). 51

62 Chapter 3. Design of a Chireix s/inc amplifier (a) Circuit schematic (b) Admittance in each branch (c) Output power and normalized efficiency Figure 3.7: Ideal outphasing operation without load compensation (using power sources that have source impedance); (a) circuit schematic (b), (c) simulation results 5

63 Chapter 3. Design of a Chireix s/inc amplifier Note that the source impedance has been set equal to the inverse of the optimum conductance so that the maximum output power can be obtained for the optimum load. Power sources with source impedance can approximate the actual active device more accurately, but they are still simplified models of the actual active devices. Consequently, although very similar to the curves of the outphasing system using actual active devices, the simulation results still differ from them oad adjustment for Chireix s/inc operation For a PA cell realized with one active device, if the reactive device elements (e.g. output capacitance) could be fully compensated, the optimum load for the maximum output power at a proper level of high efficiency would be the resistance obtained from the loadline match condition: R V dc opt = I / (Equation 3.3) max Furthermore, even if the load resistance deviates from the loadline match value (e.g. becoming larger than R opt ), although the output power will deviate from the maximum value, the efficiency can still remain at a level comparable to the efficiency obtained at the optimum resistance as long as the load resistance is far smaller than the output resistance of the active device. On the other hand, if the output capacitance is not fully compensated by the reactive load, the efficiency will degrade as the load resistance deviates from the optimum resistance. In a Chireix s outphasing system, a varying load produced by the outphasing operation is presented to the PA in each branch. Both the load conductance and the load susceptance are modulated by the outphasing angle. With the load compensation, the load susceptance due to outphasing effect is compensated at two compensation angles (φ comp and 90 o -φ comp ). With a proper susceptance B pro added to completely compensate the output capacitance (C DS ) of the active device, the efficiency should peak and become close to the efficiency obtained at the optimum conductance at these two compensation angles. High efficiency at two compensation angles is key to the good performance of a Chireix s outphasing system. A proper load admittance, especially a proper load susceptance B pro, is needed to ensure the achievement of high efficiency at these compensation angles. In Section 3.3.4, we have obtained the optimum load (Y opt = G opt + j*b opt ) from the load- 53

64 Chapter 3. Design of a Chireix s/inc amplifier pull simulation. There is no guarantee that the susceptance B opt chosen from the load-pull simulation can fully compensate the output capacitance of the active device because the loadpull simulation is carried out only at zero outphasing angle. In the outphasing operation, such a load only ensures that the maximum efficiency with the maximum output power is obtained at zero outphasing angle when without load compensation. It does not guarantee the same high efficiency at two compensation angles. In order to make sure that high efficiency can be achieved at two compensation angles, a proper susceptance B pro has to be found which can better compensate the output capacitance of the active device. To do this, the circuit schematic in Figure 3.8 is used. (a) (b) B opt = (c) B opt = Figure 3.8: Optimum load adjustment for Chireix s outphasing operation; (a) circuit schematic (b), (c) simulation results before and after load adjustment In this circuit, an admittance equation component is used to model the conductance generated by the upper branch of the power combiner at the compensation angle. The conductance as a function of the outphasing angle is described as: 54

65 Chapter 3. Design of a Chireix s/inc amplifier G( φ) = G opt cos ( φ) (Equation 3.4) In our design, we aim to compensate the susceptance due to outphasing operation at 0 and 70 degree. Therefore, the optimum load susceptance need to be adjusted so that high efficiency can be achieved at these two compensation angles. Before the load adjustment, the load used in the outphasing operation is the optimum load obtained from the load-pull simulation. As can be seen from the simulation result in Figure 3.8(b), the efficiency at 0 degree is close to the efficiency at zero outphasing angle, but the efficiency at 70 degree is much lower. An outphasing system based on such a load will not have good performance. The reason is that the optimum susceptance B opt is not good enough for fully compensating the output capacitance of the active device. The load susceptance need to be adjusted. After the adjustment of the load susceptance, the simulation result is shown in Figure 3.8(c). Both the efficiency at 0 degree and that at 70 degree outphasing angle are very high, comparable to the efficiency obtained from the load-pull simulation. As a result, the new optimum load is: G B opt opt = = The Chireix s outphasing system will be based on this new optimum load admittance. (Equation 3.5) oad compensation For load compensation, the compensating susceptance is: B comp sin( φcomp) sin( φcomp) sin( φcomp) = = = Gopt R / G opt (Equation 3.6) In order to compensate the output capacitance of the active device, optimum susceptance components are needed by two branches. The combination of optimum susceptance and the compensating susceptance gives: B = B + G 1 opt B = B G opt opt opt sin( φ ) sin( φ ) comp comp (Equation 3.7) These susceptance components can be realized by shunt stubs. After adding the compensating susceptance components, the Chireix s outphasing system is illustrated by the simplified schematic in Figure

66 Chapter 3. Design of a Chireix s/inc amplifier Branch A C DS B opt B com p λ, 4 Z 0 compensation load compensation λ, 4 Z 1 Branch B R = 50 Ohm C DS B opt B comp λ, 4 Z 0 compensation load compensation Figure 3.9: A simplified schematic of the Chireix s outphasing system with load compensation Ideal implementation of Chireix s outphasing system For this ideal implementation of Chireix s outphasing system, we also perform the design in three steps. First, we use ideal voltage sources and ideal components to verify the concept of load compensation. Next, ideal voltage sources are replaced by power sources that have source impedances to see the change of the simulation results. Finally, we use the actual active device, along with other ideal components, to check the functionality of the Chireix s outphasing system. The circuit used to verify the concept of load compensation and the simulation results are shown below. (a) Circuit schematic 56

67 Chapter 3. Design of a Chireix s/inc amplifier (b) Simulation results Figure 3.30: Concept verification of Chireix s outphasing system with load compensation by using ideal voltage sources and ideal components; (a) circuit schematic (b) simulation results Recalling the theoretical derivation for the load compensation, i.e. (Equation.9, (Equation.30, cos φ sinφ sinφcomp G = j = G j R R Y 1, η= η cos( Y ) = η B B opt opt cos φ (sinφ sin φcomp ) cos ( cos φ) + ( sin φ sin φcomp ) φ we can see the simulation results of the varying admittance and the efficiency correspond to the theoretical results very well. Comparing the simulated efficiency curves with those in Figure.16 and Figure.17, we can draw the same conclusion. 57

68 Chapter 3. Design of a Chireix s/inc amplifier With the ideal voltage sources replaced by power sources having source impedance, the circuit schematic and simulation results become: (a) Circuit schematic (b) Simulation results Figure 3.31: Ideal Chireix s outphasing system with load compensation (realized by using power sources having source impedance and ideal components); (a) circuit schematic (b) simulation results 58

69 Chapter 3. Design of a Chireix s/inc amplifier One remarkable effect of the source impedance in the power sources is that the conductance now peaks at about 10 degree, between zero outphasing angle and the compensation angle (0 degree), instead of peaking at zero outphasing angle. Due to the change of the conductance curve, the output power now also peaks between zero outphasing angle and the compensation angle because theoretically the output power is proportional to the conductance ((Equation.8). The reason is that with load compensation, both the conductance at zero outphasing angle and the conductance at 0 degree (i.e. the compensation angle) considerably deviate from the optimum conductance for the maximum output power (i.e. G opt ). At a particular point between these two angles, however, a load close to the optimum load appears which has conductance very close to G opt, and therefore the output power peaks at that point. Finally, we use actual active devices and the ideal component to realize a Chireix s outphasing system with load compensation. The circuit schematic is shown in Figure 3.3 and Figure 3.33 presents the simulation results. As can be seen from the simulation results, the varying susceptance due to outphasing effect has been compensated at 0 degree and 70 degree outphasing angles. At these two compensation angles, both the output power and the efficiency for the two branches become equal because the loads for two branches become identical. Because very high efficiency (over 80%) has been realized at these two compensation angles, the overall efficiency of the Chireix s system remains high over a wide range of output power back-off. Figure 3.3: Chireix s outphasing system realized with actual active devices and ideal components 59

70 Chapter 3. Design of a Chireix s/inc amplifier (a) Varying load seen by B opt (b) Varying load including B opt (c) Varying load seen at the internal drain of each GaN HEMT 60

71 Chapter 3. Design of a Chireix s/inc amplifier (d) Efficiency and output power (thin for branch, thick for total) (e) Efficiency, output power, and efficiency versus output power Figure 3.33: Simulation results of the ideal implementation of the Chireix s outphasing system Practical implementation of Chireix s outphasing system Based on the ideal realization of the Chireix s outphasing system, a practical outphasing system can be implemented by using practical components. First, all ideal transmission lines should be replaced by practical microstrip lines. Based on the substrate used, the equivalent microstrip line dimensions of a particular ideal transmission line can be calculated by using inecalc in the ADS. At the crossings of transmission lines, microstrip bends or junctions have to be added to ensure the continuity of the transmission. After microstrip junctions are added, the dimensions of the microstrip lines connected to the junctions need to be adjusted 61

72 Chapter 3. Design of a Chireix s/inc amplifier to compensate the effect of the junction. While the process of replacing ideal transmission lines with microstrip lines seems clear, it is not always easy to transform an ideal transmission line network into a practical microstrip line network that fulfills an identical function. Usually the adjustment of the dimensions of the microstrip lines, i.e. the tuning of the size, is time-consuming because several parameters that correlate with each other might need to be tuned at the same time. Second, all the dc block components should be substituted by practical SMC capacitors and dc feed components should be replaced by practical bias inductors. Finally, additional microstrip lines are used at abrupt junctions (T7 and T8) or at the biasing (T1 and T) in order to make signal transmission more continuous. The final practical implementation of this Chireix s outphasing amplifier is shown in Figure Figure 3.35 shows the simulated performance of this outphasing system. The efficiency is about 74% at the peak output power and is kept above 55% over 10 dbm output power backoff range. (a) A panoramic view of the whole circuit (b) Input part and output part of the upper branch Figure 3.34: Circuit schematic of the practical Chireix s outphasing amplifier; (a) schematic of the whole circuit (b) input part and output part of one branch 6

73 Chapter 3. Design of a Chireix s/inc amplifier (a) Admittance seen before the output matching network (b) Admittance seen at the internal drain of GaN HEMT (c) Output power and efficiency (thick for total, thin for branch values calculated at the reference point of Y line ) 63

74 Chapter 3. Design of a Chireix s/inc amplifier (d) Efficiency versus output power Figure 3.35: Simulated performance of the Chireix s outphasing amplifier As can be seen from the efficiency curves in Figure 3.35(c), the total efficiency is not equal to the average of the two branch efficiencies, which means there are some losses in the circuit. In addition, it has also been noted that the loss at a large outphasing angle (e.g. 70 degree) is much higher than that at a small outphasing angle (e.g. 0 degree). In order to check the distribution of the losses, several current probes and voltage labels are added at different locations to calculate the different output power at the compensation angle. The circuit schematic used is shown in Figure 3.36(a) and the simulation results are shown in Figure 3.36 (b) and (c). Figure 3.36(b) shows that the main losses are located at the components before and after the reference point of Vload1, i.e. the microstrip line used for package parasitics compensation and the load compensation network. Another loss contributor is the microstrip curve bend used in the power combiner, which also causes a considerable amount of loss. The distribution of the losses in another branch has been found similar. These microstrip line networks are constituted not by ideal transmission lines but by practical microstrip lines based on a particular substrate, and therefore they cause some losses. In order to investigate the reason why the loss at large outphasing angle is higher than that at small outphasing angle, the loss as a function of the outphasing angle has been plotted in Figure 3.36(c). As can be seen from this curve, the loss goes up as the outphasing angle 64

75 Chapter 3. Design of a Chireix s/inc amplifier increases. (a) (b) Output power at 0 degree (c) Main loss versus outphasing angle Figure 3.36: Checking the losses in the Chireix s outphasing system; (a) circuit schematic (b) output power at 0 degree (c) main loss versus outphasing angle 65

76 Chapter 3. Design of a Chireix s/inc amplifier The reason can be found by examining the curve of the varying conductance generated by the power combiner. As the outphasing angle increases, the conductance, modulated by the outphasing angle, gradually decreases. At 0 degree, the conductance is very close to the optimum conductance needed for the maximum output power. At 70 degree, however, the conductance becomes far smaller than the optimum value. In other words, the varying load at 0 degree is close to the power match for the maximum output power and therefore little power is reflected by the load compensation network; by contrast, at 70 degree, the load considerably deviates from the power match and, as a result, more power is reflected by the load compensation network. Such reflected power will travel back as a power wave, and will be reflected again when it reaches the drain biasing network at the T-junction Tee1. Consequently, the power wave will experience multiple reflections between two T-junction Tee1 and Tee. Every time the power wave goes through the microstrip line used for package parasitics compensation (i.e. T4) or the load compensation network, some of its power will be dissipated and at a certain time all the power will be exhausted. The power dissipated is loss. At the very beginning, the load compensation network reflects more power at 70 degree than at 0 degree. As a result, the loss at 70 degree is higher than at 0 degree. This is also the reason why the theoretically supposed second peak of the total efficiency curve does not appear around 70 degree. 3.5 ayout implementation and measured results Figure 3.37: ayout of the Chireix s outphasing amplifier 66

77 Chapter 3. Design of a Chireix s/inc amplifier Figure 3.37 presents the final layout of this Chireix s outphasing amplifier, which was designed by using ADS Momentum. A prototype of this outphasing amplifier was fabricated and its performance measured (with the help of Mr. Jawad Qureshi). Figure 3.38 is a block diagram of the test bench for measuring the performance of this Chireix s outphasing amplifier. As mentioned before, instead of using an analog SCS, we rely on arbitrary waveform generator, along with the I/Q (In-phase/Quadrature) up-converting modulators, to generate two outphased PM input signals (RFin1 and RFin) for the Chireix s outphasing amplifier. Before these two PM signals enter the outphasing amplifier, each of them is first preamplified by two preamplifiers. The RF output signal of the outphasing amplifier is first attenuated and then sent to a mixer to be down-converted so that the original informationcarrying signal can be recovered. The data of the recovered signal is first acquired by using data acquisition cards (with a data rate of 100 mega samples per second) and then is sent to the system PC with MATAB to be compared with the original signal generated by the arbitrary waveform generator. A spectrum analyzer is used to analyze the spectrum of the attenuated RF output signal. Arbitrary Waveform Generator MATAB Data Acquisition Cards 100 MS/sec O Mixer RF IF I1 Q1.1MHz O I/Q Modulator 1 RFin1 Pre-amp Pre-amp RFout Attenuation I Q O I/Q Modulator RFin Pre-amp Pre-amp Chireix s Outphasing Amplifier Power Divider O Synthesizer Spectrum Analyzer Figure 3.38: Test bench of the Chireix s outphasing amplifier Figure 3.39 shows the measured efficiency as a function of the output power for different outphasing angles. As the outphasing angle increases, the conductance presented to each active device will gradually decrease. If the input power is fixed at the level for the maximum output power, which means the device is still overdriven, due to the decrease of the load conductance, the output power at high outphasing angle drops significantly, whereas the dc 67

78 Chapter 3. Design of a Chireix s/inc amplifier power remains comparatively high because the device is still overdriven. As a result, the efficiency at high outphasing angle becomes very low. If the input power is backed off, better efficiency can be achieved for the dc power will also start to go down. In the measurement, in order to find the best efficiency achievable for a certain outphasing angle, the output power of the amplifier is backed off by decreasing the input power. For an outphasing angle near the compensation angle, the efficiency of about 70% was measured at 48.5 dbm output power. This is the best measurement result of the Chireix s outphasing amplifier we have designed. Figure 3.39: Measured efficiency versus output power for different outphasing angles 3.6 Summary Based on the principle of Chireix s outphasing operation, a Chireix s outphasing amplifier with load compensation was implemented by using GaN HEMT and transmission lines. The circuit design and the layout design was carried out by using ADS 005A. Simulation results show that the drain efficiency of 74% is obtained at 49 dbm output power and the efficiency is kept above 55% over 10 db output power back-off range. A prototype based on microstrip lines was fabricated and the drain efficiency of 70% was measured at 48.5 dbm output power. 68

79 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier Chapter 4 Potential solutions to multi-band Chireix's/INC amplifier 4.1 A review of several current multi-band PA implementation To meet an increasing demand of modern wireless communication terminals to handle different standards with a single power amplifier, multi-band multi-mode PAs are urgently needed. To date, several methods for achieving multiple band coverage in the transmitter have been proposed in literature. Basically, present multi-band PA implementations can be divided into several types multi-band PAs based on switches, those based on diplexers, and those based on electronically tunable elements. Figure 4.1 presents the block diagram of a.4 GHz/5. GHz CMOS PA for dual-band applications. This dual-band selection is realized by using a NMOS SPDT (Single Pole Double Throw) band switch. At.4 GHz and 5. GHz bands, the achieved saturated output power are 9.7 dbm and 19.5 dbm, respectively. The PAE (Power Added Efficiency) at 5. GHz is 15.3%. Figure 4.1: Block diagram of a dual-band PA based on band switch (Courtesy of E. Yun Seong and. Kwang Du) Figure 4. illustrates an 800/1500 MHz 1 watt-class GaAs FET amplifier. In this implementation, the band selection is realized by using the two-frequency lumped-element 69

80 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier matching circuits which is designed based on the low-pass Chebyshev-form impedance transformer design method. This dual-band PA exhibits the saturated output powers of 30.9 dbm and 8. dbm with the PAE of 51.6% and 51.9% at 800 MHz and 1500 MHz, respectively. Figure 4.: Configuration of a dual-band PA (Courtesy of K. Uchita et al.) Figure 4.3 shows a.4/5 GHz dual-band PA module realized by using diplexer-matching. This dual-band PA exhibits an output power 0 dbm at.4 GHz and 18 dbm at 5 GHz with an EVM (Error Vector Magnitude) of 4-5% for a 54-Mbps OFDM (Orthogonal Frequency- Division Multiplexing) signal. Figure 4.3: Block diagram of a.4/5 GHz diplexer-matching PA module (Courtesy of K. Kunihiro et al.) In these multi-band PA implementations, various band selection approaches are employed such as switches, diplexers, and resonators. Each of these approaches has some disadvantages. E.g. for multi-band PAs based on switches or diplexers, the drawbacks caused by the additional band selection circuits are apparent the PA being less compact and high cost. Moreover, many of these solutions to multi-band applications are unable to provide concurrent operation because of the fact that a change in transmitting frequency requires adjustment of tunable components, change of connection to different matching network, or even between different modules. In order to solve these problems, new approaches for 70

81 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier implementing multi-band PAs are needed. 4. Proposals for implementing multi-band Chireix s amplifiers The key to implementation of multi-band Chireix s outphasing amplifiers is finding a suitable band selection approach that can be employed in Chireix s outphasing operation. For this purpose, here we propose two approaches for implementing dual-band Chireix s outphasing amplifiers. Idealized voltage sources (to model active devices) and idealized components are used to realize an idealized Chireix s outphasing operation to test the feasibility of these two approaches for dual-band application Dual-band Chireix s amplifier based on resonators The first idea for realizing dual band selection is based on the use of resonators. The circuit schematic used to check the feasibility of this approach is shown in Figure 4.4. These resonators, which are composed of ideal capacitors and inductors, are used to realize shorts and open circuits for the dual bands.14/4.8 GHz. oad compensation components of the Chireix s outphasing operation are realized by ideal admittance equations. Figure 4.4: A dual-band Chireix s amplifier model based on resonators Because the active devices are modeled by ideal voltage sources, according to (Equation.30, the efficiency of this idealized Chireix s outphasing system equals the cosine of the 71

82 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier phase of the varying admittance seen by each device. Because admittance is the ratio of current to voltage, the phase of the admittance is equal to the phase difference between current and voltage. Therefore, alternatively, the efficiency can also be calculated by the following method. First, the in-phase input power of each branch is calculated which does not include the phase relationship between current and voltage. P = 0.5 I V P = 0.5 I V (Equation 4.1) Then, the normal output power of the system is calculated which includes the currentvoltage phase difference. P * { } = 0.5 real I V (Equation 4.) out o o The ratio of the sum of these two input in-phase power to the output power is then equal to the efficiency of the idealized Chireix s outphasing system. P out η = P + P (Equation 4.3) 1 If the transmission efficiency of the power combiner is η pc, which is defined as the ratio of the output power of the power combiner to the sum of the input powers at each branch of the power combiner, then the output power can be expressed by * * { } { } P = ( P + P ) η = (0.5 real I V real I V ) η out rf 1 rf pc 1 1 pc = 0.5 I1 V1 cos( θ) 0.5 I V cos( θ) + η = (0.5 I V I V ) cos( θ) η = ( P + P) cos( θ) η pc pc pc (Equation 4.4) Where θ is the phase difference between current and voltage at any branch. Then, the efficiency can be expressed by η Pout = = cos( ) P P θ + η 1 pc (Equation 4.5) In our idealized dual-band Chireix s outphasing amplifier, all components of the power combiner are idealized and therefore there is no loss in the power combiner. As a result, the 7

83 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier transmission efficiency of the power combiner is unity. Apparently, this total efficiency is equivalent to the cosine of the phase difference between current and voltage, i.e. the cosine of the phase of the admittance. However, if there is some loss in the circuit, the above efficiency also includes the transmission efficiency of the power combiner. This definition of efficiency is more accurate, and therefore is used in the simulation of the dual-band Chireix s outphasing amplifier. The simulation results are shown in Figure 4.5. (a) fundamental frequency (b) double frequency Figure 4.5: Simulation results of the dual-band Chireix s outphasing amplifier based on resonators; (a) at the fundamental frequency (b) at double frequency 73

84 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier The simulated efficiency curves agree with the theoretical results derived in Chapter very well, which shows that the designed resonators have realized good isolation and connection at corresponding frequencies so that this Chireix s outphasing amplifier functions well both at the fundamental frequency and at the double frequency. In the simulation results, current and voltage values have been provided to show the functioning of these resonators. 4.. Dual-band Chireix s amplifier based on transmission lines The second idea for realizing dual band selection is based on the use of special transmission lines such as λ/4 lines and λ/8 lines. The circuit schematic used to check the feasibility of this approach is shown in Figure 4.6. (a) Circuit schematic (b) Isolation and connection network realized by special transmission lines 74

85 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier (c) simulation results at the fundamental frequency (d) Simulation results at the double frequency Figure 4.6: A dual-band Chireix s outphasing amplifier model based on special transmission lines (a), (b) circuit schematic (c), (d) simulation results The calculation of the efficiency has followed the same definition as that in Section These simulated output power curves and efficiency curves show that this dual-band Chireix s outphasing amplifier functions well both at the fundamental frequency and at the double frequency. This dual-band realization based on special transmission lines has an advantage over the one based on resonators. Provided that the active devices that can operate 75

86 Chapter 4. Potential solutions to multi-band Chireix s/inc amplifier at both bands are available, this dual-band Chireix s outphasing amplifier is able to concurrently operate at the dual bands, saving the need of band-switches. 4.3 Summary Several present multi-band PA implementations have been reviewed so that some inspiration can be obtained for implementing multi-band Chireix s outphasing amplifiers. Two ideas for how to realize dual-band Chireix s amplifier have been proposed. One realization of dual-band Chireix s outphasing amplifier is based on resonators. This dualband realization still needs some kind of band-switch to realize band-selection. Another dualband Chireix s outphasing amplifier is based on using special transmission lines. The advantage of the second realization is that it can concurrently operate at the dual bands without using additional band-selection components, provided the active devices that can simultaneously operate at dual bands are available. Circuit schematic and simulation results of both dual-band realizations have been provided to show their functionality. 76

87 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS Chapter 5 Efficiency comparison under static load modulation between GaN HEMT and DMOS 5.1 Research motivation For an active device in (linear) class-b operation mode, the best efficiency at the maximum output power (i.e. the output power rating of the device) can be achieved only at a particular load, which is usually referred to as the optimum load. The optimum load consists of two parts the real part (the optimum conductance) and the imaginary part (the optimum susceptance). With the optimum susceptance compensating the output capacitance of the active device, the optimum conductance determines the relationship between the output voltage swing and the current swing at the load and thereby the efficiency. As mentioned before, for a linear class-b operation, the optimum conductance can be determined by the load-line equation: R V dc opt = I / (Equation 5.1) max At such optimum conductance, a maximum unclipped (linear amplification) voltage swing is generated by the maximum current swing (the fundamental component of the drain current). Therefore, a maximum output power is achieved for a proper input power that induces the maximum current swing, and so is the optimum efficiency for a certain dc supply. In some applications, signals with a varying envelope need to be amplified. When the input power decreases, with an ideal strongly nonlinear trans-conductive model assumed (which has a perfectly linear region between the cutoff and saturation points), the induced drain current will drop in proportion to the envelope of the input signal. If the load is still fixed at the optimum conductance for the maximum output power, the output voltage swing generated at the load will shrink proportionally. By contrast, for the dc components, although 77

88 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS the dc current also goes down with the input power, the dc voltage still remains at the dc supply. As a result, the output RF power drops more rapidly than does the dc power, which means sharp degradation of the efficiency. In order to avoid the decline of the efficiency, the real part of the load can be accordingly modulated (more specifically, the conductance should be reduced proportionally while the susceptance remains fixed) so that the maximum output voltage swing (double of the dc supply voltage for class-b operation) is restored. For an idealized device in class-b operation, the optimum efficiency at the maximum output power should be completely restored at an output power backed off. For an actual device, however, the original efficiency cannot be fully restored due to device nonlinearity, device parasitics, and other factors. Yet the efficiency can still be improved significantly by load modulation. Such efficiency performance under load modulation is of great importance in some applications such as Chireix s/inc amplifiers and Doherty amplifiers. The efficiency performance under load modulation differs in various types of active devices that have different prices. Performance price ratio is important for commercial applications of these active devices. As a more expensive active device, GaN HEMT should, arguably, show better efficiency under load modulation than the cheaper DMOS. This chapter is devoted to a comparison of the simulated efficiency under load modulation between GaN HEMT and DMOS. The research goal is to find out whether GaN HEMT really outperforms DMOS under load modulation and if it does, how much. Based on the results of this research, a better choice of active device in commercial applications can be made. 5. Device models For GaN HEMT, we use the 45-watt die model CGH40060D delivered by CREE and the corresponding package parasitics network (same as used in the design of Chireix s outphasing amplifier, see Figure 3.3) to simulate the efficiency under static load modulation. For DMOS, a 45-watt package model NXP_BF6G_45_V1p0ii provided by NXP is used in the simulation. This DMOS package model includes the bare die device as well as the package parasitics. The symbol schematic of NXP_BF6G_45_V1p0ii is shown in Figure 5.1. One special feature of this model is that extra pins are provided so that model users can easily access the internal gate, drain, and source of the device. According to the user guidelines of this model, these extra pins can only be connected to probe components or be 78

89 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS connected short-circuited, but nothing more is recommended. Figure 5.1: A 45-watt DMOS package model (Courtesy of NXP) 5.3 Simulation procedures of static load modulation The static load modulation simulation is carried out for each model in the following procedures. (1) Determine the biases and estimate the input power (actually the available power from source P avs ) and the optimum conductance at the internal drain (G opt ) for the maximum output power (P max ). In a class-b operation mode, the gate of the active device should be biased at the pinchoff voltage. The drain bias is provided by a 8-volt dc supply for both models. The P avs needed for P max can be estimated by using the output power rating and the power gain in the data sheet of the device model. The optimum conductance at the internal drain can be estimated by using the loadline equation: G I V max Imax / dc Pmax opt = = = (Equation 5.) Vdc Vdc Vdc () Based the estimation of P avs and G opt, proper harmonic termination that can achieve good class-b waveforms are determined both at the internal gate and at the internal drain. 79

90 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS To achieve a class-b operation mode, besides proper biases, proper harmonic termination both at the input and at the output are also needed. For an idealized device, in order to achieve a class-b operation, whose features involve a perfect sinusoidal drain voltage waveform and a halfwave-rectified sinewave drain current, all higher harmonics should be shorted both at the internal gate and at the internal drain. For actual devices, however, things are somewhat different. First of all, because of package parasitics, sometimes it is impractical to provide perfect harmonic short at the internal gate and the internal drain. In practice, we can only provide harmonic short as perfect as possible by tuning the source impedances and the load impedances outside the package because the internal pins of the actual device are inaccessible. Second, even if we can provide nearly perfect short for all the higher harmonics at the internal gate, this does not necessarily lead to a good class-b drain current waveform. The reason is that due to device nonlinearity, in order to achieve a good halfwave-rectified sinewave drain current, some harmonics need to be provided at the internal gate. Therefore, in our simulation, nearly perfect harmonic short is provided at the internal drain, which ensures a perfect sinusoidal drain voltage waveform; at the internal gate, instead providing harmonic short, we tune the harmonic termination until the drain current waveform looks as close to a class-b waveform (a perfect halfwaverectified sinewave) as possible. Before tuning the harmonic termination, an input conjugate match at fundamental frequency should be realized so that the actual input power is approximately equal to P avs. When tuning the harmonic termination, we also need to ensure that the active device is not overdriven because we want to base the comparison on a linear class-b operation, not an overdriven one. Whether the device is overdriven or not can be discovered by checking the swing of the drain voltage. If the device is overdriven, the amplitude of the drain voltage will be larger than the dc supply voltage. In that case, P avs needs to be reduced accordingly so that the device is not overdriven. With a proper P avs, proper harmonic termination, and a proper load conductance, the efficiency and the output power should be comparable to the optimum values, at least not much lower than the optimum values. (3) Based on the input match and the harmonic termination determined previously, loadpull simulations are performed at several different P avs levels to determine the best P avs and the optimum internal load (seen by the internal drain) for the optimum efficiency at the maximum output power in a linear class-b operation. (4) Estimate the P avs level required for each output power back-off level. Under the 80

91 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS optimum load condition, a P out -P avs characteristic curve can be plotted by sweeping P avs. The P avs level required by a particular output power back-off can be estimated by this characteristic. (5) Based on the estimate of the P avs levels, P avs is reduced and the conductance of the load is accordingly modulated while the susceptance is kept unchanged so that a particular target output power back-off is achieved. Tune the conductance and adjust the source power until an optimum efficiency is obtained at the target output power. Alternatively, a load-pull simulation can be performed at the estimated P avs to determine the optimum load for the optimum efficiency at the target output power. Two approaches, tuning and load-pull simulation are equivalent in principle. No matter which approach is adopted, special attention needs to be paid on ensuring that the device is not overdriven. (6) Repeat step (5) until enough simulated data points are obtained to plot the efficiency as a function of the output power back-off into a smooth curve. Because the load conductance is modulated point by point at each output power back-off level, not continuously or dynamically, this kind of load modulation is referred to as static load modulation. 5.4 GaN HEMT 45-watt model Harmonic termination The biases of the GaN HEMT 45-watt device are identical to those used in the Chireix s outphasing amplifier design. From the data sheet of the GaN HEMT 45-watt model, we know that this device has an output power rating of 45 watts (or 46.6 dbm) and a power gain of about 10 db. Therefore, an estimate of the input power for the maximum output power is about 36 dbm. An estimate of the optimum conductance at the internal drain can be calculated by using the loadline equation: G opt P 45 = = = (Equation 5.3) V max dc 8 The circuit used for tuning harmonic termination is shown in Figure 5.. At the input, variable Zsource provides the source impedance of the power source at the fundamental frequency while impedance array Z_s provides all the higher harmonic impedance. Impedance array Z_series is used to ensure that Zsource functions only at the fundamental frequency. At the output, reflection coefficient array oadtuner provides the fundamental load as well as the loads at all the higher harmonics. Variable SourceRX and oadrx are 81

92 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS used to tune the harmonic termination at the input and at the output. Besides the common components used for load-pull simulation (HB1, Sweep1, SweepEquations, and ImpedanceEquations), an additional reflection coefficient array oadtuner0 is used to set the optimum load (S11_opt) and an additional harmonic balance component HB0 is used to simulate the performance at such optimum load. A large signal S-parameter component HB is used to check the input conjugate matching. Figure 5.: Circuit schematic for the static load modulation of GaN model The simulation results are shown in Figure 5.3. Nearly perfect harmonic short has been provided at the internal drain. As a result, the drain voltage is a perfect sinusoidal waveform that has an amplitude about 7.6 volts (under 8 V), meaning the device is not overdriven. In 8

93 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS order to ensure the device is not overdriven, the source power has been reduced to dbm and the load conductance has been increased to The actual output power at the internal drain is about 45.8 watts, slightly higher than the output power rating of the device because the package parasitics cause some loss. It can be seen that the relationship between the actual output power and the actual drain voltage amplitude agrees with the loadline equation pretty well: G opt P 45.8 = = = 0.10 (Equation 5.4) V drain drain 7.6 Because the waveform of the drain current is far from a halfwave-rectified sinewave, only by checking the drain current waveform, it is difficult to determine when the harmonic termination is good enough. So, in practice, after we have achieved nearly perfect harmonic short at the internal drain, we tune the harmonic termination at the internal gate until the best attainable efficiency at the maximum output power is obtained. Figure 5.3: GaN model simulation results of harmonic termination tuning 5.4. Optimum load Based on the harmonic termination determined from above, load-pull simulations are performed at several different P avs to find the best P avs and the optimum load for the maximum output power. The circuit used in the load-pull simulation is identical to that in 83

94 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS Figure 5.. The simulation result of the optimum load is shown in Figure 5.4. The efficiency at the optimum load is slightly better than the one obtained previously. Figure 5.4: GaN model simulation results at the optimum load for maximum output power One thing needs to be explained here is that the susceptance in the optimum load for the maximum output power is not necessarily an optimum one for the static load modulation. In the static load modulation, the susceptance of the load is kept fixed while the load conductance is modulated to improve the efficiency at each output power back-off level. The precondition of static load modulation is the load susceptance can fully compensate the output capacitance of the active device so that it can be fixed when the load conductance is modulated. Such susceptance can be regarded as an optimum susceptance for the whole output power back-off range and its accuracy is key to the success of the static load modulation. However, the susceptance in the optimum load found from load-pull simulation is not necessarily the optimum one for static load modulation. To obtain a more accurate value of such optimum susceptance, load-pull simulations can be performed at several output power back-off levels to find the optimum load for the best efficiency. The susceptance of the resulting loads should be approximately constant, which can be used as a more accurate estimate of the optimum susceptance for the static load modulation. If such optimum susceptance is used at the maximum output power, the efficiency will 84

95 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS be lower than the optimum one obtained at the optimum load obtain from load-pull simulation because the load deviates from the optimum load. Then the load conductance can be adjusted so that an efficiency as close to the optimum one as possible is achieved. This final combination of the optimum susceptance for static load modulation and the adjusted conductance, i.e. the final load admittance, can be regarded as an optimum one for the static load modulation. At this optimum load, the simulated result is shown in Figure 5.5. Figure 5.5: GaN model simulation results at the optimum load for static load modulation At such optimum load, the P avs is swept to achieve a P out -P avs characteristic, based on which an estimate of P avs needed for a certain output power back-off level can be made. This P out -P avs characteristic is presented in Figure 5.6. Also, a curve of the efficiency as the function of the output power back-off is presented in the same figure. 85

96 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS Static load modulation Figure 5.6: P out -P avs characteristic of GaN model and efficiency versus output power without load modulation Based on the P out -P avs characteristic, static load modulation is carried out for the GaN model. The circuit used in static load modulation is the same as shown in Figure 5.. The simulation results are shown in Table 5.1 and Figure 5.7. In the static load modulation, 10 output power back-off levels, from -1 db to -10 db, have been simulated. P in is the real input power, which remains close to P avs in the whole output power back-off range, meaning a good input conjugate match has been realized. S11 opt is the reflection coefficient of the fundamental load at the output whereas Y d is the load admittance seen by the internal drain. In the simulation, we tune S11 opt to achieve the required Y d. V d [1] is the fundamental component of the voltage at the internal drain, which can indicate whether the device is overdriven or not. As can be seen from the comparison between the efficiency in the static load modulation and non-modulation, load modulation can significantly improve the efficiency of this GaN device when the output power backs off. Table 5.1: Simulation data of static load modulation for GaN model P out (dbm) P avs (dbm) P in (dbm) Efficiency (%) S11 opt Y d (S) V d [1] (V) j* j* j* j* j* j* j* j* j* j* j* j*

97 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS j* j* j* j* j* j* j* j* j* j* Figure 5.7: Static load modulation result of GaN model (Red curve, blue one is the efficiency without load modulation) 5.5 DMOS 45-watt model For the DMOS 45-watt model, the procedure of static load modulation is almost the same as that for GaN HEMT model. Therefore, detailed procedure description will be omitted here. Instead, key steps and important results are provided in the following sections Harmonic termination From the DC simulation, we found the pinch-off voltage of the DMOS 45-watt device is about.0 volts. So the gate is biased at.0 volts. The drain of the device is also biased at 8 volts. From the data sheet of the DMOS 45-watt model, we know that this device has an output power rating of 45 watts (or 46.6 dbm) and a power gain of about 18 db. Therefore, an estimate of the input power for the maximum output power is about 8.6 dbm. An estimate of the optimum conductance at the internal drain can be calculated by using the loadline equation: G opt P 45 = = = (Equation 5.5) V max dc 8 87

98 Chapter 5. Efficiency comparison under static load modulation between GaN HEMT and DMOS The circuit used for tuning harmonic termination is shown in Figure 5.8. Figure 5.8: Circuit schematic for the static load modulation of DMOS model 5.5. Optimum load The circuit used in the load-pull simulation is identical to that in Figure 5.8. The simulation result at the optimum load is shown in Figure 5.9. Figure 5.9: DMOS model simulation results at the optimum load for maximum output power 88