ECE 598 JS Introduction

Transcription

1 ECE 598 JS Introduction Spring 2012 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois 1

2 Future System Needs and Functions Auto Digital Wireless MEMS Consumer 2.5 Limits of Optical Analog, RF Computer 2 Log (Capacity Gb/s) A High bandwidth High-speed Digital 2

3 Demand in the Information Age Activities at home * Telecommuting / home * Teleshopping / home banking * Home medical and health care Pursuing comfortable labor * Remote and mobile offices * Remote control, unattended factory * Collaboration environment Information-oriented living * Shopping / events / traffics * Pastime / learning / sightseeing * Administrative services for residents Voice 64 kbps Documents and drawings 128 kbps 3D-CG 1 Mbps HD still images 1 Mbps Video images 1 Mbps NTSC images 6 Mbps HDTV images 26 Mbps Required media and the amount of information 100 Mbps per home 3 Source: ITRCS

4 PCI PC Interface For external cards Graphics, Network, Sound, etc Parallel 4

5 PCI Express Computer Expansion Card Standard Replaced older PCI Based on serial links Capacity up to 1 Gb/s V3.0 scheduled for

6 Universal Serial Bus (USB) Interfaces devices to computers No rebooting Low power No need for external power supply 480 Mb/s 6

7 IDE Expansion Card Standard Replaced older PCI Based on serial links Capacity up to 1 Gb/s V3.0 scheduled for

8 Serial ATA Storage interface Replaces older parallel ATA or IDE Based on serial links Capacity up to 3 Gb/s Hot swapping capability 8

9 Computer Interconnections 9

10 Motherboards and Backplanes 10

11 Cables and Transmission Lines coaxial twisted pairs 11

12 Cable Specifications 12

13 Measurements VNA: S-parameter Spectrum Analyzer Time-domain simulation Eye diagram 13

14 Semiconductor Technology Trends Chip size (mm 2 ) Number of transistors (million) Interconnect width (nm) Total interconnect length (km)

15 Signal Delay Trend gates delay Signal Delay interconnect delay Delay for Metal 1 and Global Wiring versus Feature Size Global Wiring w/o Repeaters Global Wiring w Repeaters Local Wiring Gate Delay Source: ITRS roadmap

16 The Interconnect Bottleneck Delay (ps) SPEED/PERFORMANCE ISSUE Gate Delay Sum of Delays, Al & SiO2 Sum of Delays, Cu & Low K Interconnect Delay, Al & SiO2 Interconnect Delay, Cu & Low K Gate Gate wi Al & SiO2 Al 3.0 μω -cm Cu 1.7 μω -cm SiO2 κ = 4.0 Low κ κ = 2.0 Al & Cu.8μ Thick Al & Cu Line 43μ Long Generation (nm) 16

17 MOS Technology Trends 17

18 Interconnect Total interconnect length (m/cm 2 ) active wiring only, excluding global levels will increases: Year Total Length Interconnect power dissipation is more than 50% of the total dynamic power consumption in 130nm and will become dominant in future technology nodes Interconnect centric design flows have been adopted to reduce the length of the critical signal path 18

19 5 Layer Interconnect Technology 0.25 μm Vertical parallel-plate capacitance 0.05 ff/μm 2 Vertical parallel-plate capacitance (min width) 0.03 ff/μm Vertical fringing capacitance (each side) 0.01 ff/μm Horizontal coupling capacitance (each side) 0.03 Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March

20 Integrated Circuit Wiring Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Substrate Vertical parallel-plate capacitance 0.05 ff/μm 2 Vertical parallel-plate capacitance (min width) 0.03 ff/μm Vertical fringing capacitance (each side) 0.01 ff/μm Horizontal coupling capacitance (each side)

21 Chip Level Interconnect Delay Line Pulse Characteristics: rise time: 100 ps fall time: 100 ps pulse width: 4ns Line Characteristics length : 3 mm near end termination: 50 Ω far end termination 65 Ω 1 Near End Response 0.7 Far End Response Volts Board VLSI Submicron Deep Submicron Logic threshold Volts Board VLSI Submicron Deep Submicron Logic threshold Time (ns) Time (ns) 21

22 Package Level Complexity - Up to 16 layers - Hundreds of vias - Thousands of TLs - High density - Nonuniformity ECE 598 JS, Spring 2012 Copyright by Jose E. Schutt Aine, All Rights Reserved 22

23 Signal Integrity Ideal Transmission Channel Common Transmission Channel Noisy Transmission Channel 23

24 Signal Integrity Crosstalk Dispersion Attenuation Reflection Distortion Loss Delta I Noise Ground Bounce Radiation Drive Line Sense Line Drive Line 24

25 IC on Package 25

26 Mixed Signal Noise Analog Power bus Interconnect Digital Power bus Interconnect coupled noise Substrate Chip-package interconnect bond Inductance Simultaneous switching and inductance (L eff ) L eff is f( current magnitude and direction) Interactions between noise generated by power/ground and signal paths GND 26

27 Power Supply Noise - Power-supply-level fluctuations - Delta-I noise - Simultaneous switching noise (SSN) - Ground bounce VOH VOL Ideal Vout Actual Vout Time 27

28 Power Distribution Problem Gate A Output voltage from Gate A + V 1 - Low Frequency Wire B N GROUND CONNECTION Differential voltage at receiver V 1 - R + V 1 - Gate C R + - Internal reference generator Gate A Output voltage from Gate A + V 1 - High Frequency GROUND CONNECTION Wire B - N + Equivalent noise source in series with ground connection Differential voltage at receiver V 2 - N - R + V 2 - Gate C R + - Internal reference generator At high frequencies, Wire B is a transmission line and ground connection is no longer the reference voltage 28

29 On Chip Power and Ground Distribution Distribution Network for Peripheral Bonding Power and ground are brought onto the chip via bond pads located along the four edges Metal buses provide routing from the edges to the remainder of the chip Local Buses GND VP Bus GND Bus VP Bus GND Bus VP Bus Wiring Tracks VP GND Bus VP Bus GND Bus VP Bus 29

30 Dual in Line (DIP) Package -Mounted on PWB in pin-through-hole (PTH) configuration - Chip occupies less than 20% of total space - Lead frame with large inductance 30

31 Packages & Packaging Trends Quad Flat Pack Thermal Package MCM 31

32 Stacked Wire Bonds 32

33 Ceramic Substrate 33

34 Area Bonding with Flip Chip Bumped Die Package Body Pins Minimizes IR drops between gates Minimizes interconnection inductance 34

35 Tools for Physical Design * Schematic editor * Circuit level simulator * Layout editor * Placement & routing * Design rule checker * Netlist extractor * Layout vs Schematic * Libraries * Design verification * Electromagnetic analysis 35

36 State of the Art in Extraction CAPACITANCE * MoM- BEM * FEM * Fast Multipole INDUCTANCE * MoM- BEM (2D) * FEM (2D) * PEEC (3D) * Fast Multipole Main Challenge: 3D inductance extraction is computationally expensive. 36

37 Circuit Simulation Board/Module Chip Y(t) v(t) = I(t) Given, Y and I, find v * SPICE * Asymptotic Waveform Evaluation * Complex Frequency Hopping * Passive Multipoint Matching Method * Latency Insertion Method 37

38 Why SPICE? Established platform Powerful engine Source code available for free Extensive libraries of devices New device installation procedure straightforward 38

39 SPICE From Netlist Parser Device Stamp I=YV To Solver spice3f4 conf examples lib man notes patches src tmp util doc helpdir scripts man1 man3 man5 bin include lib unsuppo lib skeleton ckt cp dev fte hlp inp mfb mfbpc misc ni sparse mac asrc bjt bsim1 bsim2 cap cccs ccvs csw dio disto ind isrc jfet ltra mes mos1 mos2 mos3 mos6 res sw tra urc vccs vcvs vsrc Directory Structure 39

40 Interconnect Simulation Application New Interconnects: 3D Interconnect (System In Package) package-intermediated interconnects Chip-Package-Board Co-Design Power Ground Network: It will greatly affect the performance of the chip design: Voltage (IR) drops on VDD nets ground bounce on VSS nets High currents in the power grids Electromigration effect Power Ground Network Design 40

41 Chip Package Co Design Repeated Simulation of the Package/Board Super Fast Simulation Source: Joel Mcgrath, Chip/package co-design: The bridge between chips and systems, Advanced Packaging Magazine June,

42 Power Ground Network Design Flow Repeated Simulation of the P/G network Super Fast Simulation 42

43 Deep Submicron Timing Closure requirements specification behavioral representation structural representation structural representation physical representation Design Specification Functional Design Logic Design Circuit Design Physical Design functional simulation logic simulation circuit analysis extraction and verification Unbounded design iterations resulting from unpredicted timing violations microns and lower - 2 to 20 iterations - mismatch between logic and physical designs - greater timing variations - dominated by interconnects - inductive and capacitive coupling - slows time-to-market fabrication 43

44 Example: Power Bus/Ground Plane Model Unit cell = Modeling - Determine R,L,G,C parameters and define cell - Synthesize 2-D circuit model for ground plane - Use SPICE to simulate transient Typical workstation simulation time for a 1200-cell network is 2 h 40 min. Too time consuming! Y cells X cells 44

45 Model Order Reduction Large Network (>1,000 nodes) Reduced Order Model (< 30 poles) * AWE SPICE Y(t) v(t) = i(t) MOR Schemes * Padé via Lanczos * Complex frequency hopping * Direct rational approximation Y(ω) V(ω) = I(ω) Order Reduction Y(ω) = ~ Y(ω) ~ Recursive Convolution ~ Y(t) v(t) = i(t) 45