3 Hints for application

Transcription

1 Parasitic turnon of the MOSFET channel at V GS = 0 V over C GD will reduce dv DS /dt during blocking state and will weaken the dangerous effect of bipolar transistor turnon (see Figure 3.35). Control current ratings, driving power The total driving power P Gavg to be delivered by the driver circuit can be determined from the gate charge Q Gtot (see Figure 1.12 and Figure 1.13): P Gavg ( VGG+ + VGG ) Q Gtot f s with QGtot = CEquiv. ( VGG+ + VGG ) = Peak gate current values are calculated as follows: I I GMon GMoff ( V + GG+ VGG )/ R Gon = (ideal) ( V + GG+ VGG )/ R Goff = (ideal) Driver power is calculated as follows: P P ( VGG ) = VGG+ QGtot f s + f s = switching frequency ( VGG ) = VGG QGtot f s Example: Resulting in: V GG+ = 15 V, V GG = 15 V, R G = 3.3 Ω Q Gtot = 2.3 µc (SKM500GB123DS) f s = 10 khz, V DC = 600 V I GMon = I GMoff = 9.09 A P Gavg = 0.69 W P( VGG + ) = P( VGG ) = W I( VGG + ) = I( VGG ) = 23 ma (average) Influence of driver parameters on switching features As already mentioned, important features of driven power MOSFETs or IGBTs are dependent on V GG+, V GG and R G ratings. The following table shall give a first overview (: increases, decreases, : remains): Rating/ characteristic V GG+ V GG R G see chapter R DS(on), V CEsat t on, E on t off E off turnon peak current * ) turnoff peak voltage * ) dv/dtsensitivity (MOSFET) ( IGBT) actively limited I D, I C ruggedness to load shortcircuits * ) during hard switching under ohmicinductive load

2 Forward characteristics (R DS(on), V CEsat ) The dependences of the forward characteristics of power MOSFETs and IGBTs on the drive parameters can be read from their output characteristics (see chapter 1.2.2). In Figure 3.36 this is explained with one example each for SEMITRANSMOSFETs and IGBTs taken from the current datasheets. a) b) Figure 3.36 Forward characteristics versus control voltage (gate voltage) a) Power MOSFETmodule SKM 111 b) IGBTmodule SKM100GB123D In SEMITRANS, SEMITOP and MiniSKiiP datasheets the recommended maximum ratings and characteristic values mentioned in chapter are indicated with V GG+ = 10 V for power MOSFETs and V GG+ = 15 V for IGBT modules which is an acceptable compromise in conventional applications between power dissipations, turnon peak current and shortcircuit behaviour. Switching times, switching losses (t on, t off, E on, E off ) Control voltages and gate resistances will affect the various parts of turnon time t on = t d(on) + t r, turnoff time t off = t d(off) + t f and tail time t t of the IGBT in different ways: Since the gate capacitance amounts to absolute ratings of V GG+ and V GG before switching, the recharge time will decrease (turnon delay time t d(on), turnoff delay time t d(off) ) on condition of a given gate resistor R G if the recharge current or (V GG+ + V GG ) increases. On the other hand, switching times t r and t f and, consequently, energy dissipations E on and E off may only be affected by the switching control voltages V GG+ or V GG, since they determine the current flow through the gate resistor R G. SEMITRANSIGBT datasheets include diagrams showing the dependences of switching times and energy dissipations on R G, measured for maximum current ratings I 80 C on condition of hard switching under ohmicinductive load (Figure 3.37). 182

3 a) b) Figure 3.37 IGBTswitching times (a) and switching losses (b) of SKM100GB123D versus gate resistor R G at T j = 125 C, V CE = 600 V, I C = 75 A, V GE = ± 15 V and on condition of hard switching under ohmicinductive load Switching behaviour of freewheeling diode and turnon peak current of transistor The turnon energy dissipation of the IGBT indicated in Figure 3.37b already includes the influence of the turnoff behaviour of the integrated freewheeling diode on turnon peak current and turnon power dissipations, see chapters and a) b) Figure 3.38 SKM100GB123D CALdiode recovered charge Q rr (a) and peak reverse recovery current I RRM (b) versus commutation speed di F /dt of diode current The drain or collector current (i D, i C ) rise time t r will decrease with rising gate current (higher V GG+ or lower R G ). This in turn will increase the current commutation speed di F /dt in the free 183

4 wheeling diode, by which recovered charge Q rr and peak reverse recovery current I RRM are determined. These characteristics of CALdiodes used in SEMITRANSIGBTmodules are depicted in the datasheets (Figure 3.38 and 3.39). Increase of Q rr and I RRM will cause higher turnoff power dissipations in the internal freewheeling diode. Since a higher di F /dt will result in an increase of Q rr and I RRM and, since I RRM is added to the load current within the collector or drain current, turnon peak current and turnon energy dissipation of the transistor will increase with its turnon speed (Figure 3.37). Figure 3.39 CALdiode turnoff energy dissipation E offd in a SEMITRANS IGBTmodule SKM100GB123D versus R G Turnoff peak voltage If either V GG is increased or R G is decreased, the turnoff gate current of the driven transistor will rise. As shown in Figure 3.37a, the drain or collectorcurrent fall time t f will decrease, i.e. di D /dt or di C /dt will increase. The voltage u = L σ * di/dt induced during di/dt over the parasitic commutation circuit inductance L σ will increase linear to the decreasing turnoff time Driver circuit structures and basic requirements on drivers Figure 3.40 shows the basic structure of a comfortable driver circuit for one MOSFET or IGBTbridge arm with TOP/BOTTOM interlock and protection functions close to the gate. In the depicted driver, TOP and BOTTOM switches and signal processing unit are separated by real potential isolation for control signals, control power and feedback of output and error signals. In simple driver circuits these potential isolations may be combined (common energy and signal transmission) or they are partly or even completely omitted (e.g. bootstrap circuits for TOP voltage supply). Lowvoltage switches or lowside choppers especially (only BOTTOM switch is active) only require a very simplified driver structure, since single switches can be realized without most interlock and deadtime functions. 184

5 error detect. I C, V DC fast protection S TOP input buffer shaper, shaper Gate protect. S BOTTOM input buffer interlook deadtime & short supression DC/DCConverter V GG+ V GG V GG+ V GG shaper Gate protect. STATE RESET error latch V GG watch fast protection error detect. I C T hmeasur. Galvanic Isolation Figure 3.40 Block diagram of bridge arm driver circuit with TOP/BOTTOM interlock and protection (IGBT driver) The gate unit is the core part of the driver circuit and consists (mostly) of primaryside time control stages for delay, interlock and minimum on and off times (see chapter 3.5.4), potential isolation (with shapers, if necessary) and a generator for positive/negative gate control voltage. The power transistor gate may also be equipped with overvoltage protection, combined with an active clamping for v DS or v CE (see chapter 3.6). Figure 3.41 shows the principle of a generator for positive and negative gate control voltage (designed for IGBTs with negative gateemitter voltage). Apart from the complementary source follower boosters with lowpower MOSFETs, for example, complementary drain or collector followers and totempole drivers with MOSFETs or bipolar transistors are also commonly used [277]. Further solutions including integrated components are referred to in chapter

6 GND V GG+ C R Gon i G R in R Goff R GE V GG C GND GND Figure 3.41 Turnon and turnoff gate voltage generator The gate resistance R G in Figure 3.41 has been divided up into two resistors R Gon and R Goff for turnon and turnoff, respectively. By this means, the mostly inevitable cross current from V GG+ to V GG, generated during switching of the driver MOSFETs, can be limited. The main advantage, however, is that this solution offers the possibility of separate optimization of turnon and turnoff with regard to turnon overcurrent and turnoff overvoltage (see chapter ) and to shortcircuit behaviour (chapter 3.6.2). If only one output is available for R G, this function can also be maintained by paralleling R Gon and R Goff. Diodes connected in series to the resistors should be arranged so that the cathode is directed towards the IGBTgate for R Gon and the anode is directed towards the IGBTgate for R Goff. The gateemitter resistor R GE ( kω) should not be omitted in any application, since it prevents unintentional charging of the gate capacitance even under driver operating conditions with highly resistive output levels (switching, offstate and driver supply voltage breakdown). The lowinductive capacitors C ( µf) serve as a buffer for V GG+ and V GG near the driver output and have to keep up a minimum dynamic internal driver resistance together with the lowresistive driver circuit. Only under these circumstances the driver will be able to absorb displacement currents due to dv CE /dt which are conducted via Miller capacitance to the gate and are likely to cause switching failures, parasitic oscillations or inadmissible gate overvoltages. Moreover, the following aspects have to be considered for the gate voltage generator layout: minimum parasitic inductances in the gate circuit, e.g. short ( 10 cm), twisted connection lines between driver and gate/ driver and emitter; minimum size of circuit arrangement according to Figure 3.41 elimination of feedback of load current to gate voltage caused by the parasitic emitter inductance in the power module: connection of driver ground to the power module control emitter, avoidance of ground loops, avoidance of transformative and capacitive coupling between gate and collector circuit (no paralleling of critical tracks or wires; integration of shielded areas). 186

7 Of course, these requirements also have to be met by the potential isolated supply of the buffer energy (e.g. by a switch mode power supply integrated in the driver) and by all other functional units on the power transistor potential. Lowpass filters, shapers and width triggered flipflops integrated in the signal transmission paths for interference suppression have to live up to the permissible minimum duration and the necessary response times to failures with regard to their delay times Integrated protection and monitoring functions of a driver To protect MOSFET or IGBT modules in case of failure, the implementation of a variety of fast responding and efficient protection functions in the driver is recommended, such as overcurrent and shortcircuit protection, protection from excessive drainsource or collectoremitter voltage, gate overvoltage protection, overtemperature protection and monitoring of gate control voltages V GG+ and V GG. With reference to Figure 3.40, the integration of protection functions in the driver is explained in the following. Realization and dimensioning aspects are dealt with in chapter 3.6. Overcurrent and shortcircuit protection The current signal can be generated as an analogous signal (measured via e.g. shunt, current probe, R DS(on) of the driven power MOSFET or sensesource or senseemittercells) or as a maximum rating excess (desaturation of the IGBT). As soon as an error has been detected by comparing the actual value to a fixed maximum rating, an error memory is set (ERROR status) either already on switch potential or in the case of potentialisolated sensors in the primary circuit of the driver, which will block the power transistors until the RESETsignal is triggered. If the error memory is integrated on the secondary side, its state signal will be transmitted to the primary side by a potentialisolated unit. In the case of integration of potentialisolating highprecision current sensors as for example in SKiiPPACKs and some MiniSKiiPcomponents their output signal may serve as actual value for control loops or for detection of ground currents. Gateovervoltageprotection In contrast to all protection functions described so far, the gate protection has to limit periodicly to the gate voltage without detection of an error which would require turnoff of the power transistors. Therefore, there is no connection to the error memory. More details are described in chapters and Protection from excessive drainsource or collectoremittervoltage Voltage limitation at the main terminals of a power transistor can be realized by the transistor itself (avalancheproof MOSFETs), by passive networks or by an active circuit, which realizes a defined partial turnon of the transistor in case of overvoltage (see chapter 3.6.3). A simple protection, which is not able to detect switching peak voltages and other fast overvoltage peaks, may (option U ) be optionally integrated into the SKiiPPACK driver as a static DC bus voltage monitoring. A quasi potential isolated sensor will indicate the actual DC bus voltage value and transmits it to the main control circuit as analogous actual value and sets the error memory to ERROR as soon as the limit value has been exceeded. Moreover, a brake chopper buffer may protect for example the DClink capacitors in case of load energy feedbacks active loads). 187