Low-inductive inverter concept by 200 A / 1200 V half bridge in an EasyPACK 2B following strip-line design

Transcription

1 Low-inductive inverter concept by 200 A / 1200 V half bridge in an EasyPACK 2B following strip-line design Dr. Christian R. Müller and Dr. Reinhold Bayerer, Infineon Technologies AG, Max-Planck- Straße 5, D Warstein, Germany Abstract A low-inductive inverter concept for a half-bridge power module, based on a strip-line design, is implemented in an EasyPACK 2B. Due to the strip-line design, the module-internal commutation path is reduced significantly and, by building up the power module with minimized parasitic inductances, an improved controllability of the switches is achieved. The optimized design enables the usage of several fast-switching IGBTs and low-loss diodes in parallel. To operate the half-bridge power module in a low-inductive setup, the commutating current is measured by a wire-loop current sensor which does not add inductance to the setup. A comparison of the switching characteristics to standard assemblies in modules and power circuits shows that the new concept outperforms state-of-the-art power modules and makes the advantages of this low-inductive inverter concept clear. 1 Introduction In power electronics, increasing the power density is an ongoing trend which has dominated the development of power semiconductors, e.g. IGBTs, itself and especially of power-semiconductor modules in the past and will also continue in the future [1]. On the one hand, a high power density allows reducing the system costs due to an optimized cost-performance ratio. On the other hand, new challenges come to the fore like the necessities to improve the thermal management, to develop module concepts with reduced parasitics influencing the switching performance, or to apply a more sophisticated gate-driver circuit enhancing the controllability [2]. Especially parasitics, e.g. the stray inductance L σ, can influence the switching behavior of an IGBT and, hence, the system performance significantly. Stray inductances induce an over-voltage peak during the turn-off or can lead to an unintended parasitic turn-on of the upper system in a half bridge if the lower system is switched. Both effects are normally counterbalanced by reducing the switching speed, i.e. by integrating a larger gate resistor R G, or, especially for the latter one, by using a more sophisticated gate-driver circuit with an active Miller clamping. As a result, the cost-performance ratio is downgraded. If stray inductances are distributed asymmetrically in a power module or in an application, a massive current mismatch within the power module itself or even inbetween power modules is possible. The power module or the system within the power module with the highest L σ shows a delayed switching whereas the one with the lowest L σ will overtake almost the entire current for a certain timeframe. This current mismatch leads to unbalanced stress and can lower the lifetime of a power module significantly. In addition, parasitics like L σ can interact with intrinsic parasitics like the chip capacitances and form a resonant circuit. During a switching event, oscillations are induced and electromagnetic interference (EMI) is radiated. To limit this EMI radiation, additional filters are integrated in the system. Therefore, one of the fundamental requirements for future developments in power electronics is to lower the parasitics and provide symmetric designs [3]. As a result, both approaches will limit the device stress and reduce electrical overload on chip level. In this paper, a full-symmetrically designed power module is presented. For the design of the power module, a strip-line concept is used, which allows to lower the internal stray inductance significantly [4]. In this power module, a 200-A half bridge consisting of several 1200-V fastswitching IGBTs in parallel is implemented. It will be shown that the presented power module outperforms state-of-the-art power modules. Due to the high flexibility and modularity of the presented power module, this concept is suitable to realize more complex electronic circuits like H-bridge inverters, 3-phase inverters, or three-level neutral-point-clamped inverters by parallelization or series connection of modules. 2 Implementation of a lowinductive layout in an EasyPACK 2B The low-inductive layout is implemented in an Easy- PACK 2B. For the layout and the internal electric circuit, a structured direct-bonded copper (DBC) substrate with an Al 2 O 3 ceramic is used. The assembly of the power module was realized by standard processes and assembly technologies. Therefore, maximum operating tempera-

2 tures of T vj = 150 C, with the virtual-junction temperature T vj, are feasible. For the interconnection between the power module and the setup, e.g. the printed-circuit board (PCB), the PressFIT-contact technology was integrated and implemented. 2.1 Concept and module design The concept is based on a strip-line design with several chips per system, i.e. IGBTs and free-wheeling diodes, operated in parallel. Main objectives of this concept were, on the one hand, the implementation of a highly symmetric design with very low parasitics. Here, special care was also taken to lower the stray inductances in the gate circuit, which is a basic requirement to provide good controllability of the IGBTs [5]. On the other hand, it was intended to realize a fully flexible and modular design. For this purpose, a 200-A half-bridge module with a maximum blocking voltage of 1200 V per system was designed. Based on this approach, more complex electronic circuits like H-bridge inverters, 3-phase inverters, or three-level neutral-point-clamped inverters can be built up by parallelization or series connection of modules. In the lower part of Figure 1, a drawing of the DBCsubstrate layout is shown. In each system, four 1200-V IGBTs with a nominal collector current I C = 50 A per IGBT are operated in parallel. Four 1200-V emittercontrolled diodes, with a nominal diode current I F = 50 A each, serve as free-wheeling diodes. The pin rows for DC+ and DC- are situated in the middle of the substrate and the distance in-between is minimized. The corresponding commutation path is indicated by the red arrows. Due to the position of the pins for DC+ and DC-, the commutation path is minimized and the current distribution within the power module is fully symmetric. Therefore, the module is optimized in terms of stray inductance. Measurements on L σ provided a module-stray inductance of only 8 nh. This highly symmetric module design allows the integration of fast-switching IGBTs without losing controllability. In combination with diodes which provide reduced recovery losses, the power module is optimized for highspeed switching. Hence, such a low-inductive module design can outperform common power-module designs due to the possibility to use fast-switching devices. 2.2 Comparison of the new power-module concept with a common design To evaluate the performance of this low-inductive module design, the EasyPACK-2B module is compared with a reference module. As reference, the Infineon module FS225R12OE4 with a module-stray inductance of 20 nh was used. The measurements were performed on a conventional setup with an integrated current probe and a setup-stray inductance L σ = 30 nh (see Figure 5b). The DC-link voltage was set to V DC = 600 V. To drive the IGBTs, a gate-emitter voltage V GE = ±15 V was used. The measurements were performed at T vj = 150 C. Figure 1 Top: Picture of the 200 A / 1200 V half-bridge EasyPACK-2B module together with the corresponding pinout. Bottom: Drawing of the DBC-substrate layout. The commutation path within the module is indicated by the red arrows/lines. The upper part of Figure 1 shows the EasyPACK 2B together with the pinout of the half-bridge inverter. The gate signal and the auxiliary emitter of the upper system are connected at G1 and E1, respectively, whereas G2 and E2 are the corresponding contacts for the lower system. It has to be pointed out that, due to symmetry reasons, there are two gate pins for each system, which are connected to the identical gate driver. Figure 2 Comparison of the switching curves of the EasyPACK-2B module (solid line) and the reference module (dotted line) at T vj = 150 C. The measurements were performed for V CEnom = 600 V and I Cnom = 200 A. On the left-hand side of Figure 2, the turn-off waveforms of the EasyPACK-2B module and the reference module are displayed. Due to the di/dt during the turn-off, an over-voltage peak V CEpeak is induced. The over-voltage peak of the EasyPACK-2B module is smaller than for the reference module, although the di/dt of the EasyPACK-

3 2B module is 34 % larger. The right-hand side of Figure 2 shows the turn-on waveforms for both modules. Both modules provide an almost equal di/dt, which leads to the stray-inductance-induced voltage drop on the collectoremitter voltage V CE. This voltage drop is 30 % larger for the reference module, which is in good agreement with the ratio of the effective stray inductances in the measurement for both modules. Figure 4 Comparison of the switching losses versus I C of the EasyPACK-2B module (Easy2B) and the reference module (Ref.) at T vj = 150 C. Inset: RBSOA diagram at T vj = 150 C for both modules. Figure 3 di/dt and V CEpeak versus I C at T vj = 150 C of the EasyPACK-2B module (Easy2B) and the reference module (Ref.). Inset: For the turn-off, -di/dt and dv/dt versus I C at T vj = 150 C of the EasyPACK-2B module (Easy2B) and the reference module (Ref.). The typical behavior of di/dt and V CEpeak versus I C is compared in Figure 3. For both modules, the di/dt during the turn-on increases with raising I C and is almost constant for I C 200 A, which is defined as the nominal module current. V CEpeak of both modules increases monotonically and, for the reference module, V CEpeak is on average 23 % larger than for the EasyPACK-2B module. It has to be pointed out that the di/dt and the dv/dt during turn-off is significantly higher for the EasyPACK-2B module compared to the reference module. The behavior of both parameters versus I C is displayed in the inset of Figure 3. Hence, the smaller V CEpeak indicates clearly the advantages of a low-inductive design, like it is demonstrated for the EasyPACK-2B module, if compared to a common design as for the reference module. Figure 4 shows the switching losses for both modules versus I C. The switching losses, i.e. turn-on E ON, turn-off E OFF, and diode recovery E REC, rise with increasing I C. In comparison to the reference module, the EasyPACK-2B module provides smaller E OFF and E REC independent of I C. In contrast to this, the turn-on losses of the reference module are on average 17 % smaller. The lower E OFF and E REC of the EasyPACK-2B module are directly related to the usage of fast-switching devices, i.e. IGBTs and diodes, which points out one of the clear advantages of the fully-symmetric and low-inductive design. In contrast to this, the low-inductive design leads to an increased E ON. The inset of Figure 4 highlights an additional advantage of the low-inductive design. Although the EasyPACK-2B module provides an up to 45 % higher di/dt during turnoff, the reverse-bias safe-operating area (RBSOA) of the reference module is limited to smaller values of V CE. Hence, the EasyPACK-2B module can be operated at higher V DC without exceeding the maximum blocking voltage of the power semiconductors. E ON E OFF E REC ΣE EasyPACK B module Reference module Table 1 Comparison of the typical switching losses of the EasyPACK-2B module and the reference module for T vj = 150 C and I C = 200 A. In Table 1, the switching losses of both modules are summarized for the operating point. Here, it becomes evident that, although the E ON for the EasyPACK-2B module is raised, the sum of losses, i.e. E ON + E OFF + E REC, is more than 23 % smaller than for the reference module. 3 Improvement of the switching performance by reducing the setup parasitics In power circuits, not only the parasitic inductance of the power module itself is a barrier for the utilization of fastswitching devices. Also the parasitics in the setup influence the system performance significantly. Therefore, it is mandatory to reduce both, the stray inductance of the power module and of the setup.

4 3.1 Low-inductive setup with an integrated current sensor In a conventional setup, which is shown exemplarily in Figure 5b, a current probe is integrated directly in the DC link. On the one hand, this allows measuring the device currents. On the other hand, an additional stray inductance is implemented in the setup due to a forced constriction of the current distribution by the sensor design. As a first estimation and without considering coupling effects, such a constriction of the current distribution increases the setup-stray inductance by a value of ΔL σ 8 nh (based on the typical design parameters of a standard current sensor). In addition with parasitic inductances which originate from the DC-link capacitors, a conventional setup provides a typical stray inductance of approximately 30 nh and, thus, influences the switching characteristics of fast-switching devices significantly. 3.2 Operating principle of the wire-loop current sensor The operating principle of the wire-loop current sensor is based on the fact that, according to Faraday s law of induction, a time-variant magnetic field B/ t induces a voltage V ind in a conductor loop. The induced voltage is approximately given by V ind A N B/ t with the number of turns N and the loop area A. The latter one is directly based on the diameter d of the conductor loop. In Figure 6a a schematic drawing of the wire-loop current sensor is shown together with its characteristic parameters. In a switching event, a change of I C leads to a B/ t and, by integrating the wire-loop current sensor in one of the cuts in the PCB, a sensor signal, i.e. V ind, is induced. Due to the fact that V ind B/ t, the collector current is given by I C = const V ind t. Therefore, by measuring the sensor signal, I C is determined and the switching losses of the power module were calculated. As mentioned above, N and A affect the sensor signal, whereas V ind will increase linearly with both, N and A, as long as the magnetic field in the conductor loop is homogeneous and no parasitics attenuate the sensor signal. Figure 6b and c show the amplitude of the sensor signal in arbitrary units versus A and N, respectively. For both parameters, the sensor signal increases linearly until A = 20 mm² or N = 5 are reached. Beyond these points, the slope of the curve is reduced. Figure 5 a) Low-inductive setup (L σ = 13 nh) based on a PCB design which allows integrating a wire-loop current sensor in-between the DC-link capacitors and the power module. b) Conventional setup (L σ = 30 nh) with a current probe integrated close to the DC-link capacitors. Figure 5a shows a photo of a low-inductive setup, which was developed for the characterization of the EasyPACK- 2B module. To reduce the stray inductance of the setup, module and low-inductive DC-link capacitors are integrated in a PCB. For the PCB, a strip-line design is used. In contrast to the setup in Figure 5b, no conventional current probe is integrated in the DC link. To measure the device current, additional cuts were inserted in the PCB. In one of these cuts, a wire-loopcurrent sensor was positioned perpendicular to the current flow. Especially for fast-switching devices, this method of measuring the device current by inserting a wire-loop current sensor is very promising [6]. Figure 6 a) Schematic drawing of the wire-loop current sensor. b) Amplitude of the sensor signal in arbitrary units versus the loop area. c) Amplitude of the sensor signal in arbitrary units versus the number of turns. Inside the cut in the PCB, the magnetic field is homogenous and, thus, the sensor signal depends linearly on A. For larger loop areas, the conductor loops are positioned partially outside of the cut. Hence, the inhomogeneity of the magnetic field increases and, for A 20 mm², the slope of the curve is reduced. The larger N, the more turns

5 are integrated within the cut in the PCB. Hence, the distance in-between the turns is reduced and the capacitive coupling within the sensor, i.e., in-between the conductor loops, becomes dominant. This capacitive coupling provides a lowpass-filter characteristic and, in turn, this results in an attenuation of the sensor signal. 3.3 Impact of the low-inductive setup on the device performance The presented results on the wire-loop current sensor make clear that this method is feasible to determine I C within a low-inductive setup. Prior to the first measurement, a calibration of the sensor signal is required. Within this calibration, the constant factor const, which depends on the sensor geometry and the positioning of the sensor in the setup, is determined. This allows calculating I C by integrating the sensor signal. The measurements were performed at T vj = 150 C and with V DC = 600 V. Here, too, V GE = ±15 V was used to drive the IGBTs. On the left-hand side of Figure 7, the turn-on and turn-off waveforms of the EasyPACK-2B module operated in the low-inductive setup are shown. I C was determined by integrating the sensor signals, which are shown in the upper part on the right-hand side. The di/dt during the turn-off induces an over-voltage peak V CEpeak. Although the -di/dt for both measurements, i.e. for the low-inductive and the conventional setup, are identical, V CEpeak is 30 % lower in the low-inductive setup. For the turn-on, the strayinductance-induced voltage drop on V CE is affected significantly by the used setup. Whereas, for the conventional setup, a di/dt of 5.0 ka/µs results in a voltage drop of more than 180 V, a voltage drop of only 120 V is observed for a di/dt of 5.4 ka/µs in the low-inductive setup. This result is in good agreement with the above determined stray inductances of the setup and the power module. Figure 7 On the left-hand side: Turn-on and turn-off waveforms of the EasyPACK-2B module operated in the low-inductive setup at T vj = 150 C. The measurements were performed for V CEnom = 600 V and I Cnom = 200 A. On the right-hand side: Waveform of the sensor signal for the turn-on and turn-off of the EasyPACK-2B module with V DC = 600 V and I C = 200 A (top). Switching losses versus I C of the EasyPACK-2B module in the lowinductive setup at T vj = 150 C (bottom). In the upper part on the right-hand side of Figure 7, the signal of the wire-loop current sensor is displayed for the turn-on and the turn-off. The di/dt during the switching induces a sensor signal and, by integrating this signal, I C was calculated. In its present design, the wire-loop current sensor provides a resolution of 1.2 V per 1 ka/µs. According to the findings presented above, higher resolutions can be obtained by varying A and N. In the lower part on the right-hand side of Figure 7, the switching losses versus I C are shown for the low-inductive setup. In comparison to the conventional setup, E OFF is almost identical and no impact of the reduced L σ is observed. In contrast to this, E ON is lower for the lowinductive setup. The common expectations are that a reduction of the setup-stray inductance leads to an increase of E ON due to the lower stray-inductance-induced voltage drop on V CE. On the contrary, the di/dt during the turn-on increases in the low-inductive setup. This originates from the less negative dv/dt which is feeding back through the Miller capacitance to the gate. Hence, a reduction of L σ allows the realization of higher di/dt during the turn-on with an identical gate-driver configuration, which, in turn, results in a lowering of E ON. A comparison of the di/dt during turn-on shows that, for the low-inductive setup, the di/dt is up to 30 % larger than for the conventional setup. In accordance with this, E REC was raised, mainly due to the increased di/dt during the switching event, by using the low-inductive setup. In summary, the low-inductive setup leads to less switching losses for IGBT and to increased switching losses for the diode compared to the conventional setup. The sum of losses is almost identical and, thus, the EasyPACK-2B module provides even in the low-inductive setup lower losses, in the operating point, than the reference module in the conventional setup. As mentioned above, the fullysymmetric and low-inductive design of the EasyPACK- 2B module enables the usage of fast-switching devices, which results in a significant reduction of the switching losses. 4 Conclusion In this paper, the implementation of a 200 A / 1200 V half-bridge module in an EasyPACK 2B with a modulestray inductance of only 8 nh is demonstrated. The design of the module is based on a strip-line concept which allows the combination a fully-symmetric layout together with a minimized commutation path within the module. The low-inductive and symmetric design provides a good controllability of the switches and, in turn, allows the integration of fast-switching IGBTs and low-loss diodes. A comparison of this low-inductively-designed module with a state-of-the-art reference module points out that the new concept outperforms the reference module in terms of switching performance. To determine the advantages of this low-inductive module design, a setup with a stray inductance of no more than 13 nh was developed. This was achieved by using a wire-loop current sensor instead of a conventional current probe.

6 5 References [1] G. Miller, New semiconductor technologies challenge package and system setups, CIPS, Nuremberg, Germany, [2] R. Bayerer, Parasitic inductance - a problem in power electronics, ISiCPEAW, Stockholm, Sweden, [3] R. Bayerer and D. Domes, Power circuits design for clean switching, CIPS, Nuremberg, Germany, [4] D. Domes, R. Bayerer, and A. Herbrandt, New module concept for overall low inductance, PCIM Europe, Nuremberg, Germany, [5] R. Bayerer and D. Domes, Parasitic inductance in gate driver circuits, PCIM Europe, Nuremberg, Germany, [6] E. Hoene, A. Ostmann, B. T. Lai, C. Marczok, A. Müsing, and J. W. Kolar, Ultra-low-inductance power module for fast switching semiconductors, PCIM Europe, Nuremberg, Germany, 2013.