Integrated optical switch matrices for packet data networks Stabile, R.; Albores-Mejia, A.; Rohit, A.; Williams, K.A.

Transcription

1 Integrted opticl switch mtrices for pcket dt networks Stile, R.; Alores-Meji, A.; Rohit, A.; Willims, K.A. Pulished in: DOI: 1.138/micronno Pulished: 1/1/216 Document Version Pulisher s PDF, lso known s Version of Record (includes finl pge, issue nd volume numers) Plese check the document version of this puliction: A sumitted mnuscript is the uthor's version of the rticle upon sumission nd efore peer-review. There cn e importnt differences etween the sumitted version nd the officil pulished version of record. People interested in the reserch re dvised to contct the uthor for the finl version of the puliction, or visit the DOI to the pulisher's wesite. The finl uthor version nd the glley proof re versions of the puliction fter peer review. The finl pulished version fetures the finl lyout of the pper including the volume, issue nd pge numers. Link to puliction Cittion for pulished version (APA): Stile, R., Alores-Meji, A., Rohit, A., & Willims, K. A. (216). Integrted opticl switch mtrices for pcket dt networks., 2, [1542]. DOI: 1.138/micronno Generl rights Copyright nd morl rights for the pulictions mde ccessile in the pulic portl re retined y the uthors nd/or other copyright owners nd it is condition of ccessing pulictions tht users recognise nd ide y the legl requirements ssocited with these rights. Users my downlod nd print one copy of ny puliction from the pulic portl for the purpose of privte study or reserch. You my not further distriute the mteril or use it for ny profit-mking ctivity or commercil gin You my freely distriute the URL identifying the puliction in the pulic portl? Tke down policy If you elieve tht this document reches copyright plese contct us providing detils, nd we will remove ccess to the work immeditely nd investigte your clim. Downlod dte: 14. Nov. 218

2 OPEN (216) 2, 1542; REVIEW ARTICLE Integrted opticl switch mtrices for pcket dt networks Riplt Stile 1, Aron Alores-Meji 2, Ahinv Rohit 3 nd Kevin A. Willims 1 Integrted circuit technologies re enling intelligent, chip-sed, opticl pcket switch mtrices. Rpid rel-time reconfigurility t the photonic lyer using integrted circuit technologies is expected to enle cost-effective, energy-efficient, nd trnsprent dt communictions. InP integrted photonic circuits offer high-performnce mplifiers, switches, modultors, detectors, nd de/multiplexers in the sme wfer-scle processes. The complexity of these circuits hs een trnsformed s the process technologies hve mtured, enling component counts to increse to mny hundreds per chip. Active pssive monolithic integrtion hs enled switching mtrices with up to 48 components, connecting 16 inputs to 16 outputs. Integrted switching mtrices route dt strems of hundreds of gigits per second. Multi-pth nd pcket time-scle switching hve een demonstrted in the lortory to route etween multiple fire connections. Wvelength-grnulrity routing nd monitoring is relised inside the chip. In this pper, we review the current sttus in InP integrted photonics for opticl switch mtrices, pying prticulr ttention to the dditionl on-chip functions tht ecome fesile with ctive component integrtion. We highlight the opportunities for introducing intelligence t the physicl lyer nd explore the requirements nd opportunities for cost-effective, sclle switching. Keywords: lrge-scle integrtion; opticl switching devices; optoelectronics; photonic integrted circuits (216) 2, 1542; ; Pulished online: 11 Jnury 216 INTRODUCTION Cloud-sed services, video trffic, enterprise pplictions, nd virtulistion hve led to relentless rise in trffic in opticl communictions networks 1. In turn, this is leding to unsustinle energy usge nd n incresing complexity in network control 2 4. Opticl pcket routing nd switching technologies offer the prospect of highly efficient networking tht is ttuned to pcket-sed trffic flows 4. However, to dte the underlying photonic hrdwre hs not proved sufficiently sclle, nd the physicl lyer performnce hs een impeded y the nlogue nture of the underlying photonic components. Photonic switch mtrices nd wvelength-selective switches lredy provide energy-efficient connectivity t the highest ndwidths for circuit-provisioned time-scles. The opticl switching engines tht re now eing deployed in telecom networks nd dt centre networks re sed on slow (millisecond) circuitswitching technologies tht leverge micro-electro-mechnicl systems (MEMS) 5,6 nd liquid crystl on silicon 7,8 switch elements. 3D MEMS systems now llow for connectivity etween mny hundreds of fire connections 9,1. The comintion of rodnd photonic switches nd wvelength-selective diffrctive opticl elements offers even higher connectivity. However, the use of surfce norml micro-optics introduces considerle ssemly complexity s the connectivity scles. The switching speeds do not support pcket-sed trffic t the opticl lyer. Plnr photonic integrted circuits hve long held the promise of high-speed rodnd connectivity with mss-mnufcturele microchips 11, ut only recently hs the technology 12 mtured to the point tht circuits with sufficient numers of components cn e relised. Photonic integrted circuits enle not only switching solutions for high cpcity dt ut lso support the components required to support loss compenstion, dynmic reconfigurility, power equlistion, chnnel monitoring, nd multicsting. In this work, we review the progress mde in electroniclly ctuted, monolithic switching circuits. The methods used for creting these circuits hve een reported elsewhere 13 15, nd we focus here on circuit-level functionlity. In section MONO- LITHIC OPTICAL SWITCH ARCHITECTURES, we review the integrtion technologies tht hve enled high-connectivity routing in plnr opticl nd optoelectronic circuits. We then focus on circuits tht exploit the InP integrted photonics pltform. In section BROADBAND PHOTONIC PACKET SWITCH MATRICES, we ddress rodnd implementtions with demonstrtions of up to 32 G s 1 line rtes, pcket time-scle reconfigurility nd connectivity of up to 16 ports in pcket-complint switching mtrix. A study of the circuit-level gin, loss, nd noise performnce provides insight into the future sclility of these circuits. In section WAVELENGTH-SELECTIVE PACKET SWITCHING MATRI- CES, we ddress developments in the scling of monolithiclly integrted wvelength- nd spce-selective elements. We identify opportunities for wvelength-grnulrity opertions such s opticl lel routing nd in-line monitoring. We discuss the possiilities nd chllenges for future deployment in the DIS- CUSSION section nd offer n outlook in the lst section. MONOLITHIC OPTICAL SWITCH ARCHITECTURES Plnr integrted circuit technologies hve een implemented with wide rnge of switch rchitectures nd electroniclly ctuted methods. These rnge from thermo-optic nd electrooptic methods for controlling loss, gin, nd refrctive index through the electrosttic movement of wveguides. A rod rnge of estlished techniques using interferometric nd gted switch elements hve lso een reported Here we focus 1 COBRA Institute, Eindhoven University of Technology, Postus 513, Eindhoven 56MB, The Netherlnds; 2 Ntionl Institute of Advnced Industril Science nd Technology (AIST), Centrl 2, Umezono, Tsuku, Irki , Jpn nd 3 PhotonIC Corportion, 58 Uplnder Wy, Culver City, CA 923, USA Correspondence: Kevin A. Willims (k..willims@tue.nl) Received: 17 August 215; revised: 1 Novemer 215; ccepted: 23 Novemer 215

3 2 Integrted opticl switch mtrices Tle 1 Lrge-scle switches relised with plnr integrtion technologies Pltform Actution method Inputs Outputs λ pths Reference 1 2 nd 2 2 elements in multistge rchitecture LiNO 3 EO Mch-Zehnder LiNO 3 EO Mch-Zehnder Polymer TO DOS PLC Silic PLC TO Mch-Zehnder SOI CI Mch-Zehnder SOI TO Mch-Zehnder SOI TO Mch-Zehnder InP Mch-Zehnder InP Mch-Zehnder nd 2 2 elements in cross-point rchitecture Silic PLC TO ule-ctuted SOI Electrosttic MEMs SOI TO micro-rings SOI TO micro-rings InP SOA directionl coupler N nd N N elements InP SOA InP SOA nd λ conversion InP EO phse rry InP SOA nd EO phse rry InP SOA InP SOA Arevitions: EO, electro-optic; TO, thermo-optic; CI, current injection. specificlly on switch circuits tht cn e scled in cpcity nd connectivity. Tle 1 chronologiclly highlights prominent exmples, specifying circuits in terms of their rchitectures, mterils, ctution mechnisms, nd connectivity. Figure 1 shows schemtic implementtions for the rnge of circuits reviewed. Cscded 2 2 switch elements 19 28, s shown in Figure 1, enle incresing connectivity through the conctention of dditionl switching stges. Such switches cn e redily implemented with comintion of reltively long phse modultors within 2 2 Mch-Zehnder interferometers. Erly work ws performed using Lithium Niote Ti:LiNO 3, Silic, nd SiON technologies. The former enled the exploittion of fst electro-optic phse modultion within Mch-Zehdner interferometers. Switch mtrix connectivities of nd were demonstrted erly on through multistge networks ut chieving high extinction rtios in rodnd switch elements hs proven chllenging. Doule-stge switch elements provide enhnced extinction 22. Switch elements used in comintion with semiconductor opticl mplifier (SOA) gtes offer n even smller footprint 28. The physicl size of electro-optic phse modultors hs led to circuit pth lengths of few centimetres for the erlier exmples, ut technology dvnces driven y highperformnce InP modultors hve llowed su-millimetre-length phse shifters with low voltge ctution 29. Thermo-optic phse shifters for Silicon on Insultor switches with 8 8 connectivity hve led to footprint of mm 2 24 nd circuits with connectivities of up to , ut thermo-optic ctution hs not een sufficiently fst for pcket-sed trffic. Compct current injection, Mch-Zehnder switches offer route to fster reconfigurility 3. Here the Mch-Zehnder switch elements re implemented with pssnd-rodened couplers with ndwidths greter thn 75 nm. However, criticl phse mtching is required for rodnd opertion. A need for on-chip mplifiction hs een identified for further scling in connectivity 18. The cross-point rchitecture 31 35, which uses n rry of orthogonl input nd output guides, is shown schemticlly in Figure 1. The rchitecture uses compct switch elements tht redily scle. 1 2 elements cn e effectively used t the intersection, with ultr-low-loss off-stte losses for high sclility. Silic plnr light wve circuits hve een used in comintion with thermlly ctuted ule-switch elements to chieve connectivities up to Connections re mde y totl internl reflection t trenched intersections nd roken y infilling the trenches with n index-mtched fluid 31. Plnr integrted MEMS hve een deployed in comintion with twin-guide plnr circuits to crete monolithic 5 5 photonic switch mtrices 32. An electrostticlly ctuted MEMS wveguide is moved to enle directionl coupling etween the input nd output uses 32. These wveguides re low-loss nd rodnd, with compct footprint of mm 2, lthough the ctution voltges re still reltively chllenging t the low tens of volts. Ring resontor elements hve een considered extensively, given the incresed vilility of silicon on insultor technology for photonic circuits. Plcing rings t the intersections etween the input nd output usses llows wvelength-specific routing through thermo-optic tuning 33. Higher order ring resontors offer flttened-pssnd response tht enles wvelength-tolernt, rodnd routing in crossgrid rry 34. Fster ctution hs proven more chllenging with cross-point rchitectures generlly ecuse the physicl size of the switching elements hs lrgely precluded the use of fst electro-optic switching. One potentil exception is the verticlly coupled SOA switch concept, which hs een scled to 4 4 connectivity 35. c d Figure 1 Switch rchitectures including () multistge switches exploiting 2 2 elements, () cross-point switch mtrices, (c) rodcst nd select with splitter cominer, nd (d) wvelength selection with de/multiplexer pir.

4 Integrted opticl switch mtrices 3 Brodcst nd select techniques offer the prospect of multicst routing t the chip level, nd connectivity cn e scled y mens of multiple interconnected stges 36. An equivlent pth-to-pth connection is lso fesile in the wvelength domin y mens of wvelength conversion 37. An exmple is shown in Figure 1c. Splitters nd cominers hve enled up to 16 connections. Work on one-to-mny switches hs led to the demonstrtion of 1 16 connectivity for rodnd phse rry switches 38 nd 1 1 connectivity for n integrted two-stge circuit comprising comintion of phse rrys nd SOA gtes 39. N N switch mtrices require shuffle networks with wveguide crossings nd the dditionl ssocited opticl wiring complexity. However, this complexity cn e trctle using lower rdix rodcst nd select elements in multistge rchitectures. An ll-mplifying circuit hs een implemented with three stges of four 4 4 switch-uilding locks to demonstrte the first lossless port count opticl switches 36. The electricl power consumption of the ll-ctive chip is estimted to e 12 W for fully opertionl circuit with moderte power density of.3 W mm 2. Approximtely hlf of the required electricl power is required to is the split nd shuffle elements t trnsprency. The use of n ll-ctive epitxy lso degrdes the noise performnce nd limits the opticl input power dynmic rnge. Recently, we hve demonstrted ctive pssive integrted circuits with connectivity, leding to improvements in opticl signl-to-noise performnce 14. These results re reviewed in further detil in section BROAD- BAND PHOTONIC PACKET SWITCH MATRICES to provide insights into the potentil for scling nd performnce. Wvelength-selective switching (WSS) cn e performed within plnr wveguide monolithic circuits. Progrmmle Mch-Zehnder filter chins 4 nd gted rryed wveguide grting filters 41 hve oth een studied. The erliest wvelength lockers using SOA gtes were implemented with 1 1 physicl connectivity nd up to 1 wvelength on-chip selectivity 42. An exmple implementtion is shown in Figure 1d, where the splitters nd cominers hve een replced with wvelength de/multiplexers. Scling to N N with on-chip wvelength selectivity offers powerful route towrds very high levels of connectivity. The possiility to connect ritrry wvelength comintions with comintion of rodcst nd select switches nd wvelength-selective switches enles functionlity tht pproches tht of (modest-connectivity) multi-degree reconfigurle opticl dd drop multiplexing. This cn e chieved through the comintion of de/multiplexers nd rodnd cominers. Circuits with 4 4 connectivity for four wvelengths 43 nd more recently 8 8 with eight wvelengths 15 hve now een implemented with this concept within 1 cm 2 of n InP chip nd re reviewed in section WAVELENGTH-SELECTIVE PACKET SWITCHING MATRICES. The use of on-chip mplifiers dditionlly enles pth to opticl lossless, multi-cst functionlity nd rod rnge of control nd monitoring functions. BROADBAND PHOTONIC PACKET SWITCH MATRICES Monolithiclly integrted photonic switches introduce considerle flexiility nd ndwidth ut without wvelength-scle grnulrity. SOA gte switches enle pssnds of severl Terhertz, enling colourless nd wvelength-multiplexed routing with 1 2 V ctution levels. In the on stte, the signls re mplified, nd in the off stte, they re strongly ttenuted. As the dt throughput is not directly linked to the ctution energy, such rodnd switches re expected to enle considerle energy svings with respect to electronic switching s line rtes increse. This motivtes the study of highline-rte signl routing. 32 G s 1 line rte routing The first multistge SOA-sed switch using ctive pssive InP regrown wfers ws implemented with n N-stge plnr design using cscded 2 2 crossr switch elements. Figure 1 shows the rchitecture for the four-input, four-output switching mtrix. Figure 2 shows the circuit, which ws fricted s prt of multi-project wfer (MPW) run to study high seril line rte dt trnsmission in such multistge networks 44. The crossr elements were implemented with rodcst nd select switches. The gold pds visile in Figure 2 re the electrodes, which re used for controlling the 2 2 crossr switch elements. For convenience, the opticl connections re mde from the sme front fcet, nd the electronic connections to the SOA gtes re mde to PCB on the right side of the photogrph. The performnce of the switch ws originlly studied in terms of the power penlty with incresing line rte nd n incresing numer of switching stges, to etter understnd the physicl limittions in ultrhigh line rte optoelectronic integrted circuits. Custom test eds were implemented nd used to nlyse the signl degrdtion over rnge of line rtes from 4 G s 1 nd 16 G s 144 to 32 G s 145. For worst cse electricl power consumption per gte of.2 W, four 32 G s 1 chnnels could in principle e routed with power of 1.2 W, which corresponds to su-pj/it energy udget. It should e noted tht the energy consumption is it-rte independent for switches of this clss, nd the efficiency improves with incresed throughput. Signl impirments my e nticipted through such circuits, nd they will increse s the signl propgtes through dditionl mm Power penlty (db) 4 3 : 4 stges 2 1 Time (ps) stges Line rte (G s 1 ) Figure 2 Integrted, four-input, four-output multistge switching network produced in n MPW run 44 () photogrph of the switch circuit nd () highline-rte routing through the circuit. The power penlty is shown s function of incresing line rte. The solid line shows predictions for noise-limited performnce. The solid symols show the experimentlly mesured dt. The open symols represent dt simulted with the lrge-signl numericl model. The inset shows the experimentl eye digrm mesurement for 32 G s 1 line rte routing.

5 4 Integrted opticl switch mtrices switch elements. By compring the signl qulity efore nd fter the switch for different numers of switch stges nd line rtes, it ecomes possile to develop n insight into the scling properties of the switch mtrix, oth in terms of cpcity nd connectivity. A it error-rte nlysis ws performed for the three different line rtes nd different numers of integrted switch elements to study signl qulity degrdtion mechnisms. Figure 2 shows the power penlty for 4, 16, nd 32 G s 1 for two- nd fourswitch stges. The inset shows mesured, open eye digrm for the 32 G s 1 signl, which hs een routed through four stges of integrted crossr switches. The power penlty is negligile for modest 4 G s 1 line rtes, ut the signl qulity degrdes s the line rte increses to 16 G s 1 nd ove. The power penlty incurred through the switching network my e expected to degrde through nonlinerities in the SOA gtes nd the uildup of dditionl noise in the circuit. Two models were used to predict nd quntify the precise contriutions to the signl degrdtion 46. A lrge-signl model 47 ws implemented to simulte the comined effects of the SOA nonlinerity nd noise s function of the line rte, nd the simulted dt points re shown using open symols. A smll signl model 48 ws lso pplied to predict the noise-incurred power penlty, nd this is shown using solid line. Shot noise, signl spontneous et noise nd spontneous spontneous et noise were defined consistently with the lrge-signl model prmeters. The equivlent noise figure for ech mplifier stge for the optimum on-stte condition ws 6.5 db, nd the gin for ech on-stte SOA gte ws ssumed to equl the 7 db pssive component loss from the splitter cominer pir in the 2 2 switch element. A comprison of the experimentl dt with the noise model nd the lrgesignl model indictes tht performnce to 32 G s 1 ppers to e noise limited. However, higher line rtes re expected to e impcted y the higher men input powers ssocited with higher line rtes, nd this is expected to led to gin sturtion nd ptterning in the output dt strem. Wvelength multiplexing schemes might e considered to chieve higher ggregte throughputs. Dynmic routing with nnosecond reconfigurtion times The full demonstrtion of pcket routing in integrted opticl switch mtrices requires n strction of the photonic physicl lyer from the control plne. The most efficiently implemented form of strction hs een relised with fst current driver rrys in comintion with round-roin scheduler. Figure 3 shows n integrted 4 4 rodcst nd select switching mtrix to demonstrte pcket time-scle connectivity. Dt were input to ech of the four opticl inputs, nd the time trces were recorded for ll the opticl outputs. The round-roin scheduler enled comintions of pths to e sequenced on 3.2 µs time slot 49. Figure 3 shows the output time trce from the first output. The independent level control for ech of the SOA gtes enled on-chip opticl power levelling. The complete circuit required only one time slot clock input signl to synchronise with the externl network. Multiple gte sttes were simultneously defined to llow the full utilistion of the fric. Lrge-scle switching mtrices using multiple stges of switch elements require more complex switching lgorithms, lookup tles, nd level control, which motivte the use of progrmmle logic for the schedulers nd level control. This hs een implemented 5 for susequent work on 8 8 nd connectivity switching mtrices. Arrys of fst (nnosecond) current drivers were connected to the SOA selector gtes of the integrted cross-connect to enle pth nd chnnel selection. The current levels for ech of the SOA selector gtes were seprtely progrmmed y rrys of digitl-to-nlogue converters nd centrl microcontroller. An Alter Strtix III field progrmmle gte rry provided time-slotted control signls to the nnosecond rise time current drivers for opticl pth selection 5. A lck of on-chip opticl uffering limited opertion to time slot schemes, ut the precise durtion of the time slots ws progrmmle 51. This electronic control plne hs more recently een implemented to enle time slot resolved errorrte mesurements during scheduled multi-pth opertion in n 8 8 switching fric 52. Flow control hs lso een implemented for more distriuted control plnes connectivity in monolithic switch High-rdix 4 4 SOA-sed switch elements cn e efficiently configured in multistge networks to enle high connectivity with limited numer of stges. Three switch stges provide good compromise etween opticl wiring complexity, signl integrity, nd control complexity. A monolithic connectivity switch hs een implemented with ctive pssive integrtion 14. A composite microscope photogrph is shown in Figure 4. The input nd output wveguides for the circuits re visile t the fcets on 25 µm grid t the left nd right edges of the circuit, respectively. The circuit comprised n input stge of 2 2 switch rrys on the left nd n output stge of 2 2 switch rrys on the right. These were interconnected with two plnes of 4 4 switch rrys. The 4 4 switches with losscompensted rodcst nd select cpility enled multicst oth t switch element level nd t the circuit level. A totl of 192 ctive SOA gtes were integrted with 188 pssive splitters nd cominers within circuit re of mm, which creted one of the most complex circuits in its clss to dte. Connections were fesile from ny port to ny port, with just three SOA gtes on ny pth. The dditionl switching plne t the centre stge llowed for two different pths for ech input output comintion to enle rerrngele nonlocking design. Mesurements of circuit performnce were used to nlyse the pth-dependent chrcteristics in terms of gin, loss, nd noise. Inputs 1 nd 16 were electroniclly progrmmed to connect to ech of outputs 1 through to 16. The longest nd shortest pth lengths nd representtive rnge of intermedite pth lengths Inputs Electronic control signls Outputs Output 1 Input: Time (µs) 15 Figure 3 () 4 4 rodcst nd select switch operting with round-roin scheduler showing () opticl pcket routing with nnosecond switch reconfigurtion.

6 Integrted opticl switch mtrices 5 Figure output photonic switch mtrix. Fier-to-fier signl loss (db) Input signl power 6 Input signl OSNR OSNR db.1 nm Output numer Output numer Figure 5 Performnce nlysis for switching mtrices. () Fire-to-fire losses, () opticl signl-to-noise rtio. Input reference (green dotted line), mesured performnce (red circles), predicted performnce (red solid line), nd projected performnce (lue dshed line) with component optimistions per Tle 2. through the circuit were nlysed y compring the circuit s input nd output signl nd noise levels using n opticl spectrum nlyser. Figure 5 shows the fire-to-fire signl loss when moving from pth 1-to-1 to pth 1-to-16 (open circles). The fire-to-fire signl losses incresed s the pth length nd complexity incresed. This is quntittively consistent with the dditionl incurred losses for the longer pths, s shown y the predicted losses in Figure 5. The rodcst-enled rchitecture incurred 3 db of opticl loss ecuse ten 3-dB opticl splitter cominers were present in ny given pth. An dditionl gin from the SOA gtes compensted for much of the excess component loss. Figure 5 shows the opticl signl-to-noise performnce for the sme pths rnging from 28.3 to 13.7 db.1 nm 1 for men, in-fire, input opticl power of 2.1 dbm. A direct correltion cn e oserved etween pth loss nd the degrdtion in the opticl signl-to-noise rtio. Although these vlues re encourging, one might expect lower loss nd improved noise performnce with three stges of on-chip SOAs gtes. A circuit-level nlysis ws therefore performed using component-level performnce dt from seprte test structures nd circuits using comprle friction techniques. The circuit-level losses were nlysed y evluting the losses in comprle circuits nd through direct mesurement. The two vlues for the component losses re summrised in Tle 2. The first set of vlues re for the component types implemented in the switching circuit nd the second set of vlues re those tht hve een chieved in seprtely optimised chips. The predicted performnce for the implemented circuit elements (solid line) nd the projected performnce with optimised circuit elements (dshed lines) re shown in Figure 5. The greement for the implemented elements is excellent, giving confidence tht the loss nd noise performnce of the circuits cn e clerly ttriuted to the excess losses of the components. The noise performnce ws predicted y estimting the opticl power mp for the signl nd noise within the switch mtrix circuit nd including the dditionl mplified spontneous emission noise contriuted t ech SOA gte. Ech of the three stges of the SOA gtes in the circuit ws expected to operte with men gin of 12.9 db nd men mplified spontneous emission power density of 47.3 dbm.1 nm 1. The operting opticl input power ws 21 dbm, so the 5-µm-long gtes were operted fr from the opticl sturtion power. The electricl is conditions were 75 ma nd 1.5 V. The component-level excess losses re summrised in Tle 2, nd lthough they my pper to e modest for ech component, the comintion of the high numers of components in ech pth, long wveguide lengths nd the two fire-to-chip couplings led to high levels of circuit-level excess losses, which were 3 db nd ove. However, the losses cn e significntly reduced. For Tle 2 Losses in the fricted circuits nd losses ssumed with improved design Loss Inherent In circuits Best cse Fire to chip [54] db Splitters [14] 3.2 [55] db Crossings.2 [14].2 [56] db Deep wveguides 8. [14].5 [57] db cm 1 Shllow wveguides 5.5 [14].5 [57] db cm 1

7 Integrted opticl switch mtrices 6 Figure 6 Monolithic spce- nd wvelength-selective switches. () 4 4 circuit operting on four wvelength nds. This circuit ws produced in n MPW run. () 8 8 circuit operting on eight wvelength nds. Note the difference in the scle rs. exmple, mode-size dption t the fcets my e expected to reduce fire-to-chip coupling to 1.5 db per connection54. Low prsitic reflection splitters operting with only.2 db excess loss55 would led to net loss reduction of 3 db. The numer of crossing is significnt, vrying from 7 to 26, ut the loss per crossing my e reduced y n order of mgnitude through rodening in the intersecting wveguides56. Wveguide losses of pproximtely.5 db cm 1 my e expected when the level of pdoping is minimised in the pssive wveguides57. Such optimistions of excess losses hve een shown to enle lossless circuitlevel opertion nd will lso hve rdicl impct on the opticl signl-to-noise rtio, reducing the opticl signl-to-noise rtio to 5.3 to 49.2 db per.1 nm. This would e equivlent to circuitlevel noise figure of 9.7 db, of which 5.5 db is ttriutle to losses etween the input side fire nd the first SOA gte. WAVELENGTH-SELECTIVE PACKET SWITCHING MATRICES The integrtion of wvelength switching functions within monolithic photonic switches enles dditionl control nd connectivity, while retining the sme level of opticl fire connectivity. This offers powerful comintion of wvelength, time, nd spce domin switching on single chip. Pcket-reconfigurle multi-wvelength routers cn e implemented y comining demultiplexer, gte rry, nd rodnd cominer. The underlying concept ws first prototyped in integrted form for pcket routing pplictions with 1 4 gted cyclic router connecting four ports with wvelength-selective SOA gtes58. The 4 4 circuit43 replictes this concept four times nd interconnects the circuits with 4:16 split-nd-shuffle network nd spce-selective SOA gtes. This is shown in Figure 6. Thirty-two ctive components were integrted with 24 splitters nd cominers nd four cyclic routers to chieve 64 possile pths through the circuit. This circuit hs now een used to demonstrte multi-pth 4 G s 1 routing59 nd multistge routing through the sme circuit6. This repeted circultion indictes the possiility for further scling t the network level. Higher on-chip 8 8 connectivity hs lso een chieved using the sme technology pltform nd rchitecture15. The split-nd-shuffle network on the left of Figure 6 ws scled up to 8:64 y douling the numer of inputs nd dding n dditionl premplifier nd splitter stge. Eight 8 8 cyclic routers comined with gte rry on the right-hnd side of the circuit enled the wvelength selection functionlity. A numer of wvelength routing mesurements hve een performed, including dynmic multi-cst routing nd wvelength-multiplexed pcket routing with low power penlty5,52. The inclusion of on-chip de/multiplexing lso introduces opportunities for on-chip signl monitoring nd remotely reconfigured switching. Opticl lel routing Remotely configured, WSS is performed using the SOA gtes s oth monolithiclly integrted lel reders nd chnnel selectors. Here the dul functionlity of n SOA rry cn e exploited to either detect lels or gte routed signls. A proof-of-principle experimentl demonstrtion ws performed using our first monolithiclly integrted photonic integrted 1 4 wvelength nd spce-selective switch61. In the experimentl proof-of-concept, which is shown schemticlly in Figure 7, two dt wvelengths were controlled y one out-of-nd opticl lel. This llowed the fst remote 1 G s-1 dt Trnsmitter l1 Trnsmitter l2 Trnsmitter n lel Control signl SOA l1: gte signl SOA l1: opticl signl SOA n 2n Electronic susystem Test input l2: gte signl l2: opticl output Control re-write* Multiplexed output Wvelength selective switch node Time (µs) 15 Figure 7 Lel routing demonstrted with 1 4 wvelength-selective switches using the SOAs s oth gtes nd control signl monitors. The time trces show the time domin multiplexing of the two wvelength chnnels (5 µs time-se).

8 Integrted opticl switch mtrices 7 l 7 l Inputs Premplifiers Fn out Gte rry Cyclic router Fn in Outputs O 1 O 7 OSNR (db per.1 nm) SOA NF (d) Input power in fier (dbm) Figure 8 In-line OSNR monitoring demonstrted with n 8 8 spce- nd wvelength-selective switch. () Circuit configurtion, () comprison of the on-chip nd off-chip opticl signl-to-noise mesurements. The differences etween the on-chip (lue line) nd off-chip (red line) mesurements were used to clculte the finl SOA gte noise figure (open circles). configurtion of the WSS stte for the two test dt wvelengths. The presence or sence of the opticl-lel wvelength defined which of the two dt chnnels pssed through the circuit. More sophisticted routing lgorithms re lso fesile for higher numers of chnnels nd ports. For the dynmic routing studies, the pttern trigger signl from the it error-rte tester ws used to crete squre wve modultion for the control chnnel. The switch stte toggled etween high nd low with ns time slot. This ws sufficiently long to enle gted error mesurements under dynmic lel routing conditions. The time trces show, from top to ottom, the remotely generted control signl, the gte signls to the SOAs, nd the resulting time-interleved wvelengths. The opticl lel wvelength ctuted the gtes for the two incoming dt wvelengths, which led to the successful time multiplexing of the two dt strems seen in the lower time trce. On-chip opticl performnce monitoring As switching mtrices ecome more complex nd interconnected, it ecomes importnt to monitor the opticl signl qulity s dt pss through the switching mtrices. Recently, we proposed nd demonstrted scheme for on-chip opticl signl-to-noise rtio (OSNR) monitoring 62. One output pth from the spce- nd wvelength-selective switch ws re-purposed for performnce monitoring using the sme component set nd circuit configurtion s shown in Figure 8. The finl stges of the SOA gtes re now used to monitor signl nd noise power, respectively. The distriution of the SOA gtes efore nd fter the cyclic router enled the on-chip clirtion of the OSNR meter, which further enled pre-clirtion nd, potentilly, inservice clirtion, depending on the mode of opertion. The pre-clirtion ws performed using the centrl-stge SOA gtes s rodnd light sources. The photocurrents mesured t the premplifier SOAs nd the wvelength-selective SOA gtes yielded the rodnd nd filtered integrted opticl power, which ws used to clculte noise power spectrl density correction fctor. Under live-trffic conditions, pckets my e intermittently copied or routed to the OSNR meter for the mesurement of signl nd noise powers. In principle, this nlysis cn e performed in rel time nd t the pcket level. An experimentl vlidtion of the concept is shown in Figure 8. The uppermost spce selecting SOA routed the signl under test to the uppermost wvelength-selective plne. However, in this cse the wvelength-selective SOA gtes were implemented s photodiodes. The outputs were connected to trns-impednce mplifiers insted of fst current drivers. The output voltge ws recorded nd clirted to give the opticl signl-to-noise rtio shown in Figure 8. To verify the technique, comprison ws mde etween the OSNR vlues tht were mesured using the on-chip method nd vlues directly mesured using n opticl spectrum nlyser connected vi the output wveguide nd the finl-stge SOA gte. The mesured OSNR vried from to 4 db per.1 nm, depending on the opticl input power to the circuit. The vlues exceeded 3 db per.1 nm for in-fire, input opticl powers exceeding 9 dbm. A strong correltion cn e oserved etween the on-chip nd off-chip mesurements, lthough there ws cler offset etween the two mesurements of 3.9 to 5.3 db. This offset corresponds to the nticipted noise figure of the wvelength-selective SOA gte, which needs to e included for the off-chip mesurement. This ws forwrd ised t 4 ma, with n estimted input power of 16.8 dbm nd gin of 8.2 db. DISCUSSION Opticl pcket switching mtrices my e expected to offer compelling lterntive to the comintion of electronic frics with opticl trnsceiver interfces when the photonic integrted circuits re trnsprent, sclle, mnufcturle, nd network complint. Energy nd cost dvntges my e nticipted s line rtes scle through the use of extensive opticl multiplexing. Trnsprent opertion requires the minimistion of noise, signl-induced distortion nd inter-chnnel crosstlk. Gin nd noise re linked, ut s shown in this work, the use of modestconnectivity, loss-less switch elements in multistge rchitecture does provide mens to optimise the opticl power distriution in the circuit with mngele levels of noise. The noise figures nticipted in this work re db for ech integrted semiconductor opticl mplifier, which will llow sclle, loss-less, nd multistge circuits 63. The input side firechip coupling loss domintes the circuit-level noise figure, which provides strong motivtion for further integrtion. The polristion-independent performnce is ttrctive ecuse it enles the use of stndrd fires nd polristion-multiplexed trnsceivers. Polristion-independent opertion hs long een fesile for individul semiconductor opticl mplifiers, de/multiplexers, nd splitters, ut it will e chllenging to ensure wide-nd opertion under ll operting conditions for complex circuits using reconfigured comintions of mny such components. Switch technologies tht rely on directionl coupling, electrooptic modultion, or grting techniques will e more chllenging to implement in polristion-independent mnner. On-chip polristion hndling my offer more sclle nd mnufcturle pproches. Scling to mny tens of connections is conceivle from n opticl power-mp nd opticl power dynmic rnge perspective 63, ut crosstlk levels nd switch extinction rtios will need to e controlled 64. For exmple, the current wvelength-selective switch designs pper to e limited y wvelength chnnel

9 8 Integrted opticl switch mtrices crosstlk levels of the order of 2 db in nonoptimised de/ multiplexers 15. Integrtion density is not currently limiting fctor, nd component counts hve lredy een scled to 17 devices in the most dvnced WDM devices 65. Integrted de/ multiplexers similrly scle to severl tens of chnnels. Therml loding will influence design. To dte, the electricl input energy is pproximtely 16 W even for ll-ctive lossless switch frics 36, ut ctive pssive integrtion nd component optimistions will led to further electricl power reductions for lossless, circuit-level opertion. On-chip routing nd shuffling of connections my prove to e more chllenging in the sence of multi-level opticl wiring solution. Mnufcturility will require ll components to meet loss, extinction, nd crosstlk specifictions cross the full opertionl ndwidth nd t sufficient yields to meet product-pricing requirements. This will e chllenging, ut it is worth noting tht stisfctory yield performnce metrics hve een chieved in the highly demnding telecom trnsceiver mrket using dvnced InP integrted photonics 66. Criticl dimension vritions my e expected to ecome incresingly importnt with circuit scling. Potentilly importnt dvnces include the use of whispering gllery regimen wveguiding for reproducile, low-rdius microends 67, precision-fricted, low-loss de/multiplexers, low-reflection splitters, nd mnufcturle polristion controllers 68. Deep-UV lithogrphy cn enle oth tighter dimensionl control nd lso lower loss, lower crosstlk de/ multiplexer components tht will e importnt for wvelengthselective rchitectures. Nevertheless, lrger numers of conctented components will led to nrrowing of the operting regimens, which will impct the yield performnce specifiction nd ultimtely determine the most ttrctive levels of chip-level connectivity. Networking requirements will cll for further innovtions in control nd synchronistion. Integrtion does simplify scheduling through the ner-negligile delys etween components, ut routing lgorithm complexity still scles rpidly with connectivity 69. Burst mode trnsceiver technology will ply key enling role in the currently conceived opticl pcket switch systems. The evolution from low rtes to tens of G s 1 performnce hs een well documented for pssive opticl networks 7. Burst-mode opertion of up to 25 G s 1 is fesile for the reconfigurtion time-scles envisged for pssive opticl networks 71, nd route towrds 4 G s 1 links hs een identified 72. Efficient pcketsed networks will, however, require shorter reconfigurtion times. In the first opticl pcket demonstrtions, 25.6 ns premles nd 25 ns gurd times were used for the error-free reception of synchronous 1 G s 1 pckets 73 ;25Gs 1 urst mode receiver technology specificlly for opticl pcket switching is now lso eginning to emerge from industry reserch lortories 74,75. Gted oscilltor nd oversmpling techniques for clock nd dt recovery re identified s methods to further reduce the premle nd gurd time requirements 76. OUTLOOK InP integrted photonic circuits offer powerful route to comining dvnced routing nd signl-processing functions onto one chip. Throughputs with line rtes of 32 G s 1 hve een demonstrted with multistge networks, nd circuit connectivity hs scled to 16 ports. Further connectivity scling is chievle with on-chip wvelength routing. To relise key cost performnce dvntges, further integrtion will e necessry, nd new components will need to e introduced 12 to enle higher circuit densities, efficiencies, nd polristion hndling. The requirements for reduced energy use, lower ltency nd lower cost for incresing dt rtes re expected to continue nd led to sustined pressure on su-system integrtion. The photonic components used re nlogue in nture, ut this needs to e strcted to enle trctle network-level implementtions. Multicst cpility, pcket time-scle reconfigurility, power levelling irrespective of signl pth, distriuted signl qulity monitoring, nd dt rte trnsprency cn e implemented t the chip level, which will enle n strcted digitl control plne. Achieving this level of signl processing my hve impct eyond the immedite pressure points in dt communictions nd find potentil new pplictions from sensor redout technologies to opticl em-forming technologies. ACKNOWLEDGEMENTS The work hs een supported y the Dutch technology foundtion STW. Two of the circuits were produced on MPW runs y the technicl stff t the COBRA institute. MPW runs re supported t jeppix.eu. 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Proceedings of the Numericl Simultion of Opticl Devices 1 5 Sep 28; Nottinghm, UK, Post-dedline pper ThPD5; Stile R, Willims KA. Photonic integrted semiconductor opticl mplifier switch circuits. In: Advnces in opticl mplifiers. Intech, Rijek, Croti; 211: Summers J, Vllitis T, Evns P et l. Monolithic InP-sed coherent trnsmitter photonic integrted circuit with 2.25 Tit/s cpcity. Electronics Letters 214; 5: Kish F, Ngrjn R, Welch D et l. From visile light-emitting diodes to lrge scle III-V photonic integrted circuits. Proceedings of the IEEE 213; 11: Stile R, Willims KA. Relxed dimensionl tolernce whispering gllery microends. Journl of Lightwve Technology 211; 29: Willims KA, Bente EAJM, Heiss D et l. InP photonic circuits using generic integrtion. Photonics Reserch 215; 3: B6 B68.