Processing and Reliability Issues That Impact Design Practice. Overview

Transcription

1 Lecture 15 Processing and Reliability Issues That Impact Design Practice Zongjian Chen Copyright 2004 by Zongjian Chen 1 Overview As a maturing industry, semiconductor food chain has been broken into sectors (design houses, foundries, packaging houses, distributors, etc). Technical information that needs to be passed between design houses, and foundries has, for the most part, taken the form of models and design rules. This type of abstraction relieves the designers of the burden to understand the details of the process effect and/or some of the reliability requirements However, it is worthwhile to look into some of these process effects, because: Some of them may force future design practices to be radically different from what were used in the past Some of them force the formulation of design rules/practices that one would not expect from a pure performance/cost consideration Some of the effects are discovered so recently that people have not come up effective rules to deal with the generic cases so one need to know what the effects are and when they can make a difference. 2

2 Topics Lithography effect and impact on layout practices Chemical-Mechanical Polishing (CMP) effect and impacts on design practices Design for burn-in Antenna effect and fixes Soft error rate considerations More recently discovered effects Stress effects Well approximate effect 3 Lithography Effect and Impact on Layout Practices The science of resolving features smaller than wavelength is getting pushed to the limit R min = K1 λ/na λ is the wavelength of the light source, NA is the numerical aperture of the lens, k1 is a unit-less constant that has a theoretical minimum of 0.5 using on-axis (traditional) illumination. Reducing λ and increasing NA further from where they are today induce both economical and technical difficulties. K1 has been pushed towards/beyond the theoretical limit by using resolution enhancement techniques ITRS Node Year Pitch λ/na 248/ / / / 0.85? k ? 4

3 Resolution Enhancement Techniques Attenuated phase shift mask lithography Use a mildly translucent mask Background light 180 out-ofphase with light from clear regions Improves contrast at the edge Optical Proximity Correction Pre-distort mask shapes to compensate for known systematic inaccuracies attpsm and OPC does not change the fundamental resolution limits k1 at or slightly below 0.5 attpsm OPC 5 Strong RET At 65nm node k1 needs to be significantly below 0.5 Strong RET is needed: Idea: one of the light source approximating the openings on the mask is pushed back by ½ λ Exploit constructive/destructive interference effect 6

4 Strong RET Describing it with optics language Smaller path difference required at first interference Limit: R min =0.25 λ /NA 2X theoretical improvement Two ways to do it: Alternating phase shift mask (altpsm) Off-axis Illumination altpsm OAI 7 Implications of Strong RET OAI: Angle of the light source shared by all features Feature pitch significantly different from the optimum pitch will not get the resolution enhancement. altpsm Restrictions on layout are complex and can not be handled by simple DRC rule Implications: Gridded layout practice can be a solution in either case Designs meant to be migrated into 65nm need to take this into consideration Grid altpsm concept altpsm complexity Grid altpsm/oai example 8

5 CMP Effect and Impact on Design Practice Dual Damascene: the standard approach for modern multi-level interconnect logic process Copper CMP removes copper and dielectric at a different rate, leading to dishing/erosion effect. Barrier layer to prevent Cu from diffusing into Si SiN layer for etch stop M2 M1 An amateur s view of dual damascene ( via-first variation) 9 Electrical Impact of the Dishing and Erosion Effect Shorts for upper layer interconnects Higher sheer resistance 10

6 Design Solutions for Dishing Effect Make layout to have less variation in metal/oxide density Limit on wide metal (slotting fat metal ) Fill pattern in empty metal area Implications to designs There may be more capacitance than what you see in the layout post fill extraction is important Your wide metal can be more resistive then you think If you want to do matching of layout, pay attention to white space: they may not be filled in the same way 11 Burn-In and Its Design Implications Burn-in: Using higher than usual levels of stress to speed up the deterioration of parts to weed out infant mortality Stress condition are typically 1.5 the normal operation voltage and much higher ( o C) temperature. To have enough stress coverage, dynamic burn in became a common practice for complex parts inputs are stimulated and functionality of the design is assumed during burn-in 12

7 Design Implications for Burn-In Functionality requirements (not speed) at burn-in condition poses extra challenge for design. Race, leakage sensitive circuits have to be characterized in this corner. Example of leakage sensitive dynamic circuit optimization for burn-in compatibility : 13 Antenna Effect Plasma related process steps are used extensively in CMOS flow (etching, deposition) Charge from the electrons and ions in the plasma can be collected by conductive material on the wafer, and a net charge accumulation will leads to a change of the potential of the conducting material until that potential itself is big enough to open up the charge drainage path to balance out the collection from plasma. If the drainage path is through gate oxide, charge can be trapped in the oxide, leading to many side effects, including shift of device threshold, creation of interface states which leads to earlier breakdown of the oxide, mobility degradation, worse sub-threshold slope, etc. Example End structure Charging effect at the end of poly etch Charging effect at the end of metal1 etch 14

8 Antenna Rules The questions is: how to limit the current density through the thin oxide Approach one: if the drain path has to go through the thin oxide, limit the ratio of collection area and drainage (thin oxide) area Approach two: provide alternative path for the drainage path diodes. m4 m3 m2 2000λ m1 gate diff A case of m3 antenna violation gate ndiff psub Antenna diode fix 15 Antenna Rules More on antenna diodes: In normal operation the diodes will be reversely biased and have only a minuscule impact on total capacitance During processing, even if the diodes are reversely biased, because of the elevated wafer temperature (200 o C plus) it will provide a much conductive path There may still be a ratio requirement on the collection area over the diode area Approach three: bridging m4 m3 m2 m1 gate psub 2000λ 16 diff

9 Soft Error Rate Considerations Soft Error: Lost of states stored in memory elements due to charge upsets caused by alpha particles and high energy neutrons in the cosmic radiation The scaling of trend SER rate depends on: collection area, charge on the storage node, and probability of that a striking event can cause charge greater than the charge stored being collected From 0.25um to 90m node soft error rate, per bit, has been going up slightly. The number of on chip bits going up exponentially SER rate is a serious problem that needs to be dealt with. SER in Dram SER in SRAM 17 Design Solutions for Soft Error Normal code containing message bits only has code distance of 1 The distance of a code is the minimum number of bits by which anyone code word differs from any other With enough check bits added into the code, the new expanded code space is no longer fully populated Code space can now have legal regions and illegal regions; If a final value is in the illegal region of the code space, error is then detected The code distance of the new code can be made to be 2 or greater. The distance between the illegal point in the code space representing the corrupted code and the nearest legal code, together with the code distance, can give hint on the value of the precorrupted data. Example: Parity bit Code distance of 2; illegal code distance 1 from legal code; correction not possible 18

10 Design Solutions for Soft Error Example: Single Error Correction/ Double Error Detection for a 4 bit message (b1, b2, b3, b4) Inset check bit c1, c2, c3 to form the 7 bit new code (x1, x2, x3, x4, x5, x6, x7) = (c1, c2, b1, c3, b2, b3, b4) c1 = xor(b1, b2, b4) c2 = xor(b1, b3, b4) c3 = xor(b2, b3, b4) Recalculate the check sum on the post transmitted value using the same equation Address error bit calculated as follows e1 = xor (c1, c1 ) e2 = xor (c2, c2 ) e3 = xor (c3, c3 ) Binary address (e1, e2, e3) called syndrome. Syndrome of 000 means no error 19 Strained Silicon and Its Impact on Device Characteristics Strain can change the band structure of silicon which in turn influences the carrier mobility via band scattering rates or carrier effective mass. Technologists have purposely inserted process steps to take advantage of this physical effect to improve device characteristics Stained (tensile) silicon grown on top of relaxedsi x Ge1-x have been used to improve CMOS performance Up to 80% increase in mobility, 20-30% increase in saturation current have been reported Strained Si Relaxed SiGe Si Substrate 20

11 Unintentional Strain in Modern Device and Impact on Design Practices Modern ULSI process steps introduces stress that can become prominent when device dimensions shrinks below 90nm node For example, Shallow-Trench- Isolation (STI) included stress have observable adverse effect on device performance STI creates compressive stress within the plane parallel to gate Active region of devices at or below 90nm node is mall enough for the stress have observable impact on device behavior CAD tools are being updated to take these effect into account in post layout timing analysis 21 Mask Proximity Effect During Implant Implanted ion scattered out of the edge of photoresist are implanted in the silicon surface on the mask edge Usually happens for high energy implant, such as those used to form the wells. Can affect the threshold of the device in either direction Impact on Design In SRAM cells pull-down NFE are more susceptible to this problem than pass gate because of physical closer proximity to the resist edge during well implant An increased pull-down NFET Vt can affect cell stability and read current Also matching implications: if one want to match device, match the neighboring well patter too. 22

12 Summaries We have examined a few process issues that need changes in design practices as part of the solutions Some issues imply radical shift in design practices in the future Some issues have imposed extra design rules/steps in the current design flow As scaling in being pushed towards the extreme, new process/reliability issues will show up. More solutions coming from design communities are expected 23