Design and Development of 8-Bits Fast Multiplier for Low Power Applications
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1 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 Design nd Development of 8-Bits Fst Multiplier for Low Power Applictions Vsudev G. nd Rjendr Hegdi, Memer, IACSIT proportionl to the word length of the multiplier input. Due to the regulrity of their structures, rry multipliers re crrying to lyout nd hve een implemented frequently. The second clss of prllel multipliers reduces mtrix of prtil product its to two words through the strtegic ppliction of counters or compressors [2]. These two words re then summed using fst crry-propgte dder to generte the product. This clss of prllel multiplier is known s column compression multiplier. These re lso fstest multiplier s the dely is proportionl to the logrithm of the multiplier nd word length. Astrct High speed multipliction hs lwys een fundmentl requirement of high performnce processors nd systems. With MOS scling nd technologicl dvnces there is need for design nd development of high speed dt pth opertors such s dders nd multipliers to perform signl processing opertions t very high speed supporting higher dt rtes. In DSP pplictions, multipliction is one of the most utilized rithmetic opertions s prt of filters, convolves nd trnsforms processors. Improving multipliers design directly enefits the high performnce emedded processors used in consumer nd industril electronic products. Hence there is need for design nd development of high-speed rchitectures for N-it multipliers supporting high speed nd power. Here we review the rchitecture reported in the literture for multipliers nd criticl issues degrding the speed nd power of these multiplier. Bsed on this review suitle modifictions re suggested in the design for high speed nd low power multipliers. B. Arry Multipliers In rry multiplier the two sic functions, prtil product genertion nd summtions re comined. For unsigned N N multipliction, N2+N- cells (where N2 contin n AND gte for prtil product genertion, full dder for summing nd N- cells contining full dder) re connected to produce multiplier. This rry genertes N lower product its directly nd uses crry-propgte dder, in this cse ripple crry dder, to form the upper N its of the product. Index Terms CPA, DSP, microprocessor, multiplier. I. INTRODUCTION Multipliction is less common opertion thn ddition, ut is still essentil for microprocessors, digitl signl processors nd grphics engines. Multipliction lgorithms re used to illustrte methods of designing different cells so tht they fit into lrge structure. The most sic form of multipliction consists of forming the product of two unsigned inry numers, simplified to se 2. M N its multipliction cn e viewed s forming N prtil products of M its ech, nd then summing the ppropritely shifted prtil products to produce on M + N its result P[]. Binry multipliction is equivlent to logicl AND opertion. Therefore, generting prtil product consists of logicl ANDing of the pproprite its of the multiplier nd multiplicnd. Ech column of prtil products must then e dded nd if necessry, ny crry vlues pssed to the next columns. C. Column Compression Multiplier Column compression multiplier continued to e studied due to their high speed performnce. This multiplier s totl dely is proportionl to the logrithm of the opernd word length. These multipliers re fster thn rry multipliers whose dely grows linerly with opernd word length. According to Thoms Ko Cllwy et. l. [3] column compression multipliers re more power efficient thn rry multipliers. In 964, Wllce [4] introduced scheme for fst multipliction sed on summing the prtil product its on prllel using tree of crry sve dders which ecme generlly known s the Wllce tree. Ddd [5] lter refined Wllce's method y defining counter plcement strtegy tht required fewer counters in the prtil product reduction stge t the cost of lrger crry-propgte dder. For oth methods, the totl dely is proportionl to the logrithm of the opernd word-length. Other prtil product reduction methods hve een proposed since the work of Wllce nd Ddd. The reduced re [6] nd the Windsor methods re sed on strtegic utiliztion of (3, 2) nd (2, 2) counters to improve re nd lyout, while mintining the fst speed of the Wllce nd Ddd designs. In this pper we identify techniques for optiml computer ided designs of column compression multipliers y nlyzing re, power nd timing chrcteristics with prticulr emphsis on low power. A. Prllel Multipliers In the 96's two clsses of prllel multipliers were defined. The first clss [] of prllel multipliers uses rectngulr rry of identicl comintionl cells to generte nd sum the prtil product its. Multipliers of this type re clled rry multipliers. They hve dely tht is generlly Mnuscript received June 2, 22; revised July 3, 22. Vsudev G. is with the ACS College of Engineering, Bnglore, Indi56 32 (e-mil:dev_gg76@yhoo.co.in). Rjendr Hegdi is with the Prgti College of Engineering nd Mngement, Ripur (C.G)-4925, Indi (e-mil: rjendr.hegdi@gmil.com). DOI:.7763/IJET.22.V
2 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 II. DESIGN AND ANALYSIS The mjor works in this pper re study of multiplier rchitectures for high speed signl processing pplictions, identifying the specifictions for the multiplier design, modeling the rchitecture, functionl verifiction, nd developing the test ench to verify the design for ll possile input comintions. We lso do FPGA implementtion of the proposed multiplier to meet the specifiction identified. Synopsys tool flow is used for ASIC synthesis, physicl design nd implementtion of multipliers. GDSII generted nd report prepred. Following re the technicl specifiction of experimentl work crried out to design nd implement Booth, Wllce, Ddd multipliers using 3nm technology. Input it width: 8-it, signed, unsigned, integer, deciml. Input rrivl: prllel with Mytes / sec. Expected output: 6-it output, supporting ll formts. Output dt rte: Mytes /sec. Tech: 3 nm, Li: TSMC. Power: μ wtts. Are: 4 sq. mm. The power nlysis is the process of clculting the power consumption of the chip. It lso consists of the clcultion of voltge, current drop (IR drop) nd electromigrtion nlysis due to high current density of the metl. Tle I gives the power consumption of the multipliers. Ddd multiplier consumes less re s compred to tht of Wllce tree nd Booth Multiplier. Booth multiplier consumes less power s compred to tht of Wllce tree nd Ddd multiplier. Wllce tree hs less dely s compred to tht of Booth nd Ddd multipliers. Booth multiplier hs mximum numer of ROMs, mcros nd BELS. Wllce tree hs minimum numer of BELS nd mcros compred to Booth nd Ddd multiplier. Also Wllce tree multiplier nd Ddd multiplier hve no flip-flops nd Booth multiplier hs mximum flip-flops. The multipliers hve een synthesized setting constrint on speed to mximum of 3MHz. Bsed on this constrint the tle II gives the design compiler output for vrious fctors of the multipliers. TABLE I: COMPARIAION OF MU LTIPLIERS Booth Wllce Ddd 8 it Multiplier tree Multiplier Are (μm) Power(μw) Timings (ns) For the multipliction of two numers y nd x, we denote the multiplicnd s in () nd multiplier s in (2) y = ( y y ) () M, ym 2... y, x = ( x x ) (2) N, xn 2... x, For unsigned multipliction, the product is given in (3). M j= j y 2 N P = ( )( ) = j i xi2 i= N M i xi y 2 i= j= j + j (3) Numer of techniques cn e used to perform multipliction. In generl, the choice is sed up on fctors such s ltency, throughput, re, nd design complexity. An ovious pproch is to use n M+ its crry propgte dder (CPA) to dd the first two prtil products, then nother CPA to dd the third prtil product to the running sum, nd so forth. Such n pproch requires N- CPAs nd is slow, even if fst CPA is employed. More efficient prllel pproches use some sort of rry or tree of full dders to sum the prtil products. In the erly 95 s, multiplier performnce ws significntly improved with the introduction of Booth multiplier [7], development of fster dders [8] nd memory components. Booth's method nd the modified Booth's method do not require correction of the product when either (or oth) of the opernds is (re) negtive for two's complement numers. During the 95's dder designs moved wy from the slow sequentil circuit executed y ripple crry dders crry look hed, crry select, nd conditionl sum dders yielded speedy sums through the fster simultneous or prllel genertion of crriers. TABLE II: DESIGN COMPILER OUTPUT Multiplier 8 it Booth Wllce tree Ddd Frequency 3MHZ 3MHZ 3MHZ Numer of Ports Numer of Nets Numer of Cells References Comintionl Are (μm) Sequentil Are (μm) Totl Cell Are (μm) Cell internl Power (μw) Net Switching power μw) Totl Dynmic Power(μw) Cell Lekge Power (μw) III. ARRAY MULTIPLIER The two sic functions of rry multiplier, prtil product genertion nd summtion re comined. For unsigned N x N multipliction, N 2 +N- cells re connected to produce multiplier, where N 2 contin n AND gte for prtil product genertion, full dder for summing nd N- cells contining full dder [9]. The rry genertes N lower product its directly nd uses crry-propgte dder, in this cse ripple crry dder, to form the upper N its of the product. Replcing full dder with hlf dders, possily reduces the complexity to N 2 AND gtes, N hlf dders, nd N(N-2) full dders. The worst cse dely is (2N-2) Δ c, where Δ c is the dder dely. In order to design n rry multiplier for two's complement opernds, Booth lgorithm [] cn e employed. This 775
3 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 lgorithm computes the prtil products y exmining two multiplicnd its t time. Except for enling usge of two's complement opernds, this lgorithm offers no performnce or re dvntge in comprison to the sic rry multiplier. Better delys, though cn e chieved y implementing higher rdix modified Booth lgorithm []. Another method for uilding n rry multiplier tht hndles two's complement opernds ws presented y Bugh et l. [2] s shown in fig.. This method increses the mximum column height y two. This my led to n dditionl stge of prtil product reduction, therey incresing overll delys [2]. A modified form of the Bugh et l. strtegy is more commonly used ecuse it does not increse the mximum column height [3]. n -... n- n-2 n- n- 2 n- n-2 2 n - 2 2n - 2 n n-2 n- n-2 n-2 n- 2 n- n- n- n-2 n- n- P2n - P 2n-2 P 2n- 3 P n+ P n P n- P n- 2 P 2 P P Fig.. Two s complement y modified Bugh-Wooley method IV. COLUMN COMPRESSION MULTIPLIER Column compression multiplier continued to e studied due to their high speed performnce. These multipliers totl delys re proportionl to the logrithm of the opernd word length, where s other rry multipliers dely grows linerly with opernd word length. According to Thoms Ko Cllwy et. l. [3] column compression multipliers re more power efficient thn rry multipliers. In 964, Wllce [4] introduced scheme for fst multipliction sed on summing the prtil product its on prllel using tree of crry sve dders which ecme generlly known s the Wllce tree. Ddd [5] lter refined Wllce's method y defining counter plcement strtegy tht required fewer counters in the prtil product reduction stge t the cost of lrger crry-propgte dder. For oth methods, the totl dely is proportionl to the logrithm of the opernd word length. Other prtil product reduction methods hve een proposed since the work of Wllce nd Ddd. The reduced re [6] nd the Windsor methods re sed on strtegic utiliztion of (3, 2) nd (2, 2) counters to improve re nd lyout, while mintining the fst speed of the Wllce nd Ddd designs. This reserch identifies techniques for optiml computer ided designs of column compression multipliers y nlyzing re, power nd timing chrcteristics with prticulr emphsis on low power. V. TOOLS The tools used for this reserch work re Xilinx nd Modelsim from Mentor Grphics. NCsim from Cdence, VCSIM from Synopsys nd Astro tool from Synopsys for physicl design. Design compiler for viewing the schemtic nd primetime for sttic timing nlysis. The Synopsys Design Compiler (DC) nd Design Vision (DV) comprise powerful suite of logic synthesis products, designed to provide n optiml gte-level synthesized netlist sed on the design specifictions, nd timing constrints. Primetime (PT) is the Synopsys sign-off qulity, full chip, nd gte level sttic timing nlysis tool. It llows comprehensive modeling cpilities often required y lrge designs [4]. It is fster compred to design compilers internl sttic timing nlysis engine. It provides enhnced nlysis cpilities to other Synopsys tools, which is sed on TCL lnguge, thus providing powerful fetures of tht lnguge to promote the nlysis nd deugging of the design. The SDF file is used to perform exhustively throughout the ASIC world to perform dynmic timing simultions. It contins timing informtion of ech cell in the design. The sic timing dt comprises of the following. IOPATH dely- specifies the cell dely. INTERCONNECT dely- specifies point to point dely. SETUP timing check- contins the required setup of ech sequentil cell. HOLD timing check-hold time of ech sequentil cell. A. SDF File The SDF file my e generted for pre-lyout or post-lyout simultions. The post-lyout SDF is generted from DC or PT, fter ck nnotting the extrcted RC dely vlues nd prsitic cpcitnces to DC or PT. The post -lyout vlues represent the ctul delys ssocited with the design. The pre-lyout numers contin dely vlues tht re sed upon the wire-lod models; it does not contin the clock tree. Therefore it is necessry to pproximte the post-route clock trees delys while generting the pre-lyout SDF. The post-lyout design contins the clock tree informtion. Therefore ll the steps tht were needed to fix the clock ltency, skew nd clock trnsition time, during pre-lyout phse re not required for post-lyout SDF file genertion. After getting the schemtic view timing, power nd re constrints re set. The netlist, out put of synthesis is the input for the tool. The design setup consists of entire technology file nmed s technology file, lirry exchnge formt, dvnce lirry formt, cell lirry file, physicl lirry, design exchnge formt, top design formt, physicl design formt, nd tle look up files [4]. They contin technology nd foundry dependent prmeters nd re used to get physiclly implemented chip. Next step is to lod the netlist to the lirry for further process like floor plnning, power plnning etc. Floor plnning is process of plcing the input, output, power nd ground pds. The exct loctions of ll the pds re predefined in the technology dependent file (TDF) provided y the tool vendor. Nest step is floor plnning of the design s shown in fig.2. To set spect rtio of the core power plnning hs to e done 776
4 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 y creting the power rings round the core region through which strps nd trunks for the core region re connected. Choose the even metl lyer for verticl nd odd metl lyer for horizontl with hs less RC vlue. We hve used metl 4 for the power nd metl 3 for the ground. After creting the rectngulr rings round the core region connect the VDD nd VSS pds to the power nd ground rings, which is known s pre instnce in the tool option. B. SDC File The next step is lod the stndrd dely constrint (SDC) file contining timing prmeters of the netlist tken t the time of sttic timing nlysis through the primetime tool [4]. At the time of synthesis nets used for routing nd the numericl vlue of the RC re not known. The timing nlysis output should not e violting setup nd hold time. After loding the SDC file nd getting the timing report, plcement is to e done y plcing the stndrd cells horizontlly in the core region. At this step, we set some common option like optimiztion mode, plcement constrints, loction constrints etc. then do pre plcement optimiztion in which we hve to set design clenup, quick plcement optimiztion of high fnout synthesis, idel optimiztion nd logic rempping. After pre-plcement we do post-plcement optimiztion. The next step is to set the clock common option like the conditions worst, est nd uffers, inverters nd perform clock tree synthesis. After the process of clock tree synthesis we hve to do post-plce optimiztion for this set option like setup fixing, hold fixing, mximum cpcitnce, re recovery nd logic rempping. Now the design t this point is DRC free with no violtion in the timing. The next step is to common option like glol routing, trck ssign, CTS net, detiled routing, lirry cells nd design rule etc. routing is lst stge of physicl design flow. After giving the common option we hve to set the net group. After setting the ll options we hve to do glol routing nd fter tht detiled route. After completing ll the routing process we do the post route optimiztion with some constrints like routing phse, optimiztion effort, optimiztion trget, optimiztion mode, optimiztion control, flow control etc. The routing output for the multipliers is s shown in fig. 4. After completing the routing check the design rule checked. If there is ny DRC violtion then we hve to do serch nd repir. This option in the tool will detect the DRC violtion nd it will rectify. Fig. 3. Plcement output Fig. 4. Routing output Plced cells C. DEPOGIT: Dense Power-Ground Interconnect Architecture for Physicl Design Integrity: In recent deep sumicron VLSI design, signl integrity (SI) nd power-ground integrity (PGI) hve ecome very importnt to design in short time. Most engineers working on process design, chip design, nd EDA res re cutely wre of tough chllenges emerging ecuse of process vriility nd physicl integrity issues. Process vriility is not only friction prolem, ut lso serious design issue. Similrly, physicl integrity prolems re not only design nd EDA issues, ut lso process-relted rchitecture prolems. As solution, DEPOGIT is new dense power-ground interconnect rchitecture tht relizes more roust physicl design integrity. It siclly consists of djoining power nd ground lines. This rchitecture is method of running oth the power nd ground wires djcent to the signl wires. This provides not only the generl shielding effect ut lso explicit decoupling cpcitnce (decp) y mens of the wires. This rchitecture lso gurntees regulrity, thus reducing mnufcturing vritions in interconnects. Using this rchitecture High qulity decp for smll chip res cn e otined. The resistive IR drop cn e less thn 2% of tht of conventionl power grid. Trnsient pek noise cn e reduced y out 8%. The inductive crosstlk effect of the signl wire cn e gretly reduced. VI. REVIEW OF MULTIPLIER Left Bottom Fig. 2. Floor plnning process Top Right A. Modified Booth s Multiplier Booth s lgorithm is powerful direct lgorithm to perform signed numer multipliction []. It involves repetedly dding one of two predetermined vlues A nd S to Product P, then performing rightwrd rithmetic shift on P. Let x nd y e the multiplicnd nd multiplier respectively. Let n x nd n y represent the numer of its in x nd y. The modified Booth s multiplier lgorithm to otin 777
5 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 the product of x nd y is s follows. ) Determine the vlues of A, S nd the initil vlue of P. All of these numers should hve length equl to n x + n y +. A: Fill the most significnt (leftmost) its with the vlue of x. Fill the remining (n y +) its with zeros. S: Fill the most significnt its with the vlue of (-x) in two s complement nottion. Fill the remining (n y +) its with zeros. P: Fill the most significnt n x its with zeros. To the right of this ppend the vlue of y. Fill the lest significnt (rightmost) its with zero 2) Determine the two lest significnt (rightmost) its of P. If they re, find the vlue of P+A, ignore ny overflow. If they re, find the vlue of P+S, ignore ny overflow. If they re or, do nothing, use P directly in the next step 3) Arithmeticlly shift the vlue otined in the previous step y single plce to the right. Let P now equl to this new vlue. 4) Repet steps 2 nd 3 until they hve een done n y times. 5) Drop the lest significnt (rightmost) it from P, resultnt is the product of x nd y. B. Wllce tree Multiplier In 964 C.S.Wllce introduced scheme for the multipliction sed on summing the prtil product its in prllel using tree of crry sve dders which ecme generlly known s the Wllce tree [4]. This method hs three step process is used to multiply two numers. Step : The it products re formed Step 2: The it product mtrix is reduced to two row mtrix y using crry sve dders known s Wllce tree. Step 3: The remining two rows re summed using fst crry propgte dder to produce the product. Though the process seems to e complex it yields multipliers with dely proportionl to the logrithm of the opernd word length n. The Wllce tree multiplier elongs to fmily of multipliers clled column compression multipliers. The principle in this fmily of multipliers is to chieve prtil product ccumulted y successively reducing the numer of its of informtion in ech column using full dders or hlf dders. The full dder is known s (3:2) compressor ecuse of its ility to dd three its from single column of the prtil product mtrix nd output two its, one it in the sme column nd one it in the next column of the output mtrix. The hlf dder is known s (2:2) compressor ecuse of its ility to tke two its from single column of the prtil product mtrix nd output two its, one it in the next column of the output mtrix. Fig. 5 gives dot digrm of Wllce tree multiplier. The Wllce tree consists of numerous levels / stges of such column compressor structures until finlly only two full width opernds remin. These two opernds cn then e dded using regulr 2N its dders to otin the product result. The difference etween the Wllce tree multiplier from column compression multiplier is tht, in the Wllce tree every possile it in every column is covered y the (3:2) or (2:2) Compressors respectively. Until finlly the prtil product mtrix hs depth of only two. Thus the Wllce tree multiplier uses s much hrdwre s possile to compress the prtil product mtrix s quickly s possile into the finl product. Fig. 5. Dot digrm of Wllce tree multiplier C. Ddd Multiplier Ddd refined Wllce s method y defining counter plcement strtegy tht required fewer counters in the prtil product reduction stge t the cost of lrger crry propgte dder [5]. Ddd hs introduced numer of wys to compress the prtil product its using such counter which lter ecme known s Ddd s Counter. Fig. 6 gives the process for 8 8 its Ddd multiplier. Fig. 6. Opertion 8X8 its ddd multiplier An input 8 8 its mtrix of dots (ech dot represents it) is shown s step. Columns hving more thn six dots re reduced y the use of hlf dders, ech hlf dder tkes in two dots nd outputs one in the sme column nd one in the next more significnt column nd full dders, ech full dder tkes in three dots nd outputs one in the sme column nd one in the next more significnt column so tht no column in step will hve more thn six dots [5]. Hlf dders re shown y crossed line in the succeeding mtrix nd full dders re shown y line in the succeeding mtrix. In ech cse the rightmost dot of the pir tht is connected y line is in the column from which the inputs were tken from the dder. In the succeeding steps reduction to step 2 with no more thn four dots per column, mtrix three with no more thn three dots per column, nd finlly step 4 with no more thn two dots per column is performed. The height of the mtrices is determined y working ck from the finl two row mtrix nd limiting the height of the ech mtrix to the lrgest integer tht is no more thn.5 times the height of its successor. Ech mtrix is produced from its predecessor in one dder dely. Since the numer of its in the words to e multiplied, the dely of the mtrix reduction process tht 778
6 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 reduces is proportionl to log n, where n is word size. Since the dder tht reduces the finl two row mtrix cn e implemented s crry look hed dder which lso hs logrithmic dely, the totl dely for this multiplier is proportionl to the logrithm of the word size n. VII. COMPARISON A. Comprison of Ddd nd Wllce Tree Multipliers This section gives the comprtive study of the 8 X 8 its Ddd nd Wllce tree multipliers. Wllce tree multiplier uses 38 full dders nd 5 hlf dders. Ddd multiplier uses 35 full dders nd 7 hlf dders. Wllce tree multiplier requires crry-propgte dder of its wide Ddd multiplier requires crry propgte dder of 4 its wide. The other disdvntge of Ddd multiplier is tht it is less regulr thn the Wllce tree multiplier, mking it more difficult to lyout in VLSI design. The multiplier eing one of the mjor complex rithmetic uilding locks for VLSI design hs its own sets of complexities in terms of re, power, speed, nd cost nd design methodology. The tle III nd tle IV show the complexity involved in multiplier design. With it width eing incresed, the numer of stges lso increses, nd this introduces complexity. Wide it width is required for ccurcy nd high smpling rte. Hence there is need for design nd development of n IP tht cn e esily dopted for ny high speed pplictions y just using the sic uilding lock of the multiplier design. TABLE III: NUMBER OF STAGES IN MULTIPLIERS Bit width of Multiplier Numer of Stges to to 9 4 to to to to to o 94 TABLE IV: COMPARIAION OF MULTIPLIERS WITH RESPECT TO AREA, SPEED AND POWER Multiplier Dely (ns) Are (µm 2 ) Power (mw) Ddd using crry look hed dder Ddd using Ripple crry dder Arry Wllce B. FPGA nd ASIC The dvntges of ASIC physicl design over FPGA re listed in tle V. TABLE V: COMPARIAION OF MULTIPLIERS WITH RESPECT TO AREA, SPEED AND POWER Sl. No. FPGA ASIC Complexity of multipliers is Complexity of multipliers more is less 2 Are occupied y the Are occupied y the multipliers is less. multipliers is more. 3 Power consumption y the Power consumption y the 4 multipliers is more. Dely is more nd hence speed is less. multipliers is less. Dely is less nd hence speed is high. VIII. APPLICATION, CONCLUSION AND FUTURE WORK A. Appliction The potentil usges of proposed design re - High Speed Signl Processing tht includes DSP sed pplictions. DWT nd DCT trnsforms used for imge nd wide signl processing. FIR nd IIR Filters for high speed, low power filtering pplictions. Multirte signl processing pplictions such s digitl down converters nd up converters. B. Conclusion In this work we hve identified the techniques for optiml computer ided designs of selected three 8 its multipliers nmely Booth, Wllce tree nd Ddd y nlyzing dely, re nd power chrcteristics with prticulr emphsis on designing the cells for optimum power using lyout design techniques. These three multipliers re implemented nd the constrints re, power nd timing re optimized using Verilog codes sed on softwre resources NC SIM nd VC SIM. The results of the reserch work crried out re Reviewed the existing high speed seril nd prllel multipliers ville, identified the specifiction requirements for the multipliers. Modeled the multipliers using HDL nd verified the functionlity using test vectors. Implemented the design on FPGA nd verified its functionlity nd identified the hrdwre requirements. Crried out ASIC design on the synthesized net list y ppropritely providing the constrints sed on the first cut informtion otined from FPGA synthesis. Compred the performnce of multiplier design nd optimized the design for re, speed nd power. Finlly we conclude tht performnce wise, Ddd multiplier consumes less re s compred to Wllce tree nd Booth multiplier. Power wise Booth multiplier consumes less power compred to Wllce tree nd Ddd multiplier. Dely wise Wllce tree hs less dely s compred to Booth nd Ddd multiplier. From the tles we oserved tht the Ddd Multipliers requires more nets nd consumes lesser references thn Wllce tree multiplier nd Booth multiplier. The increse in numer of intermedite stges in multipliers, the 779
7 IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 interconnection etween the uilding locks lso increses. As Ddd multiplier hs more numer of intermedite stges it hs more numer of interconnections (76.5% more). C. Scope for Future Work: As this work ws limited to design of only the multiplier s n IP using TSMC 3nm CMOS technology, it would e etter to incorporte the Multiplier into MAC unit tht cn perform multipliction nd ccumultion. MAC forms the mjor lock for ny filtering ppliction. During the design of MAC lock, redundncy in filter coefficients cn e exploited to minimize the filter structure nd optimize the performnces of MAC unit. Also, there is possiility in developing hyrid multiplier tht tkes into considertion oth Ddd nd Wllce multiplier rchitecture comined with ooths multiplier. REFERENCES [] R. De Mori, Suggestions for n IC fst prllel multiplier, Electronics letters, vol. 5, pp. 5-5, 965. [2] C. L. Wey nd T. Y. Chng, Design nd nlysis of VLSI-sed prllel multipliers, in Proc. IEEE proceedings Computers nd Digitl Techniques, vol. 37, no. 4, pp , July 99. [3] T. K. Cllwy nd E. E. Swtzlnder, Optimizing multipliers for WSI, in Proc. Interntionl Conference on Wfer Scle Integrtion, 993, pp [4] C. S. Wllce, A suggestion for fst multiplier, IEE Trnsctions on Electronic Computers, vol. EC-3, pp. 4-7, 964. [5] L. Ddd, Some schemes for prllel multipliers, Alt Frequenz, vol. 34, pp , August 965. [6] K. Adre, C. Bickerstff, M. J. Schulte, nd E. E. S. Lnder, Reduced re multipliers, in Proc. Interntionl Conference on Appliction Specific Arry Processors, pp , 993. [7] O. L. Mc Sorley, High-speed rithmetic in inry computers, in Proc. of the IRE, vol. 49, pp. 67-9, 96. [8] B. Gilchrist, J. H. Pomerene, nd S. Y. Wong, Fst crry logic for digitl computers, IRE Trnsctions on Electronic Computers, vol. 4, pp , 955. [9] K. K. Prhi, VLSI digitl signl processing systems design nd implementtion, ASIA: John Wiley nd sons, 999, vol. 5, pp [] A. D. Booth, A signed inry multipliction technique, Qurterly Journl of Mechnics nd Applied Mthemtics, vol. 4, pp , 95. [] R. F. Shw, Arithmetic Opertions in Binry Computer: Review of Scientific Instruments, 95, vol. 2, no. 9, pp [2] C. R. Bugh nd B. A. Wooley, A two s complement prllel rry multipliction lgorithm, IEEE Trnsctions on Computers, vol. C-22, pp , 973. [3] B. Prhmi, Computer Arithmetic: Algorithms nd Hrdwre Designs, Newyork: Oxford University press, 2, vol. 4, pp [4] H. Bhtngr, Advnced ASIC Chip Synthesis, Second Edition: Kluwer Acdemic pulisher, 22, vol. 3-4, pp Vsudev G. This uthor ecme Memer (M) of IAENG. He ws orn on 2 Mrch 985, hs completed B.E from Ngrjun college of Engineering nd Technology,Bnglore, Indi in 26, Completed his M.Tech from JSS Acdemy of Technicl Eduction, Bnglore Indi, in the yer 28. Currently he is working s fculty in ACS College of Engineering, Bnglore, Indi. He is memer of IACSIT. Rjendr Hegdi is Senior Memer ( ) of IAENG, orn in Bijpur, stte Krntk. He hs completed his Mster of Science Degree in Solid Stte Physics from Gulrg University, Gulrg, Krntk, Indi, Mster Technology Degree in Computer Science nd Engineering from Ntionl Institute of Technology Krntk, Surthkl, Indi in 2, Ph.D in Computer Science nd Engineering from Dr. M.G.R. Eductionl Reserch Institute University, Chenni, Indi in 29. He hs over 7 yers of teching in engineering eduction nd 2 yers of softwre industry experience. Currently he is working s Professor nd Principl t Prgti College of Engineering nd Mngement, Ripur (C.G), Indi since 2. Dr. R. Hegdi is the Life Memer of Cryptology Reserch Society of Indi (CRSI), Life memer of Indin Society for Technicl Eduction (ISTE), Memer of The Society of Digitl Informtion nd Wireless Communictions (SDIWC). He is Co-editor of CSVTU Reserch journl. 78
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