ISL Features. 3.3V, Low Power, 30Mbps, RS-485/RS-422 Transceiver. Applications. Pinout. Ordering Information FN Data Sheet March 15, 2005

Transcription

1 ISL448 ata Sheet FN67..V, Low Power, Mbps, RS-48/RS-4 Transceiver The Intersil ISL448 is a high speed BiCMOS.V powered, single transceiver that meets both the RS-48 and RS-4 standards for balanced communication. Unlike some competitive devices, this Intersil transceiver is specified for % tolerance supplies (V to.6v). ata rates up to Mbps are achievable by using this transceiver, which features higher slew rates. Logic inputs (e.g., and ) accept signals in excess of.v, making them compatible with V logic families. Receiver (Rx) inputs feature a fail-safe if open design, which ensures a logic high output if Rx inputs are floating, and the ISL448 presents a single unit load to the RS-48 bus, which allows up to transceivers on the network. river (Tx) outputs are short circuit protected, even for voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. Pinout ISL448 (SOIC) TOP VIEW Features High ata Rate up to Mbps Operates from a Single +.V Supply (% Tolerance) Interoperable with V Logic Single Unit Load Allows up to evices on the Bus Low Current Shutdown Mode na -7V to +V Common Mode Input Voltage Range Three State Rx and Tx Outputs ns Propagation elay, ns Skew Half uplex Pinout Current Limiting and Thermal Shutdown for driver Overload Protection Pb-Free Available (RoHS Compliant) Applications SCSI Fast rivers and Receivers Factory Automation ata Loggers Security Networks R 8 7 B/Z Building Environmental Control Systems Industrial/Process Control Networks 6 A/Y Level Translators 4 GN Ordering Information PART NO. (BRAN) TEMP. RANGE ( C) PACKAGE PKG. WG. # ISL448IB (448IB) ISL448IBZ (448IB) (Note) -4 to 8 8 Ld SOIC M8. -4 to 8 8 Ld SOIC (Pb-free) M8. ISL448IB-T (448IB) -4 to 8 8 Ld SOIC Tape and Reel M8. ISL448IBZ-T (448IB) (Note) -4 to 8 8 Ld SOIC Tape and Reel (Pb-free) M8. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEC J ST-. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 4,. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 ISL448 Truth Tables TRANSMITTING CEIVING INPUTS OUTPUTS INPUTS OUTPUT Z Y X X X High-Z High-Z X High-Z * High-Z * NOTE: *Shutdown Mode A-B +.V -.V Inputs Open X High-Z * X High-Z NOTE: *Shutdown Mode Pin escriptions PIN GN FUNCTION Receiver output: If A > B by at least.v, is high; If A < B by.v or more, is low; = High if A and B are unconnected (floating). Receiver output enable. is enabled when is low; is high impedance when is high. river output enable. The driver outputs, Y and Z, are enabled by bringing high. They are high impedance when is low. river input. A low on forces output Y low and output Z high. Similarly, a high on forces output Y high and output Z low. Ground connection. A/Y Noninverting receiver input and noninverting driver output. Pin is an input if = ; pin is an output if =. B/Z Inverting receiver input and inverting driver output. Pin is an input if = ; pin is an output if =. System power supply input (V to.6v). Typical Operating Circuit +.V ISL448 +.V 8 +.µf.µf + 8 R B/Z A/Y 7 6 R T R T 7 6 B/Z A/Y 4 4 R GN GN FN67.

3 ISL448 Absolute Maximum Ratings to Ground V Input Voltages,, V to +7V Input/Output Voltages A/Y, B/Z V to +.V V to ( +.V) Short Circuit uration Y, Z Continuous Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) 8 Ld SOIC Package Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to C Maximum Lead Temperature (Soldering s) C (Lead Tips Only) Operating Conditions Temperature Range ISL448I C to 8 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications Test Conditions: = V to.6v; Unless Otherwise Specified. Typicals are at =.V, T A = C, Note PARAMETER SYMBOL TEST CONTIONS TEMP ( C) MIN TYP MAX UNITS C CHARACTERISTICS river ifferential V OUT (no load) V O Full - - V river ifferential V OUT (with load) V O R L = Ω (RS-4) (Figure A) Full.7 - V R L = 4Ω (RS-48) (Figure A) Full.. V R L = 6Ω, -7V V CM V (Figure B) Full..6 - V Change in Magnitude of river ifferential V OUT for Complementary Output States V O R L = 4Ω or Ω (Figure A) Full -.. V river Common-Mode V OUT V OC R L = 4Ω or Ω (Figure A) Full -.8 V Change in Magnitude of river Common-Mode V OUT for Complementary Output States V OC R L = 4Ω or Ω (Figure A) Full -.. V Logic Input High Voltage V IH,, Full - - V Logic Input Low Voltage V IL,, Full V Logic Input Current I IN, Full - - µa Full - - µa Input Current (A/Y, B/Z) I IN = V, = V or.6v V IN = V Full -.6 ma V IN = -7V Full ma Receiver ifferential Threshold Voltage V TH -7V V CM V Full V Receiver Input Hysteresis V TH V CM = V - - mv Receiver Output High Voltage V OH I O = -4mA, V I = mv Full V Receiver Output Low Voltage V OL I O = -4mA, V I = mv Full V FN67.

4 ISL448 Electrical Specifications Test Conditions: = V to.6v; Unless Otherwise Specified. Typicals are at =.V, T A = C, Note (Continued) PARAMETER SYMBOL TEST CONTIONS TEMP ( C) MIN TYP MAX UNITS Three-State (high impedance) Receiver Output Current I OZR.4V V O.4V Full - - µa Receiver Input Resistance R IN -7V V CM V Full 9 - kω No-Load Supply Current (Note ) I CC = V or =, = V or = V, = V Full -.7. ma Full -.6 ma Shutdown Supply Current I SHN = V, =, = V or Full - na river Short-Circuit Current, V O = High or Low I OS =, -7V V Y or V Z V (Note 4) Full - - ma Receiver Short-Circuit Current I OSR V V O Full 8-6 ma RIVER SWITCHING CHARACTERISTICS Maximum ata Rate f MAX (Figure A) Full - Mbps river ifferential Output elay t R FF = 6Ω, C L = pf (Figure A) Full ns river ifferential Rise or Fall Time t R, t F R FF = 6Ω, C L = pf (Figure A) Full 6 ns river Input to Output elay t PLH, t PHL R L = 7Ω, C L = pf (Figure C) Full 6 ns river Output Skew t SKEW R L = 7Ω, C L = pf (Figure C) Full - ns river Enable to Output High t ZH R L = Ω, C L = pf, SW = GN (Figure ), (Note ) river Enable to Output Low t ZL R L = Ω, C L = pf, SW = (Figure ), (Note ) Full ns Full ns river isable from Output High t HZ R L = Ω, C L = pf, SW = GN (Figure ) Full ns river isable from Output Low t LZ R L = Ω, C L = pf, SW = (Figure ) Full - 7 ns river Enable from Shutdown to Output High river Enable from Shutdown to Output Low t ZH(SHN) R L = Ω, C L = pf, SW = GN (Figure ), (Notes 7, 8) t ZL(SHN) R L = Ω, C L = pf, SW = (Figure ), (Notes 7, 8) Full - ns Full - ns CEIVER SWITCHING CHARACTERISTICS Maximum ata Rate f MAX V I with t r /t f = ns, t H & t L 6% t UI (Figure 4) Full 7 - Mbps Receiver Input to Output elay t PLH, t PHL (Figure 4) Full 4 8 ns Receiver Skew t PLH - t PHL t SK (Figure 4) Full - ns Receiver Enable to Output High t ZH R L = kω, C L = pf, SW = GN (Figure ), (Note 6) Receiver Enable to Output Low t ZL R L = kω, C L = pf, SW = (Figure ), (Note 6) Full - ns Full - ns Receiver isable from Output High t HZ R L = kω, C L = pf, SW = GN (Figure ) Full - 7 ns Receiver isable from Output Low t LZ R L = kω, C L = pf, SW = (Figure ) Full - 7 ns 4 FN67.

5 ISL448 Electrical Specifications Test Conditions: = V to.6v; Unless Otherwise Specified. Typicals are at =.V, T A = C, Note (Continued) PARAMETER SYMBOL TEST CONTIONS TEMP ( C) MIN TYP MAX UNITS Time to Shutdown t SHN (Note 7) Full 8 9 ns Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low t ZH(SHN) R L = kω, C L = pf, SW = GN (Figure ), (Notes 7, 9) t ZL(SHN) R L = kω, C L = pf, SW = (Figure ), (Notes 7, 9) Full ns Full ns NOTES:. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.. Supply current specification is valid for loaded drivers when = V. 4. Applies to peak current. See Typical Performance Curves for more information.. When testing this parameter, keep = to prevent the device from entering SHN. 6. When testing this parameter, the signal high time must be short enough (typically <ns) to prevent the device from entering SHN. 7. The ISL448 is put into shutdown by bringing high and low. If the inputs are in this state for less than 8ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least ns, the parts are guaranteed to have entered shutdown. See Low-Power Shutdown Mode section. 8. Keep = VCC, and set the signal low time >ns to ensure that the device enters SHN. 9. Set the signal high time >ns to ensure that the device enters SHN. Test Circuits and Waveforms Z Y V O R L / Z Y V O R L = 6Ω 7Ω V CM -7V TO +V R L / V OC 7Ω FIGU A. V O AN V OC FIGU B. V O WITH COMMON MO LOA FIGU. C RIVER TEST CIRCUITS FN67.

6 ISL448 Test Circuits and Waveforms (Continued) V SIGNAL GENERATOR Z Y R FF = 6Ω C L = pf C L = pf OUT (Y) t r, t f = 4.ns t PLH t PHL % % V V V OH FIGU A. FFENTIAL TEST CIRCUIT t PHL t PLH V OL V SIGNAL GENERATOR Z Y OUT R L = 7Ω V OM C L = pf V OH + V OL V OM = OUT (Z) % % t t FF OUT (Y - Z) 9% 9% % % % % t R t F SKEW = t PLH (Y or Z) - t PHL (Z OR Y) VOH V OL +V O -V O FIGU C. SINGLE EN TEST CIRCUIT FIGU B. MEASUMENT POINTS FIGU. RIVER ATA RATE, PPAGATION LAY AN FFENTIAL TRANSITION TIMES SIGNAL GENERATOR Z Y Ω C L = pf SW GN V V PARAMETER OUTPUT SW t HZ Y/Z X / GN t LZ Y/Z X / t ZH, t ZH(SHN) OUT (Y, Z) OUTPUT HIGH % t HZ V V OH OH -.V V t ZH Y/Z (Note ) / GN t ZL Y/Z (Note ) / t ZH(SHN) Y/Z (Note 8) / GN t ZL(SHN) Y/Z (Note 8) / t ZL, t ZL(SHN) OUT (Y, Z) % OUTPUT LOW t LZ V OL +.V VOL FIGU A. TEST CIRCUIT FIGU B. MEASUMENT POINTS FIGU. RIVER ENABLE AN SABLE TIMES 6 FN67.

7 ISL448 Test Circuits and Waveforms (Continued) GN + B A R pf A V V t PLH t PHL SIGNAL GENERATOR % % V FIGU 4A. TEST CIRCUIT FIGU 4B. MEASUMENT POINTS FIGU 4. CEIVER ATA RATE AN PPAGATION LAY SIGNAL GENERATOR GN B A R kω pf SW GN V V PARAMETER A SW t HZ + GN t LZ - t ZH, t ZH(SHN) OUTPUT HIGH t HZ V V OH OH -.V V t ZH (Note 6) + GN t ZL (Note 6) - t ZH(SHN) (Note 9) + GN t ZL(SHN) (Note 9) - t ZL, t ZL(SHN) t LZ OUTPUT LOW V OL +.V V OL FIGU A. TEST CIRCUIT FIGU B. MEASUMENT POINTS FIGU. CEIVER ENABLE AN SABLE TIMES Application Information RS-48 and RS-4 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-4 is a subset of RS-48, so RS-48 transceivers are also RS-4 compliant. RS-4 is a pointto-multipoint (multidrop) standard, which allows only one driver and up to (assuming one unit load devices) receivers on each bus. RS-48 is a true multipoint standard, which allows up to one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-48 spec requires that drivers must handle bus contention without sustaining any damage. Another important advantage of RS-48 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +V to -7V. RS-4 and RS-48 are intended for runs as long as 4, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. Receiver Features This device utilizes a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is ±mv, as required by the RS4 and RS-48 specifications. Receiver input impedance surpasses the RS-4 spec of 4kΩ, and meets the RS-48 Unit Load requirement of kω minimum. Receiver inputs function with common mode voltages as great as +9V/-7V outside the power supplies (i.e., +V and -7V), making them ideal for long networks where induced voltages are a realistic concern. All the receivers include a fail-safe if open function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). The receiver easily meets the data rate supported by the driver, and the receiver output is tri-statable via the active low input. 7 FN67.

8 ISL448 river Features The RS-48, RS-4 driver is a differential output device that delivers at least across a 4Ω load (RS-48), and at least V across a Ω load (RS-4) even with = V. The driver features low propagation delay skew to maximize bit width, and to minimize EMI, and it is tri-statable via the active high input. Outputs of the ISL448 driver are not slew rate limited, so faster output transition times allow data rates of at least Mbps. ata Rate, Cables, and Terminations Twisted pair is the cable of choice for RS-48, RS-4 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in this IC. RS-48, RS-4 are intended for network lengths up to 4, but the maximum system data rate decreases as the transmission length increases. evices operating at Mbps are often limited to lengths of less than one hundred feet. Figure 6 details the ISL448 s Mbps performance driving of CAT cable terminated in Ω at both ends. Note that the differential signal delivered to the receiver at the end of the cable (A-B) still exceeds peak. Longer cable lengths are possible by reducing the data rate, as shown in Figure 7 for a data rate of Mbps. To minimize reflections, proper termination is imperative when using this Mbps device. In point-to-point, or point-tomultipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically Ω) at the end farthest from the driver. In multireceiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multidriver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In river Overload Protection As stated previously, the RS-48 spec requires that drivers survive worst case bus contentions undamaged. The ISL448 meets this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-48 spec, even at the common mode voltage range extremes. Additionally, it utilizes a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short circuit condition, this device also includes a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically reenable after the die temperature drops about degrees. If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. Low Power Shutdown Mode This BiCMOS transceiver uses a fraction of the power required by its bipolar counterparts, nevertheless, the ISL448 includes a shutdown feature that reduces the already low quiescent I CC to a na trickle. They enter shutdown whenever the receiver and driver are simultaneously disabled ( = and = GN) for a period of at least ns. isabling both the driver and the receiver for less than 8ns guarantees that shutdown is not entered. Note that receiver and driver enable times increase when these devices enable from shutdown. Refer to Notes -9, at the end of the Electrical Specification table, for more information. 8 FN67.

9 Typical Performance Curves =.V, T A = C; Unless Otherwise Specified CEIVER OUTPUT (V) = Mbps RIVER INPUT (V) CEIVER INPUT (V) RIVER+CABLE LAY A - B (~9ns) TIME (ns/v) FIGU 6. RIVER AN CEIVER WAVEFORMS RIVING FEET OF CAT CABLE (OUBLE TERMINATE WITH Ω) FIGU 7. RIVER AN CEIVER WAVEFORMS RIVING FEET OF CAT CABLE (OUBLE TERMINATE WITH Ω) FIGU 8. RIVER OUTPUT CURNT vs FFENTIAL OUTPUT VOLTAGE FIGU 9. RIVER FFENTIAL OUTPUT VOLTAGE vs TEMPERATU FIGU. RIVER OUTPUT CURNT vs SHORT CIRCUIT VOLTAGE FIGU. SUPPLY CURNT vs TEMPERATU 9 FN67.

10 Typical Performance Curves =.V, T A = C; Unless Otherwise Specified (Continued) PPAGATION LAY (ns) 6 4 R FF = 4Ω t PHLY t PHLY t PLHZ t PLHY 9 t PHLZ TEMPERATU ( C) FIGU. RIVER PPAGATION LAY vs TEMPERATU SKEW (ns) 4... R FF = 4Ω FIGU A t PHLY - t PLHZ CSSING PT. OF Y & Z - CSSING PT. OF Y & Z t PLHY - t PHLZ TEMPERATU ( C) FIGU. RIVER SKEW vs TEMPERATU CEIVER OUTPUT (V) R FF = 4Ω, C L = pf RIVER INPUT (V) CEIVER OUTPUT (V) R FF = 4Ω, C L = pf RIVER INPUT (V) RIVER OUTPUT (V)... B/Z A/Y TIME (ns/v) FIGU 4. RIVER AN CEIVER WAVEFORMS, LOW TO HIGH RIVER OUTPUT (V)... A/Y B/Z TIME (ns/v) FIGU. RIVER AN CEIVER WAVEFORMS, HIGH TO LOW ie Characteristics SUBSTRATE POTENTIAL (POWE UP): GN TRANSISTOR COUNT: 8 PCESS: Si Gate BiCMOS FN67.

11 ISL448 N Small Outline Plastic Packages (SOIC) INX AA e B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H A µ.(.) M B α.(.4) L M h x 4 o NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. imensioning and tolerancing per ANSI Y4.M-98.. imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side. 4. imension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.6mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.4 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M8. (JEC MS--AA ISSUE C) 8 LEA NARW BOY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C E e. BSC.7 BSC - H h L N α o 8 o o 8 o - Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN67.