Joon Huang Chuah ab & David Holburn a a Electrical Engineering Division, Department of Engineering,

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1 This article was downloaded by: [University of Malaya], [Dr Joon Huang Chuah] On: 02 September 2014, At: 18:15 Publisher: Taylor & Francis Informa Ltd Registered in England and Wales Registered Number: Registered office: Mortimer House, Mortimer Street, London W1T 3JH, UK International Journal of Electronics Publication details, including instructions for authors and subscription information: Design of fully-integrated digitallycontrolled voltage amplifier Joon Huang Chuah ab & David Holburn a a Electrical Engineering Division, Department of Engineering, University of Cambridge, Cambridge CB3 0FA, UK b Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia Accepted author version posted online: 31 Jan 2014.Published online: 24 Feb To cite this article: Joon Huang Chuah & David Holburn (2014): Design of fully-integrated digitally-controlled voltage amplifier, International Journal of Electronics, DOI: / To link to this article: PLEASE SCROLL DOWN FOR ARTICLE Taylor & Francis makes every effort to ensure the accuracy of all the information (the Content ) contained in the publications on our platform. However, Taylor & Francis, our agents, and our licensors make no representations or warranties whatsoever as to the accuracy, completeness, or suitability for any purpose of the Content. Any opinions and views expressed in this publication are the opinions and views of the authors, and are not the views of or endorsed by Taylor & Francis. The accuracy of the Content should not be relied upon and should be independently verified with primary sources of information. Taylor and Francis shall not be liable for any losses, actions, claims, proceedings, demands, costs, expenses, damages, and other liabilities whatsoever or howsoever caused arising directly or indirectly in connection with, in relation to or arising out of the use of the Content. This article may be used for research, teaching, and private study purposes. Any substantial or systematic reproduction, redistribution, reselling, loan, sub-licensing, systematic supply, or distribution in any form to anyone is expressly forbidden. Terms & Conditions of access and use can be found at

2 International Journal of Electronics, Design of fully-integrated digitally-controlled voltage amplifier Joon Huang Chuah a,b * and David Holburn a a Electrical Engineering Division, Department of Engineering, University of Cambridge, Cambridge CB3 0FA, UK; b Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia (Received 18 March 2013; accepted 20 October 2013) This paper presents a fully integrated digitally controlled voltage amplifier. Operating at 3.3 V, this three-stage amplifier was designed and fabricated in an Austriamicrosystems (AMS) 0.35 µm process technology. The amplifier does not require any external discrete components to function and its gain value can be configured by providing digital signals to its control pins. The amplifier performs AC-coupling on the input signals to ensure suitable biasing for proper operation. The good stability of the circuit has been verified. Results obtained from simulations and experiments show that the circuit has a minimum bandwidth of 17.2 MHz. The circuit has been proven to execute well for the gain settings of 1, 10, 100 and 1000 with acceptable losses of 0, 2, 5, 12 db respectively. Keywords: voltage amplifier; variable-gain amplifier; ; fully-integrated; digitally-controlled 1. Introduction Voltage amplifiers have been commonly employed in the signal chain of many electronic systems. The voltage amplifiers selected for use are generally based on the requirements and specifications of a particular application. This research work proposes a voltage amplifier that integrates all its devices and components which are conventionally in the discrete form into a single silicon chip. This implementation will essentially help to reduce the overall dimensions of a system and prove to be a significant contribution in cases where size is one of the main design considerations. In addition to being fully-integrated, the circuit allows the control of its gain to be performed digitally. This voltage amplifier has been designed primarily for assuming the task of the postamplifier in a multi-pixel photon detector (Chuah & Holburn, 2012), which aims to operate at the frequency of 10 MHz. The voltage amplifier has been realised in an Austriamicrosystems (AMS) 0.35 µm process technology (Austriamicrosystems, 2008) and the supply voltage applied is 3.3 V. Design work was carried out with software tools from Mentor Graphics and simulations were conducted by using BSIM3v3 SPICE (Austriamicrosystems (AMS), Unterpremstaetten, Austria) device model provided by AMS. 2. Circuit and layout design Figure 1 depicts the complete circuit construction of the proposed fully integrated digitally controlled voltage amplifier. It consists of three stages of differential amplifier with *Corresponding author. jhc53@cam.ac.uk 2014 Taylor & Francis

3 2 J.H. Chuah and D. Holburn VIN P1 C1 N1 R1 T1 N2 P2 CC1 P3 N3 P4 C2 N4 R4 T2 N5 P5 CC2 P6 N6 P7 C3 N7 R7 T3 N8 P8 CC3 P9 N9 VOUT VBIASR VBIAS2 VBIAS1 VREF Figure 1. R2 R3 S1 VC1 Circuit diagram of fully-integrated digitally-controlled voltage amplifier. frequency compensation component to ensure the stability of the circuit. As the circuit constructions of these stages are identical, subsequent explanation in this paper will be referring to devices in the first-stage wherever applicable. Each stage has a control input to allow digital selection of a voltage gain of 1 or 10. The voltage amplifier thus has different configurations to produce an overall gain of 1, 10, 100 or It is also possible to achieve intermediate gain values by varying the voltage applied to a control pin, so as to adjust the gain value in analogue manner. The signal received by the voltage amplifier is AC-coupled. In traditional signal chains, DC coupling is normally desired at the input as the low frequency signal may also provide important information for analysis. An unexpectedly high DC level, whether from the signal itself or/and from the preceding circuitry, may however prevent the amplifier from working at a suitable input bias, thus resulting in non-linear amplification. For that reason and also considering the possibility of restoring the DC information after the amplification, AC coupling is used in lieu of DC coupling. AC coupling is widely used in circuit design to help bias the transistors of the amplifier at their optimal bias point to achieve optimal gain or optimal noise performance (Bespalko, 2007). The AC-coupling circuit is constructed by using an RC filter (target corner frequency = 50 Hz) implemented with the parasitic capacitance and the on-resistance of two appropriately dimensioned PMOS transistors, C1 and R1. The gate terminal of C1 is connected to the signal input; meanwhile, the source, drain and substrate of C1 are coupled together and connected to the input of the differential amplifier. The size of C1 is chosen as µm, producing a capacitance of 46 pf. The substrate of this transistor (n-well) has a parasitic capacitance of 1.8 pf to the p-type substrate (connected to ground), which negatively affect the bandwidth of the circuit. The semiconductor process used does offer the capability of creating polysilicon-insulator-polysilicon (PIP) capacitor; however, this opportunity was not taken in this work. The main reason is that to achieve the same capacitance value, the lateral dimension of the PIP capacitor must be 5.8 times greater than that of the capacitor created using a PMOS transistor. Furthermore, the parasitic capacitance to the p-type substrate would be even larger at 7.9 pf and this would greatly affect the circuit bandwidth. The NMOS transistor is not suitable for implementation because the substrate, which forms one of the terminals of the parasitic capacitor, must be connected to ground. R1 is implemented with a transistor instead of n- or p-diffusion or polysilicon because it consumes relatively a lot less silicon area and the resistance value can be controlled by varying the gate voltage. PMOS is chosen over R5 R6 S2 VC2 R8 R9 S3 VC3

4 International Journal of Electronics 3 NMOS as the former gives a larger resistance for the same channel dimensions. The W/L ratio of R1 is given a very small value in order to produce a high resistance in the region of 100 MΩ. V BIASR is used to adjust the resistance of R1 and thus the cut-off frequency of the filter. The differential amplifier, which comprises P1, P2, N1, N2 and T1, operates with a tail current, transconductance and output resistance of 205 µa, 865 µs and 0.14 MΩ respectively. P3 and N3 form a push-pull inverter to drive the large input capacitance of the next stage of differential amplifier. CC1 is used for frequency compensation to improve circuit stability. R2 and R3 provide feedback in order to set the voltage gain to 20dB. These resistors are implemented using p-diffusion (polysilicon 8 Ω/sq, n-diffusion 75 Ω/sq, p-diffusion 140 Ω/sq, n-well 1 kω/sq). Despite producing the highest resistance with the smallest area, n-well was not used in the implementation of the resistors as it could cause serious non-linearity issues, which were observed in simulations. An NMOS transistor is used as a binary switch to select between 1 and 10 gain modes. An NMOS transistor is chosen here instead of PMOS as it has a higher transconductance parameter, and hence less resistance, for the same device dimensions. When the gate of the transistor is supplied with V SS, it operates in the cut-off region and gives a very large resistance between source and drain. The gain is therefore not influenced by transistor S1 but by R2 and R3. When the gate of the transistor is supplied with V DD,it operates in the deep triode region with low resistance. This gives a closed-loop gain of nearly one, commonly known as unity-gain feedback. The stability of the differential amplifier is maintained by the inclusion of a suitablevalue capacitor, CC1 between the input and output of the push-pull inverter. This technique is widely known as Miller compensation. It essentially results in pole splitting, which increases the separation between the dominant pole and non-dominant pole and thus improves the stability of the amplifier (Sansen, 2006). By using this technique, a lowfrequency dominant pole is established with a substantially smaller capacitor and this saves a considerable amount of chip area. A PMOS of size W/L = 14 µm/14 µm is used to implement the Miller capacitor, giving a capacitance of 14 µm 14 µm 4.6 ff/µm 2 1/3 ( ) 2.7 pf. Figure 2 shows the frequency response of the differential amplifier in the voltage amplifier without frequency compensation. Under this condition, it exhibits a phase margin of 29. This poor phase margin may cause ringing and long settling time at the output. Figures 3 and 4 exhibit the frequency response of the differential amplifier with inclusion of an ideal capacitor (of 2 pf) and a Miller capacitor (equivalent to 2.7 pf), respectively, for frequency compensation. Both produced stable phase margins of 47 and 65, respectively. Figure 5 shows the full layout of the voltage amplifier, which takes up a silicon area of µm. The identical layouts of the three stages of amplifiers constituting the voltage amplifier were horizontally aligned and connected. The flow of signal is from left to right. Located at the top and occupying nearly half of the layout area are the MOSFET-derived parasitic capacitances used for AC coupling. Despite the minimum feature of the process being 0.35 µm, minimum widths and lengths of 1 µm were used to improve device matching of the differential amplifiers as larger gate areas minimise the impact of local fluctuations and long-channel transistors are less affected by linewidth variations and channel-length modulation (Hastings, 2004). The common centroid technique was used to cancel the effect of first-order process-related gradient along both axes, thus reducing matching error in the differential amplifiers (Razavi, 2001). Figure 6 shows

5 4 J.H. Chuah and D. Holburn Magnitude (db) Phase (degrees) Magnitude (db) Phase (degrees) e e e e e e e + 6 Frequency (Hz) Figure e e e e e e e + 6 Frequency (Hz) C1: e e e C1: e e e db(v(vout)) cphase(v(vout)) Frequency response of differential amplifier in voltage amplifier (without compensation). db(v(vout)) cphase(v(vout)) Figure 3. Frequency response of differential amplifier in voltage amplifier (with compensation using ideal capacitor). the common centroid drawn in the voltage amplifier and its simplified representation. Guard rings were placed around certain devices to reduce the effect of substrate noise (Baker, 2005).

6 International Journal of Electronics 5 Magnitude (db) Phase (degrees) e e e e e e e + 6 Frequency (Hz) C1: e e e db(v(vout)) cphase(v(vout)) Figure 4. Frequency response of differential amplifier in voltage amplifier (with compensation using Miller capacitor). Figure 5. Layout of fully-integrated digitally-controlled voltage amplifier.

7 6 J.H. Chuah and D. Holburn N2 N2 N2 N2 G 2 D 2 S 1 &S 2 D 1 G 1 (a) N1 N1 (b) N1 N1 Figure Results 3.1. Simulation results Table 1 summarises the performance of the voltage amplifier when different gain configurations were set. The output load capacitance used was 1.2 pf. Desired gain results were obtained with different configurations. The lower frequency cut-off was consistent at 48.6 MHz. The worst higher frequency cut-off obtained was 17.2 MHz, i.e. when all subamplifiers were set to 10. The input-referred noise was at V/ Hz, except for the gain configuration of due to its wider bandwidth Experimental results The relationship between the output DC voltage bias and V BIASR is presented in Figure 7. The output bias was quite constant until the value of V BIASR exceeded 0.90 V. Figure 8 shows the frequency responses of different configurations of the amplifier. When compared to values obtained from simulations, the measured gains were lower by 0, 2, 5 and 12 db, respectively, for gain settings of 1, 10, 100 and These poorer results may be caused by the effects of process variation and temperature difference on feedback resistors, which were constructed using p-diffusion. Figure 9 presents the transient response when supplied with a sinusoidal signal of 1 mv ppk and all stages of amplification were set to 10. A clear waveform was produced and the peak-to-peak amplitude measured was reasonably smaller than expected at 453 mv. The performance comparison between different implementations of voltage amplifiers are presented in Table 2. Table 1. Common centroid. (a) Original layout (b) simplified representation. Performance of fully-integrated digitally-controlled voltage amplifier. Gain configuration Gain configuration Gain configuration Gain configuration Gain (db) Lower freq cut-off (Hz) Higher freq cut-off (MHz) Input-referred noise at khz (V/ Hz) Output noise at 100 khz (V/ Hz)

8 International Journal of Electronics 7 Output voltage (V) Figure 7. Gain (db) Figure V BIASR (V) Output DC voltage bias versus V BIASR for voltage amplifier E E E E E E E E Frequency (Hz) Frequency response for voltage amplifier. Gain configuration mv Figure 9. Transient response for voltage amplifier (all amplifying stages are turned on, input = 1 mv ppk ).

9 8 J.H. Chuah and D. Holburn Table 2. Performance comparison of voltage amplifiers. Design Technology Maximum gain (db) Bandwidth (MHz) Power consumption (mw) Require external discrete components? Can control gain digitally? This work Thanachayanont (2008) Rahmatian and Mirabbasi (2007) Hsu and Wu (2003) Calvo, Celma, and Sanz (2003) Srinivasan and Rao (1996) Rijns (1996) 0.35 µm Si 0.35 µm Si 0.18 µm Si 0.35 µm Si 0.35 µm Si Standard 0.8 µm Si No Yes Yes No No Yes No Yes No Yes No No No Yes 4. Conclusions Simulations results show that the voltage amplifier can meet the bandwidth and gain requirements with different gain configurations. The worst-case input-referred noise was V/ Hz. From simulated and measured results, it was concluded that the amplifier has a minimum bandwidth of 17.2 MHz. The gain measurements obtained from experiments were however often lower than indicated by simulations, especially when a higher gain was configured; discrepancies of 0, 2, 5, 12 db respectively for gain settings of 1, 10, 100 and These differences in performance would not substantially affect the circuit from carrying out its basic operation of amplifying when being integrated into a larger circuit or system. Acknowledgements The authors are grateful to Mr. Daniel Aldridge from Carl Zeiss Microscopy and Mr. Bernie Breton, Dr. Nicholas Caldwell and Dr. Paul Robertson from Cambridge University Engineering Department for their useful discussions and technical assistance. Funding This project is financially supported in part by Carl Zeiss Microscopy. References Austriamicrosystems. (2008) μm C35 Process Parameters, Document no. ENG-182, Rev Baker, R. J. (2005). : Circuit design, layout and simulation (2nd ed.). Hoboken, NJ: Wiley- IEEE.

10 International Journal of Electronics 9 Bespalko, R. D. (2007). Transimpedance amplifier design using 0.18 μm Technology (p. 136). Kingston, ON: Department of Electrical and Computer Engineering, Queen s University. Calvo, B., Celma, S., & Sanz, M. T. (2003). High-frequency digitally programmable gain amplifier. Electronics Letters, 39, Chuah, J. H., & Holburn, D. M. (2012). Scalable and configurable multi-pixel photon detector for the scanning electron microscope. Microscopy and Microanalysis, 18, Hastings, A. (2004). The art of analog layout. Beijing: Pearson. Hsu, C. C., & Wu, J. T. (2003). A highly linear 125-MHz switched-resistor programmable gain amplifier. IEEE Journal of Solid-State Circuits, 38, Rahmatian, B., & Mirabbasi, S. (2007). A low-power 75dB digitally programmable variablegain amplifier. Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, 1 3, doi: /ccece Razavi, B. (2001). Design of analog integrated circuits. Singapore: McGraw-Hill. Rijns, J. J. F. (1996). low-distortion high-frequency variable-gain amplifier. IEEE Journal of Solid-State Circuits, 31, Sansen, W. M. C. (2006). Analog design essentials. The Netherlands: Springer. Srinivasan, C., & Rao, K. R. (1996). A 20MHz variable gain amplifier. 9th International Conference on VLSI Design, Bangalore, doi: /icvd Thanachayanont, A. (2008). Low-voltage compact variable gain amplifier. AEU- International Journal of Electronics and Communications, 62,