MOSFET BSC028N06NST. OptiMOS TM Power-Transistor,60V

Transcription

1 MOSFET OptiMOS TM PowerTransistor,6V SuperSO8 Features OptimizedforhighperformanceSMPS,e.g.sync.rec. 175 Crated 1%avalanchetested Superiorthermalresistance Nchannel QualifiedaccordingtoJEDEC 1) fortargetapplications Pbfreeleadplating;RoHScompliant HalogenfreeaccordingtoIEC Table1KeyPerformanceParameters Parameter Value Unit VDS 6 V RDS(on),max 2.8 mω ID 1 A Qoss 43 nc QG(..1V) 37 nc S 1 S 2 S 3 G 4 8 D 7 D 6 D 5 D Type/OrderingCode Package Marking RelatedLinks PGTDSON8 28N6NS 1) JSTD2 and JESD22 1 Rev.2.1,217119

2 OptiMOS TM PowerTransistor,6V TableofContents Description Maximum ratings Thermal characteristics Electrical characteristics Electrical characteristics diagrams Package Outlines Revision History Trademarks Disclaimer Rev.2.1,217119

3 OptiMOS TM PowerTransistor,6V 1Maximumratings atta=25 C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Continuous drain current ID Pulsed drain current 2) ID,pulse 4 A TC=25 C A VGS=1V,TC=25 C VGS=1V,TC=1 C VGS=1V,TA=25 C,RthJA=5K/W 1) Avalanche energy, single pulse 3) EAS 1 mj ID=5A,RGS=25Ω Gate source voltage VGS 2 2 V Power dissipation Ptot Operating and storage temperature Tj,Tstg C 1 3. W TC=25 C TA=25 C,RthJA=5K/W 2) 2Thermalcharacteristics Table3Thermalcharacteristics Values Parameter Symbol Unit Note/TestCondition Min. Typ. Max. Thermal resistance, junction case, bottom Thermal resistance, junction case, top RthJC K/W RthJC 2 K/W Device on PCB, 6 cm 2 cooling area 1) RthJA 5 K/W 1) Device on 4 mm x 4 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 7 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See Diagram 3 for more detailed information 3) See Diagram 13 for more detailed information 3 Rev.2.1,217119

4 OptiMOS TM PowerTransistor,6V 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Drainsource breakdown voltage V(BR)DSS 6 V VGS=V,ID=1mA Gate threshold voltage VGS(th) V VDS=VGS,ID=5µA Zero gate voltage drain current IDSS µa VDS=6V,VGS=V,Tj=25 C VDS=6V,VGS=V,Tj=125 C Gatesource leakage current IGSS 1 1 na VGS=2V,VDS=V Drainsource onstate resistance RDS(on) Gate resistance 1) RG Ω mω VGS=1V,ID=5A VGS=6V,ID=12.5A Transconductance gfs 5 1 S VDS >2 ID RDS(on)max,ID=5A Table5Dynamiccharacteristics 1) Values Parameter Symbol Unit Note/TestCondition Min. Typ. Max. Input capacitance Ciss pf VGS=V,VDS=3V,f=1MHz Output capacitance Coss pf VGS=V,VDS=3V,f=1MHz Reverse transfer capacitance Crss pf VGS=V,VDS=3V,f=1MHz Turnon delay time td(on) ns Rise time tr ns Turnoff delay time td(off) ns Fall time tf 8 16 ns VDD=3V,VGS=1V,ID=5A, RG,ext=3Ω VDD=3V,VGS=1V,ID=5A, RG,ext=3Ω VDD=3V,VGS=1V,ID=5A, RG,ext=3Ω VDD=3V,VGS=1V,ID=5A, RG,ext=3Ω Table6Gatechargecharacteristics 2) Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Gate to source charge Qgs nc VDD=3V,ID=5A,VGS=to1V Gate charge at threshold Qg(th) nc VDD=3V,ID=5A,VGS=to1V Gate to drain charge Qgd nc VDD=3V,ID=5A,VGS=to1V Switching charge Qsw nc VDD=3V,ID=5A,VGS=to1V Gate charge total Qg nc VDD=3V,ID=5A,VGS=to1V Gate plateau voltage Vplateau V VDD=3V,ID=5A,VGS=to1V Gate charge total, sync. FET Qg(sync) nc VDS=.1V,VGS=to1V Output charge Qoss nc VDD=3V,VGS=V 1) Defined by design. Not subject to production test 2) Defined by design. Not subject to production test.see,gate charge waveforms, for gate charge parameter definition 4 Rev.2.1,217119

5 OptiMOS TM PowerTransistor,6V Table7Reversediode Parameter Symbol Values Min. Typ. Max. Unit Note/TestCondition Diode continuous forward current IS 1 A TC=25 C Diode pulse current IS,pulse 4 A TC=25 C Diode forward voltage VSD V VGS=V,IF=5A,Tj=25 C Reverse recovery time 1) trr ns VR=3V,IF=5A,diF/dt=1A/µs Reverse recovery charge 1) Qrr nc VR=3V,IF=5A,diF/dt=1A/µs 1) Defined by design. Not subject to production test 5 Rev.2.1,217119

6 OptiMOS TM PowerTransistor,6V 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation 12 Diagram2:Draincurrent Ptot[W] 6 ID[A] TC[ C] Ptot=f(TC) TC[ C] ID=f(TC);VGS 1V Diagram3:Safeoperatingarea 1 3 Diagram4:Max.transientthermalimpedance µs µs µs.2 ID[A] 1 1 DC 1 ms 1 ms ZthJC[K/W] single pulse VDS[V] ID=f(VDS);TC=25 C;D=;parameter:tp tp[s] ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.1,217119

7 OptiMOS TM PowerTransistor,6V Diagram5:Typ.outputcharacteristics 4 Diagram6:Typ.drainsourceonresistance V 7 V 7 5 V 5.5 V 6 V ID[A] V 5.5 V RDS(on)[mΩ] V V 2 1 V VDS[V] ID=f(VDS);Tj=25 C;parameter:VGS ID[A] RDS(on)=f(ID);Tj=25 C;parameter:VGS Diagram7:Typ.transfercharacteristics 4 Diagram8:Typ.forwardtransconductance ID[A] 2 gfs[s] C 25 C VGS[V] ID=f(VGS); VDS >2 ID RDS(on)max;parameter:Tj ID[A] gfs=f(id);tj=25 C 7 Rev.2.1,217119

8 OptiMOS TM PowerTransistor,6V Diagram9:Drainsourceonstateresistance 6. Diagram1:Typ.gatethresholdvoltage RDS(on)[mΩ] max typ VGS(th)[V] µa 5 µa Tj[ C] RDS(on)=f(Tj);ID=5A;VGS=1V Tj[ C] VGS(th)=f(Tj);VGS=VDS Diagram11:Typ.capacitances 1 4 Diagram12:Forwardcharacteristicsofreversediode C 175 C Ciss C[pF] Coss IF[A] Crss VDS[V] C=f(VDS);VGS=V;f=1MHz VSD[V] IF=f(VSD);parameter:Tj 8 Rev.2.1,217119

9 OptiMOS TM PowerTransistor,6V Diagram13:Avalanchecharacteristics 1 2 Diagram14:Typ.gatecharge C 1 C 25 C V 3 V 48 V IAV[A] VGS[V] tav[µs] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) Qgate[nC] VGS=f(Qgate);ID=5Apulsed;parameter:VDD Diagram15:Drainsourcebreakdownvoltage 7 Gate charge waveforms VBR(DSS)[V] Tj[ C] VBR(DSS)=f(Tj);ID=1mA 9 Rev.2.1,217119

10 OptiMOS TM PowerTransistor,6V 5PackageOutlines Figure1OutlinePGTDSON8,dimensionsinmm 1 Rev.2.1,217119

11 OptiMOS TM PowerTransistor,6V Figure2OutlineFootprint(TDSON8) 11 Rev.2.1,217119

12 OptiMOS TM PowerTransistor,6V RevisionHistory Revision:217119,Rev.2.1 Previous Revision Revision Date Subjects (major changes since last revision) Release of final version Update footnotes TrademarksofInfineonTechnologiesAG AURIX,C166,CanPAK,CIPOS,CoolGaN,CoolMOS,CoolSET,CoolSiC,CORECONTROL,CROSSAVE,DAVE,DIPOL,DrBlade, EasyPIM,EconoBRIDGE,EconoDUAL,EconoPACK,EconoPIM,EiceDRIVER,eupec,FCOS,HITFET,HybridPACK,Infineon, ISOFACE,IsoPACK,iWafer,MIPAQ,ModSTACK,myd,NovalithIC,OmniTune,OPTIGA,OptiMOS,ORIGA,POWERCODE, PRIMARION,PrimePACK,PrimeSTACK,PROFET,PROSIL,RASIC,REAL3,ReverSave,SatRIC,SIEGET,SIPMOS,SmartLEWIS, SOLIDFLASH,SPOC,TEMPFET,thinQ,TRENCHSTOP,TriCore. TrademarksupdatedAugust215 OtherTrademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: Publishedby InfineonTechnologiesAG 81726München,Germany 217InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics ( Beschaffenheitsgarantie ). Withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnoninfringementofintellectualpropertyrightsofanythirdparty. Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer sproductsandanyuseofthe productofinfineontechnologiesincustomer sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice( Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlifesupportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlifesupport,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. 12 Rev.2.1,217119