NCP5111PG. Half bridge Power Converters. MARKING DIAGRAMS. Features. Typical Applications ORDERING INFORMATION

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High Voltage, High and Low Side Driver The NCP is a high voltage power gate driver providing two outputs for direct drive of N channel power MOSFETs or IGBTs arranged in a half bridge configuration.

1 High Voltage, High and Low Side Driver The NCP is a high voltage power gate driver providing two outputs for direct drive of N channel power MOSFETs or IGBTs arranged in a half bridge configuration. It uses the bootstrap technique to ensure a proper drive of the high side power switch. Features High Voltage Range: up to 6 V dv/dt Immunity ± V/nsec Gate Drive Supply Range from V to V High and Low Drive Outputs Output Source / Sink Current Capability ma / ma 3.3 V and V Input Logic Compatible Up to V CC Swing on Input Pins Extended Allowable Negative Bridge Pin Voltage Swing to V for Signal Propagation Matched Propagation Delays between Both Channels One Input with Internal Fixed Dead Time (6 ns) Under V CC LockOut (UVLO) for Both Channels Pin to Pin Compatible with Industry Standards These are Pb Free Devices Typical Applications Half bridge Power Converters SOIC D SUFFIX CASE 7 PDIP P SUFFIX CASE 66 NCP A L or WL Y or YY W or WW G or MARKING DIAGRAMS NCP AWL YYWWG = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) P ALYW PINOUT INFORMATION VCC IN DRV_LO VBOOT DRV_HI BRIDGE NC ORDERING INFORMATION Device Package Shipping NCPPG NCPDRG PDIP (Pb Free) SOIC (Pb Free) Units / Rail / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, 6 February, 6 Rev. 6 Publication Order Number: NCP/D

2 Vbulk + C Vcc C3 NCP39 D U NCP Vcc VBOOT 7 IN DRV_HI 3 Bridge 6 DRV_LO NC C Q Q C6 Lf T D D L Out+ + C3 Out R D3 Figure. Typical Application Resonant Converter (LLC type) U Vbulk Vcc + C SG36 MC3 TL9 NCP6 C3 D U NCP Vcc VBOOT 3 IN DRV_HI Bridge 7 6 DRV_LO NC C Q C C6 T D D L Out+ + C3 Out Q R D3 U Figure. Typical Application Half Bridge Converter VCC VCC UV DETECT VBOOT PULSE TRIGGER LEVEL SHIFTER S Q R Q DRV_HI IN DEAD TIME GENERATION UV DETECT VCC BRIDGE DELAY DRV_LO Figure 3. Detailed Block Diagram

3 PIN DESCRIPTIONS Pin No. Pin Name Pin Function VCC Low side and main power supply IN Logic Input 3 Ground DRV_LO Low side gate drive output NC Not Connected 6 BRIDGE Bootstrap return or high side floating supply return 7 DRV_HI High side gate drive output VBOOT Bootstrap power supply MAXIMUM RATINGS Rating Symbol Value Unit V CC Main power supply voltage.3 to V V CC_transient Main transient power supply voltage: IV CC_max = ma during ms 3 V V BRIDGE VHV: High Voltage BRIDGE pin to 6 V V BRIDGE Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO V V BOOT V BRIDGE VHV: Floating supply voltage.3 to V V DRV_HI VHV: High side output voltage V BRIDGE.3 to V BOOT +.3 V DRV_LO Low side output voltage.3 to V CC +.3 V dv BRIDGE /dt Allowable output slew rate V/ns V IN Inputs IN. to V CC +.3 V V ESD Capability: HBM model (all pins except pins 6 7 ) Machine model (all pins except pins 6 7 ) Latchup capability per JEDEC JESD7 kv V R JA Power dissipation and Thermal characteristics PDIP : Thermal Resistance, Junction to Air SO : Thermal Resistance, Junction to Air T STG Storage Range to + C T J_max Maximum Operating Junction + C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 7 C/W 3

4 ELECTRICAL CHARACTERISTIC (V CC = V boot = V, V = V bridge, C < T J < C, Outputs loaded with nf) Rating Symbol T J C to C Min Typ Max OUTPUT SECTION Output high short circuit pulsed current V DRV = V, PW s (Note ) I DRVsource ma Output low short circuit pulsed current V DRV = Vcc, PW s (Note ) I DRVsink ma Output resistor (Typical C) Source R OH 3 6 Output resistor (Typical C) Sink R OL High level output voltage, V BIAS V I DRV_XX = ma V DRV_H.7.6 V Low level output voltage V I DRV_XX = ma V DRV_L..6 V DYNAMIC OUTPUT SECTION Turn on propagation delay (Vbridge = V) (Note ) t ON 7 7 ns Turn off propagation delay (Vbridge = V or V) (Notes and 3) t OFF 7 ns Output voltage rise time (from % to Vcc = V) with nf load tr 6 ns Output voltage fall time (from 9% to CC = V) with nf load tf 3 7 ns Propagation delay matching between the High side and the Low C (Note ) Units t 3 6 ns Internal fixed dead time (Note ) DT 6 ns INPUT SECTION Low level input voltage threshold V IN. V Input pull down resistor (V IN <. V) R IN k High level input voltage threshold V IN.3 V Logic input bias V IN = C I IN+ A Logic input bias V IN = C I IN. A SUPPLY SECTION Vcc UV Start up voltage threshold Vcc_stup V Vcc UV Shut down voltage threshold Vcc_shtdwn V Hysteresis on Vcc Vcc_hyst.3.7 V Vboot Start up voltage threshold reference to bridge pin (Vboot_stup = Vboot Vbridge) Vboot_stup V Vboot UV Shut down voltage threshold Vboot_shtdwn V Hysteresis on Vboot Vboot_shtdwn.3.7 V Leakage current on high voltage pins to (V BOOT = V BRIDGE = DRV_HI = 6 V) Consumption in active mode (Vcc = Vboot, fsw = khz and nf load on both driver outputs) I HV_LEAK A ICC ma Consumption in inhibition mode (Vcc = Vboot) ICC A Vcc current consumption in inhibition mode ICC3 A Vboot current consumption in inhibition mode ICC A. Parameter guaranteed by design.. T ON = T OFF + DT. 3. Turn off propagation Vbridge = 6 V is guaranteed by design.. See characterization curve for t parameters variation on the full range temperature.. Timing diagram definition see: Figure and Figure 6. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5 IN DRV_HI DRV_LO Note: DRV_HI output is in phase with the input. Figure. Input/Output Timing Diagram IN % % ton tr toff tf DRV_HI Dead Time % 9% 9% % toff tf Dead Time tr DRV_LO 9% ton 9% % ton = toff + DT % Figure. Timing Definitions IN % % toff_hi DRV_HI Dead Time % 9% toff_lo Dead Time DRV_LO 9% Matching Delay = toff_hi toff_lo Matching Delay = (toff_lo + DT) (toff_hi + DT) % Figure 6. Matching Propagation Delay

6 CHARACTERIZATION CURVES T ON, PROPAGATION DELAY (ns) T ON High Side T ON Low Side 6 Figure 7. Turn ON Propagation Delay vs. Supply Voltage (V CC = V BOOT ) T ON, PROPAGATION DELAY (ns) T ON Low Side T ON High Side 6 Figure. Turn ON Propagation Delay vs. 6 T OFF, PROPAGATION DELAY (ns) 6 T OFF High Side T OFF Low Side T OFF, PROPAGATION DELAY (ns) 6 T OFF Low & High Side 6 Figure 9. Turn OFF Propagation Delay vs. Supply Voltage (V CC = V BOOT ) 6 Figure. Turn OFF Propagation Delay vs. T ON, PROPAGATION DELAY (ns) BRIDGE PIN VOLTAGE (V) Figure. High Side Turn ON Propagation Delay vs. VBRIDGE Voltage T OFF PROPAGATION DELAY (ns) BRIDGE PIN VOLTAGE (V) Figure. High Side Turn OFF Propagation Delay vs. VBRIDGE Voltage 6

7 CHARACTERIZATION CURVES 6 6 T ON, RISETIME (ns) 6 t r High Side t r Low Side T ON, RISETIME (ns) 6 t r High Side t r Low Side 6 Figure 3. Turn ON Risetime vs. Supply Voltage (V CC = V BOOT ) 6 Figure. Turn ON Risetime vs. 6 T OFF, FALLTIME (ns) t f High Side t f Low Side T OFF, FALLTIME (ns) 3 t f Low Side t f High Side PROPAGATION DELAY MATCHING (ns) Figure. Turn OFF Falltime vs. Supply Voltage (V CC = V BOOT ) 6 Figure 7. Propagation Delay Matching Between High Side and Low Side Driver vs. DEAD TIME (ns) 6 Figure 6. Turn OFF Falltime vs Figure. Dead Time vs. 7

8 CHARACTERIZATION CURVES LOW LEVEL INPUT VOLTAGE THRESHOLD (V) Figure 9. Low Level Input Voltage Threshold vs. Supply Voltage (V CC = V BOOT ) LOW LEVEL INPUT VOLTAGE THRESHOLD (V) Figure. Low Level Input Voltage Threshold vs. HIGH LEVEL INPUT VOLTAGE THRESHOLD (V).. HIGH LEVEL INPUT VOLTAGE THRESHOLD (V).... LOGIC INPUT CURRENT ( A) Figure. High Level Input Voltage Threshold vs. Supply Voltage (V CC = V BOOT ) 6 Figure 3. Logic Input Current vs. Supply Voltage (V CC = V BOOT ) LOGIC INPUT CURRENT ( A). 6 Figure. High Level Input Voltage Threshold vs Figure. Logic Input Current vs.

9 CHARACTERIZATION CURVES LOGIC INPUT CURRENT ( A) LOGIC INPUT CURRENT ( A) 6 6 Figure. Logic Input Current vs. Supply Voltage (V CC = V BOOT ) 6 Figure 6. Logic Input Current vs.. LOW LEVEL OUTPUT VOLTAGE THRESHOLD (V) Figure 7. Low Level Output Voltage vs. Supply Voltage (V CC = V BOOT ) LOW LEVEL OUTPUT VOLTAGE (V) Figure. Low Level Output Voltage vs..6.6 HIGH LEVEL OUTPUT VOLTAGE THRESHOLD (V)... 6 Figure 9. High Level Output Voltage vs. Supply Voltage (V CC = V BOOT ) HIGH LEVEL OUTPUT VOLTAGE (V) Figure 3. High Level Output Voltage vs. 9

10 CHARACTERIZATION CURVES OUTPUT SOURCE CURRENT (ma) 3 3 I src Low Side I src High Side 6 Figure 3. Output Source Current vs. Supply Voltage (V CC = V BOOT ) OUTPUT SOURCE CURRENT (ma) 3 3 I src High Side I src Low Side 6 Figure 3. Output Source Current vs. OUTPUT SINK CURRENT (ma) 6 3 I src High Side I src Low Side OUTPUT SINK CURRENT (ma) 6 3 I src Low Side I src High Side 6 Figure 33. Output Sink Current vs. Supply Voltage (V CC = V BOOT ) 6 Figure 3. Output Sink Current vs. HIGH SIDE LEAKAGE CURRENT ON HV PINS TO ( A) HV PINS VOLTAGE (V) Figure 3. Leakage Current on High Voltage Pins (6 V) to Ground vs. V BRIDGE Voltage (V BRIGDE = V BOOT = VDRV_HI) LEAKAGE CURRENT ON HIGH VOLTAGE PINS (6 V) to ( A) 6 Figure 36. Leakage Current on High Voltage Pins (6 V) to Ground vs. (VBRIDGE = V BOOT = VDRV_HI = 6 V)

11 CHARACTERIZATION CURVES V BOOT SUPPLY CURRENT ( A) 6 VBOOT CURRENT SUPPLY ( A) 6 6 V BOOT, VOLTAGE (V) Figure 37. V BOOT Supply Current vs. Bootstrap Supply Voltage 6 Figure 3. V BOOT Supply Current vs. V CC SUPPLY CURRENT ( A) 6 V CC CURRENT SUPPLY A) 3 6 Figure 39. V CC Supply Current vs. V CC Supply Voltage 6 Figure. V CC Supply Current vs. UVLO STARTUP VOLTAGE (V) V CC UVLO Startup V BOOT UVLO Startup. 6 Figure. UVLO Startup Voltage vs. UVLO SHUTDOWN VOLTAGE (V) V BOOT UVLO Shutdown 7. 6 V CC UVLO Shutdown Figure. UVLO Shutdown Voltage vs.

12 CHARACTERIZATION CURVES I CC + I BOOT CURRENT SUPPLY (ma) C LOAD = nf/q = nc R GATE = R to R 3 6 SWITCHING FREQUENCY (khz) Figure 3. I CC Consumption vs. Switching Frequency with nc Load on Each V CC = V I CC + I BOOT CURRENT SUPPLY (ma) 3 3 C LOAD =. nf/q = 33 nc R GATE = R R GATE = R R GATE = R 3 6 SWITCHING FREQUENCY (khz) Figure. I CC Consumption vs. Switching Frequency with 33 nc Load on Each V CC = V I CC + I BOOT CURRENT SUPPLY (ma) 3 3 C LOAD = 3.3 nf/q = nc R GATE = R R GATE = R R GATE = R 3 6 SWITCHING FREQUENCY (khz) I CC + I BOOT CURRENT SUPPLY (ma) C LOAD = 6.6 nf/q = nc R GATE = R R GATE = R R GATE = R 3 6 SWITCHING FREQUENCY (khz) Figure. I CC Consumption vs. Switching Frequency with nc Load on Each V CC = V Figure 6. I CC Consumption vs. Switching Frequency with nc Load on Each V CC = V

13 PACKAGE DIMENSIONS LEAD PDIP CASE 66 ISSUE N NOTE A D D b TOP VIEW e/ e SIDE VIEW A E B A A L NOTE 3 C SEATING PLANE H eb X b END VIEW. M C A M B M NOTE 6 E END VIEW WITH LEADS CONSTRAINED M NOTE c NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS 3.. DIMENSIONS D, D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED. INCH.. DIMENSION E IS MEASURED AT A POINT. BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY.. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). INCHES MILLIMETERS DIM MIN MAX MIN MAX A..33 A..3 A b b.6 TYP. TYP C D D..3 E E e. BSC. BSC eb.3.9 L M 3

14 PACKAGE DIMENSIONS Y B X A S. (.) M Y M SOIC NB CASE 7 7 ISSUE AK K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 7 6 ARE OBSOLETE. NEW STANDARD IS 7 7. Z H G D C. (.) M Z Y S X S SEATING PLANE. (.) N X M SOLDERING FOOTPRINT* J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.7 BSC. BSC H.... J K M N.... S SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 7 USA Phone: or 3 36 Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 3 7 ON Semiconductor Website: Order Literature: For additional information, please contact your loca Sales Representative NCP/D

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