TISP61089HDM Overvoltage Protector

Transcription

1 *RoHS COMPLINT TISP089HDM DUL FORWRD-CONDUCTING P-GTE THYRISTOR PROGRMMBLE OVERVOLTGE PROTECTOR TISP089HDM Overvoltage Protector Intended for Use in GR-089-CORE Issue Compliant Line Cards Dual, Voltage-Programmable SLIC Protector Low m max. Gate Triggering Current Supports Battery Voltages Down to - V High 0 m min. Holding Current Rated for GR-089-CORE Issue Conditions GR-089-CORE Test Impulse Waveshape Section Test # /0 0/ , I PPSM Meets GR-089-CORE First Level.C. Power Fault Conditions GR-089-CORE I RMS Power Fault Duration Section..0 Test # s GR-089-CORE Second Level.C. Power Fault Conditions are Detailed in the pplications Information Section 8-SOIC (0 mil) Package (Top View) (Tip) K (Gate) G NC (Ring) K NC - No internal connection Terminal typical application names shown in parenthesis Device Symbol K G K 8 K (Tip) K (Ground) (Ground) (Ring) The negative protection voltage is controlled by the voltage, V GG, applied to the G terminal. SD-TISP-00-a MD-8SOIC(0)-00-b K K... UL Recognized Component How To Order Device Package Carrier Order s Marking Code Standard Quantity TISP089HDM 8-SOIC (0 mil) Embossed Tape Reeled TISP089HDMR-S 089H 000 Description The TISP089HDM is a dual forward-conducting buffered p-gate thyristor (SCR) overvoltage protector. It is designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The TISP089HDM limits voltages that exceed the SLIC supply rail voltage. The TISP089HDM parameters are specified to allow equipment compliance with Telcordia GR-089-CORE, Issue and ITU-T recommendations K.0, K. and K.. The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of -0 V to - V. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. The protection voltage will then track the negative supply voltage and the overvoltage stress on the SLIC is minimized. *RoHS Directive 00/9/EC Jan 00 including nnex MY 00 REVISED UGUST 00

2 TISP089HDM Overvoltage Protector Description (Continued) Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state condition. s the overvoltage subsides the high holding current of TISP089HDM SCR helps prevent d.c. latchup. The TISP089HDM is designed to be used with a pair of Bourns B0T fuses for overcurrent protection. Level power fault compliance requires the series overcurrent element to become open-circuit or high impedance. For equipment compliant to ITU-T recommendations K.0, K. or K. only, the series resistor value is set by the coordination requirements. For coordination with a 00 V limit GDT, a minimum series resistor value of. Ω is recommended. bsolute Maximum Ratings, T = C (Unless Otherwise Noted) Rating Symbol Value Unit Repetitive peak off-state voltage, V GK =0 V DRM -0 V Repetitive peak gate-cathode voltage, V K =0 V GKRM - V Non-repetitive peak impulse current (see Notes, and ) 0/000 µs (Telcordia GR-089-CORE, Issue ) 00 /0 µs (ITU-T K.0, K. & K., K. open-circuit voltage wave shape 0/00 µs) 0 0/0 µs (Telcordia GR-089-CORE, Issue ) I PPSM 00./0 µs voltage waveshape (Telcordia GR-089-CORE, Issue ), including Ω non-inductive resistor 00 /0 µs (Telcordia GR-089-CORE, Issue ) 00 Non-repetitive peak on-state current, 0 Hz / 0 Hz (see Notes,, and ) 0. s s s s 0 s 900 s Junction temperature T J -0 to +0 C Storage temperature range T stg - to +0 C NOTES:. Initially the device must be in thermal equilibrium with T J = C. The surge may be repeated after the device returns to its initial conditions.. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. dditionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Ratings are obtained by using the gate circuitry as shown in Fig... Rated currents only apply if pins & 8 (Tip) are connected together, pins & (Ring) are connected together and pins & (node) are connected together.. EI/JESD- environment and EI/JESD- high effective thermal conductivity test board (multi-layer) connected with 0. mm printed wiring track widths. I TSM Electrical Characteristics, T = C (Unless Otherwise Noted) Parameter Test Conditions Min Typ Max Unit I D Off-state current V D = V DRM, V GK = 0 V GK(BO) Gate-cathode impulse breakover voltage 0/000 µs, I TM = 00, V GG = -00 V /0 µs, I TM = 0, V GG = -00 V /0 µs, I TM = 00, V GG = -00 V (see Note ) T = C T = 8 C V F Forward voltage I F =, t W = 00 µs V V FRM Peak forward recovery voltage 0/000 µs, I F = 00, V GG = -00 V /0 µs, I F = 0, V GG = -00 V /0 µs, I F = 00, V GG = -00 V (see Note ) µ V V MY 00 REVISED UGUST 00

3 TISP089HDM Overvoltage Protector Electrical Characteristics, T = C (Unless Otherwise Noted) (Continued) Parameter Test Conditions Min Typ Max Unit I H Holding current I T =-, di/dt=/ms, V GG = -00 V -0 m I GKS Gate reverse current V GG =V GK =V GKRM, V K =0 T = C T = 8 C I GT Gate trigger current I T =-, t p(g) 0 µs, V GG = -00 V m V GT Gate-cathode trigger voltage I T =-, t p(g) 0 µs, V GG = -00 V. V C K Cathode-anode off-state capacitance f = MHz, V d = V rms, V D = -0 V, I G = 0 0 pf - -0 µ NOTE:. Voltage measurements should be made with an oscilloscope with limited bandwidth (0 MHz) to avoid high frequency noise. Thermal Characteristics, T = C (Unless Otherwise Noted) R θj NOTE Parameter Test Conditions Min Typ Max Unit Junction to ambient thermal resistance EI/JESD- PCB, EI/JESD- Environment, P TOT = W (See Note ) C/W. EI/JESD- high effective thermal conductivity test board (multi-layer) connected with 0. mm printed wiring track widths. Parameter Measurement Information +i Quadrant I I PPSM Forward Conduction Characteristic I FSM (= I TSM ) I F V F V GK(BO) -v V GG V D +v I D I (BO) I S I H V (BO) V S V T I T I TSM Quadrant III Switching Characteristic -i I PPSM PM-TISP-00-a Figure. Voltage-Current Characteristic Unless Otherwise Noted, ll Voltages are Referenced to the node MY 00 REVISED UGUST 00

4 TISP089HDM Overvoltage Protector Thermal Information NON-REPETITIVE PEK ON-STTE CURRENT vs CURRENT DURTION I TSM(t) - Non-Repetitive Peak On-State Current V GEN = 00 Vrms, 0/0 Hz t - Current Duration - s Figure. TI-TISP-00-a R GEN =. x V GEN /I TSM(t) EI/JESD- ENVIRONMENT EI/JESD- PCB, T = C SIMULTNEOUS OPERTION OF R ND T TERMINLS. MY 00 REVISED UGUST 00

5 TISP089HDM Overvoltage Protector PPLICTIONS INFORMTION SLIC Fuse SLIC PROTECTOR Tip Fa B0T Ring Fb B0T TISP 089HDM 0 kω.0 Ω D C 0 nf D -V BT I-TISP-00-b Figure. Line Protection with TISP089HDM Figure illustrates how a typical SLIC protection circuit may look for a TISP089HDM and a pair of Bourns Telefuse overcurrent protectors. This is a generic circuit that is designed to withstand both lightning surge testing and C power fault testing. s applications can differ, it is recommended you contact your Bourns representative for detailed applications guidance on your specific design. MY 00 REVISED UGUST 00

6 TISP089HDM Overvoltage Protector PPLICTIONS INFORMTION (Continued) 0 PEK C vs CURRENT DURTION I-TISP-00-a TYPICL TIME TO OPEN vs CURRENT I-TISP-00-a Peak 0 Hz / 0 Hz Current GR-089 First Level Tests TISP089HDM I TSM RMS Current B0T TISP089HDM t - Current Duration - s t - Current Duration - s Figure. Figure. GR-089-CORE Issue.C. Power Fault testing has been comprehended in the design of the TISP089HDM. For compliance, circuit designs must pass both First Level and Second Level.C. Power Fault testing. First Level Power Fault testing requires that the equipment shall not be damaged and continues to operate correctly without disruption to other parts of the system. In laboratory tests it has been shown that the circuit shown in Figure can pass these tests without damage. Figure shows the TISP089HDM I TSM rating to be above the level of GR-089-CORE First Level tests. Second Level Power Fault testing may result in the equipment becoming non-operational, but any component failure should not allow the equipment to become a hazard. The system should not burn, fragment, or become an electrical safety hazard. The test data in Figure illustrates that the TISP089HDM and the B0T are current coordinated, as the fuse interrupt time is shorter than the time it takes to damage the TISP089HDM package for a given current. MY 00 REVISED UGUST 00

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