LCP154DJF. Programmable transient voltage suppressor for SLIC protection. Description. Features. Benefits
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1 Programmable transient voltage suppressor for SLIC protection Description Datasheet - production data Features Programmable transient suppressor Wide negative firing voltage range: V Gn = V max. Low dynamic switching voltages: V FP and V DGL Low gate triggering current: I GT = 5 ma max. Peak pulse current: I PP = 1 A (1/1 µs) I PP = 15 A (5/31 µs) I PP = 5 A (2/1 µs) Holding current: I H = 15 ma min. This device has been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -V BAT through the gate. is specified to comply with ITU-T K2/21/45 and GR189-Core when associated with Cooper Bussmann Telecom Circuit Protector fuse TCP 1.25 A. is packaged in a PowerFLAT 5x6 to meet IEC/UL 695 clearance requirements. Figure 1. Functional diagram Benefits Trisil is not subject to ageing and provides a fail safe mode in short circuit for a better level of protection. Trisils are used to ensure equipment meets various standards such as UL695, IEC 695 / CSA C22.2, UL1459, TIA-968-A (formerly FCC part 68) Trisils have UL94 V approved resin (Trisils are UL497B approved [file: E136224]). TM: Trisil is a trademark of STMicroelectronics September 215 DocID28213 Rev 1 1/13 This is information on a product in full production.
2 Characteristics 1 Characteristics Table 1. Standards compliance Standard Peak surge voltage (V) Voltage waveform Required peak current (A) Current waveform Minimum serial resistor to meet standard ( Ω ) GR-189 Core First level GR-189 Core Second level GR-189 Core Intra-building ITU-T-K2/K21 ITU-T-K2 (IEC ) IEC TIA-968-A, lightning surge type A TIA-968-A, lightning surge type B /1 µs 1/1 µs 5 1 2/1 µs 1/1 µs 5 2/1 µs 5 2/1 µs 15 2/1 µs 1 2/1 µs /7 µs 1/6 ns 1/7 µs 1.2/5 µs 1/16 µs 1/56 µs /31 µs ESD contact discharge ESD air discharge /31 µs 8/2 µs 1/16 µs 1/56 µs 1 9/72 µs 25 5/32 µs 2/13 DocID28213 Rev 1
3 Characteristics Table 2. Absolute ratings (T amb = 25 C) Symbol Parameter Value Unit I PP Peak pulse current (1) I TSM Non repetitive surge peak on-state current (5 Hz sinusoidal) (1) 1/1 µs 8/2 µs 1/56 µs 5/31 µs 1/16 µs 1/2 µs 2/1 µs t = 1 ms t =.2 s t = 1 s t = 2 s t = 15 min t = 3 min 1. The rated current values may be applied either to the RING to GND or to the Tip to GND terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the GND terminal current will be twice the rated current value of an individual terminal pair) V GN Negative battery voltage -175 V T stg T j Storage temperature range Operating junction temperature range to to +15 T L Maximum lead temperature for soldering during 1 s. 26 C A A C Figure 2. Electrical characteristics (definitions) Symbol Parameter I GT = Gate triggering current V FP = Peak forward voltage LINE / GND V GT = Gate triggering voltage V F = Forward drop voltage LINE /GND I RG = Reverse leakage current GATE / LINE I H = Holding current V RG = Reverse voltage GATE / LINE V DGL = Dynamic switching voltage GATE / LINE I PP = Peak pulse current I R = Breakdown current V F = Forward drop voltage LINE / GND C = Capacitance LINE /GND VR I VF IR IH V IPP DocID28213 Rev 1 3/13 13
4 Characteristics Figure 3. Pulse waveform Table 3. Parameters (T amb = 25 C unless otherwise specified) Symbol Test conditions Min Typ Max Unit I GT V LINE = -48 V.1 5 ma I H V Gn = -48 V 15 ma V GT (1) at I GT 2.5 V I RG V DGL (1) V RG = -175 V V RG = -175 V V Gn = -48 V (1) 1/7 µs 2/1 µs T j = 25 C T j = 85 C I PP = 15 A I PP = 2 A V F I F = 5 A t = 5 µs 3 V V FP(I) 1/7 µs 2/1 µs V I Gn / LINE = -1 V V LINE = -175 V R V Gn / LINE = -1 V V LINE = -175 V C V LINE = -5 V, V RMS = 1 V, f = 1 MHz V LINE = -2 V, V RMS = 1 V, f = 1 MHz I pp = 15 A I pp = 2 A T j = 25 C T j = 85 C C G Gate decoupling capacitance 1 22 nf 1. The oscillations with a time duration lower than 5 ns are not taken into account µa V V µa pf 4/13 DocID28213 Rev 1
5 Technical information 2 Technical information Figure 4. Example of PCB layout based on protection To line side >2 mm To SLIC side GND 1 nf GND Figure 4 shows the classical PCB layout used to optimize line protection. The 2 mm distance is used to comply with IEC/UL 695 clearance requirements. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows minimization of the dynamic breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP Gate pin and from the reference ground track (or plan). The schematics of Figure 5 give the topology used to protect all SLICs according to ITU-T K2/21/45 and GR189-Core. Figure 5. Protection of high voltage SLIC DocID28213 Rev 1 5/13 13
6 Technical information Figure 6. Surge peak current versus duration Figure 7. Relative variation of holding current versus junction temperature 6/13 DocID28213 Rev 1
7 Package information 3 Package information Epoxy meets UL94, V In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID28213 Rev 1 7/13 13
8 Package information 3.1 PowerFLAT 5x6 package information Figure 8. PowerFLAT 5x6 package outline 8/13 DocID28213 Rev 1
9 Package information Ref Table 4. PowerFLAT 5x6 mechanical data Millimeters Dimensions Inches Min. Typ. Max. Min. Typ. Max. A A A b D E D E e L K M N O P Q R DocID28213 Rev 1 9/13 13
10 Package information Figure 9. PowerFLAT 5x6 recommended footprint (all dimensions are in mm.) 1/13 DocID28213 Rev 1
11 Package information Figure 1. Marking DocID28213 Rev 1 11/13 13
12 Ordering information 4 Ordering information Table 5. Ordering information Order code Marking Package Weight Base qty Delivery mode CP154 PowerFLAT 5x6 91 mg 3 Tape and reel 5 Revision history Table 6. Document revision history Date Revision Changes 25-Sep First issue. 12/13 DocID28213 Rev 1
13 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 215 STMicroelectronics All rights reserved DocID28213 Rev 1 13/13 13
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