MUN5311DW1, NSBC114EPDXV6, NSBC114EPDP6 Complementary Bias Resistor Transistors R1 = 10 k, R2 = 10 k

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MUN53W, NSB4EPXV6, NSB4EPP6 omplementary Bias Resistor Transistors R = k, R2 = k NPN and PNP Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to

1 MUN53W, NSB4EPXV6, NSB4EPP6 omplementary Bias Resistor Transistors R = k, R2 = k NPN and PNP Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. Features Simplifies ircuit esign Reduces Board Space Reduces omponent ount S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and ontrol hange Requirements; AE-Q Qualified and PPAP apable* These evices are Pb-Free, Halogen Free/BFR Free and are RoHS ompliant MAXIMUM RATINGS (T A = both polarities Q (PNP) & Q 2 (NPN), unless otherwise noted) (3) (4) Q PIN ONNETIONS R 2 R (5) (2) R MARKING IAGRAMS SOT363 ASE 49B R 2 6 Q 2 () (6) M Rating Symbol Max Unit ollector-base Voltage V BO 5 ollector-emitter Voltage V EO 5 ollector urrent ontinuous I madc Input Forward Voltage V IN(fwd) 4 Input Reverse Voltage V IN(rev) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORERING INFORMATION evice Package Shipping MUN53WTG, SOT363 3,/Tape & Reel SMUN53WTG* MUN53WT2G, SMUN53WT2G* SOT363 3,/Tape & Reel SMUN53WT3G SOT363,/Tape & Reel NSB4EPXV6TG, SOT563 4,/Tape & Reel NSVB4EPXV6TG* SOT563 ASE 463A SOT963 ASE 527A M L M /L = Specific evice ode M = ate ode* = Pb-Free Package (Note: Microdot may be in either location) *ate ode orientation may vary depending upon manufacturing location. Semiconductor omponents Industries, LL, 24 July, 28 Rev. 4 Publication Order Number: T4EP/

2 MUN53W, NSB4EPXV6, NSB4EPP6 ORERING INFORMATION evice Package Shipping NSB4EPXV6T5G SOT563 8,/Tape & Reel NSB4EPP6T5G SOT963 8,/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8/. THERMAL HARATERISTIS MUN53W (SOT363) ONE JUNTION HEATE Total evice issipation T A = (Note ) erate above (Note ) (Note ) Junction to Ambient MUN53W (SOT363) BOTH JUNTION HEATE (Note 3) Total evice issipation T A = (Note ) erate above (Note ) Junction to Ambient (Note ) Junction to Lead (Note ) haracteristic Symbol Max Unit P R JA P R JA R JL Junction and Storage Temperature Range T J, T stg 55 to +5 NSB4EPXV6 (SOT563) ONE JUNTION HEATE Total evice issipation T A = (Note ) erate above (Note ) Junction to Ambient (Note ) NSB4EPXV6 (SOT563) BOTH JUNTION HEATE (Note 3) Total evice issipation T A = (Note ) erate above (Note ) Junction to Ambient (Note ) P R JA 35 P 5 4. R JA 25 Junction and Storage Temperature Range T J, T stg 55 to +5 NSB4EPP6 (SOT963) ONE JUNTION HEATE Total evice issipation T A = (Note 4) erate above (Note 4) Junction to Ambient (Note 4) NSB4EPP6 (SOT963) BOTH JUNTION HEATE (Note 3) Total evice issipation T A = (Note 4) erate above (Note 4) P R JA P mw mw mw mw MW MW 2

3 MUN53W, NSB4EPXV6, NSB4EPP6 THERMAL HARATERISTIS haracteristic NSB4EPP6 (SOT963) BOTH JUNTION HEATE (Note 3) Junction to Ambient (Note 4) Symbol Max R JA Junction and Storage Temperature Range T J, T stg 55 to +5. Minimum Pad. 2. Inch Pad. 3. Both junction heated values assume total power is sum of two equally powered channels. 4. mm 2, oz. copper traces, still air mm 2, oz. copper traces, still air. Unit 3

4 MUN53W, NSB4EPXV6, NSB4EPP6 ELETRIAL HARATERISTIS (T A = both polarities Q (PNP) & Q 2 (NPN), unless otherwise noted) haracteristic Symbol Min Typ Max Unit OFF HARATERISTIS ollector-base utoff urrent I BO nadc (V B =5V, I E =) ollector-emitter utoff urrent (V E =5V, I B =) Emitter-Base utoff urrent (V EB = 6. V, I =) ollector-base Breakdown Voltage (I = A, I E =) ollector-emitter Breakdown Voltage (Note 6) (I = 2. ma, I B =) ON HARATERISTIS urrent Gain (Note 6) (I = 5. ma, V E =V) ollector-emitter Saturation Voltage (Note 6) (I = ma, I B =.3 ma) Input Voltage (Off) (V E = 5. V, I = A) (NPN) (V E = 5. V, I = A) (PNP) Input Voltage (On) (V E =.2 V, I = ma) (NPN) (V E =.2 V, I = ma) (PNP) Output Voltage (On) (V = 5. V, V B = 2.5 V, R L =. k ) Output Voltage (Off) (V = 5. V, V B =.5 V, R L =. k ) I EO 5 I EBO.5 V (BR)BO 5 V (BR)EO 5 h FE 35 6 V E(sat).25 V i(off) V i(on) V OL.2 V OH 4.9 Input Resistor R 7. 3 k Resistor Ratio R /R Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 6. Pulsed ondition: Pulse Width = 3 ms, uty ycle 2%. nadc madc V 4 P, POWER ISSIPATION (mw) () (2) (3) () SOT363;.. Inch Pad (2) SOT563; Minimum Pad (3) SOT963; mm 2, oz. opper Trace AMBIENT TEMPERATURE ( ) Figure. erating urve 4

5 MUN53W, NSB4EPXV6, NSB4EPP6 TYPIAL HARATERISTIS NPN TRANSISTOR MUN53W, NSB4EPXV6 V E(sat), OLLETOREMITTER VOLTAGE (V) I /I B = T A = Figure 2. V E(sat) vs. I h FE, URRENT GAIN V E = V T A = 75 Figure 3. urrent Gain ob, OUTPUT APAITANE (pf) f = khz I E = A T A =.. T A = 75 V O = 5 V V R, REVERSE VOLTAGE (V) Figure 4. Output apacitance Figure 5. Output urrent vs. Input Voltage T A = 75 V O =.2 V Figure 6. Input Voltage vs. Output urrent 5

6 MUN53W, NSB4EPXV6, NSB4EPP6 TYPIAL HARATERISTIS PNP TRANSISTOR MUN53W, NSB4EPXV6 V E(sat), OLLETOREMITTER VOLTAGE (V) I /I B = V E = V T A = Figure 7. V E(sat) vs. I h FE, URRENT GAIN T A =75 Figure 8. urrent Gain ob, OUTPUT APAITANE (pf) V R, REVERSE VOLTAGE (V) f = khz l E = A T A = T A = V O = 5 V Figure 9. Output apacitance Figure. Output urrent vs. Input Voltage V O =.2 V T A = Figure. Input Voltage vs. Output urrent 6

7 MUN53W, NSB4EPXV6, NSB4EPP6 TYPIAL HARATERISTIS NPN TRANSISTOR NSB4EPP6 V E(sat), OLLETOREMITTER VOLTAGE (V).. I /I B = h FE, URRENT GAIN. V E = V 5 Figure 2. V E(sat) vs. I Figure 3. urrent Gain ob, OUTPUT APAITANE (pf) f = khz I E = A T A =. 5 V O = 5 V V R, REVERSE VOLTAGE (V) Figure 4. Output apacitance Figure 5. Output urrent vs. Input Voltage. 5 2 V O =.2 V Figure 6. Input Voltage vs. Output urrent 7

8 MUN53W, NSB4EPXV6, NSB4EPP6 TYPIAL HARATERISTIS PNP TRANSISTOR NSB4EPP6 V E(sat), OLLETOREMITTER VOLTAGE (V).. I /I B = h FE, URRENT GAIN. 5 V E = V Figure 7. V E(sat) vs. I Figure 8. urrent Gain ob, OUTPUT APAITANE (pf) f = khz I E = A T A =. 5 V O = 5 V V R, REVERSE VOLTAGE (V) Figure 9. Output apacitance Figure 2. Output urrent vs. Input Voltage 5. 2 V O =.2 V Figure 2. Input Voltage vs. Output urrent 8

9 MUN53W, NSB4EPXV6, NSB4EPP6 PAKAGE IMENSIONS E 2X bbb H e 6X ccc A B TOP VIEW SIE VIEW A 2X E aaa H aaa 2X 3 TIPS 6X b ddd M A2 A L2 SEATING PLANE S88/S76/SOT363 ASE 49B2 ISSUE Y A-B ETAIL A H L ETAIL A EN VIEW GAGE PLANE c NOTES:. IMENSIONING AN TOLERANING PER ASME Y4.5M, ONTROLLING IMENSION: MILLIMETERS. 3. IMENSIONS AN E O NOT INLUE MOL FLASH, PROTRUSIONS, OR GATE BURRS. MOL FLASH, PROTRU- SIONS, OR GATE BURRS SHALL NOT EXEE.2 PER EN. 4. IMENSIONS AN E AT THE OUTERMOST EXTREMES OF THE PLASTI BOY AN ATUM H. 5. ATUMS A AN B ARE ETERMINE AT ATUM H. 6. IMENSIONS b AN c APPLY TO THE FLAT SETION OF THE LEA BETWEEN.8 AN.5 FROM THE TIP. 7. IMENSION b OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE.8 TOTAL IN EXESS OF IMENSION b AT MAXIMUM MATERIAL ONI- TION. THE AMBAR ANNOT BE LOATE ON THE LOWER RAIUS OF THE FOOT. MILLIMETERS IM MIN NOM MAX A. A.. INHES MIN NOM MAX A b E E e.65 BS.26 BS L L2.5 BS.6 BS aaa.5.6 bbb.3.2 ccc..4 ddd..4 REOMMENE SOLERING FOOTPRINT* 6X.3 6X PITH IMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 9

10 MUN53W, NSB4EPXV6, NSB4EPP6 PAKAGE IMENSIONS SOT563, 6 LEA ASE 463A ISSUE G X A L NOTES:. IMENSIONING AN TOLERANING PER ANSI Y4.5M, ONTROLLING IMENSION: MILLIMETERS 3. MAXIMUM LEA THIKNESS INLUES LEA FINISH THIKNESS. MINIMUM LEA THIKNESS IS THE MINIMUM THIKNESS OF BASE MATERIAL e E Y b 65 PL.8 (.3) M X Y H E MILLIMETERS INHES IM MIN NOM MAX MIN NOM MAX A b E e.5 BS.2 BS L H E SOLERING FOOTPRINT* SALE 2: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.

11 MUN53W, NSB4EPXV6, NSB4EPP6 PAKAGE IMENSIONS SOT963 ASE 527A ISSUE E TOP VIEW e X Y E 6X L A SIE VIEW H E NOTES:. IMENSIONING AN TOLERANING PER ASME Y4.5M, ONTROLLING IMENSION: MILLIMETERS 3. MAXIMUM LEA THIKNESS INLUES LEA FINISH THIKNESS. MINIMUM LEA THIKNESS IS THE MINIMUM THIKNESS OF BASE MATERIAL. 4. IMENSIONS AN E O NOT INLUE MOL FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS IM MIN NOM MAX A b E e.35 BS H E L.9 REF L X L2 BOTTOM VIEW 6X b.8 X Y REOMMENE MOUNTING FOOTPRINT* 6X.2 6X.35 PAKAGE OUTLINE.2.35 PITH IMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are trademarks of Semiconductor omponents Industries, LL dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patentmarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FA lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution enter for ON Semiconductor 952 E. 32nd Pkwy, Aurora, olorado 8 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative T4EP/

MUN5313DW1, NSBC144EPDXV6, NSBC144EPDP6. Complementary Bias Resistor Transistors R1 = 47 k, R2 = 47 k

MUN5313DW1, NSBC144EPDXV6, NSBC144EPDP6. Complementary Bias Resistor Transistors R1 = 47 k, R2 = 47 k MUN533W, NSB44EPXV6, NSB44EPP6 omplementary Bias Resistor Transistors R = 47 k, R2 = 47 k NPN and PNP Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to