FDB5800 N-Channel Logic Level PowerTrench MOSFET

Transcription

1 FDB58 N-Channel Logic Level PowerTrench MOSFET 6 V, 8 A, 6 mω Features R DS(on) = 4.6 mω (Typ.), V GS = 1 V, I D = 8 A High Performance Trench Technology for Extermly Low R DS(on) Low Gate Charge High Power and Current Handing Capability RoHs Compliant G S D D 2 -PAK Description G D November 213 This N-Channel MOSFET is produced using Fairchild Semiconductor s advanced PowerTrench process that has been tailored to minimize the on-state resistance while maintaining superior switching performance. Applications Power tools Motor drives and Uninterruptible Power Supplies S Absolute Maximum Ratings T C = 25 o C unless otherwise noted. Symbol Parameter FDB58 Unit V DSS Drain to Source Voltage 6 V V GS Gate to Source Voltage ±2 V Drain Current - Continuous (T C < 12 o C, V GS = 1 V) 8 A I D - Continuous (T C < 9 o C, V GS = 5 V) 8 A - Continuous (T amb = 25 o C, V GS = 1V, with R θja = 43 o C/W) 14 A - Pulsed Figure 4 A E AS Single Pulse Avalanche Energy (Note 1) 652 mj - Power Dissipation 242 W P D - Derate above 25 o C 1.61 W/ o C T J, T STG - Operating and Storage Temperature -55 to 175 o C Thermal Characteristics R θjc Thermal Resistance Junction to Case TO-263, Max..62 o C/W R θja Thermal Resistance Junction to Ambient TO-263, Max. ( Note 2) 62.5 o C/W R θja Thermal Resistance Junction to Ambient TO-263, 1in 2 copper pad area 43 o C/W 1

2 Package Marking and Ordering Information Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity FDB58 FDB58 D 2 -PAK Tape and Reel 33 mm 24 mm 8 units Electrical Characteristics T C = 25 o C unless otherwise noted. Symbol Parameter Test Conditions Min. Typ. Max. Off Characteristics B VDSS Drain to Source Breakdown Voltage I D = 25 µa, V GS = V V I DSS Zero Gate Voltage Drain Current V DS = 48 V V GS = V T C = 15 o C I GSS Gate to Source Leakage Current V GS = ±2 V - - ± na On Characteristics V GS(TH) Gate to Source Threshold Voltage V GS = V DS, I D = 25 µa V r DS(ON) Drain to Source On Resistance Dynamic Characteristics I D = 8 A, V GS = 1 V I D = 8 A, V GS = 4.5 V I D = 8 A, V GS = 5 V I D = 8 A, V GS = 1 V, T J = 175 o C C ISS Input Capacitance pf V DS = 15 V, V GS = V, C OSS Output Capacitance pf f = 1 MHz C RSS Reverse Transfer Capacitance pf R G Gate Resistance V GS =.5 V, f = 1 MHz Ω Q g(tot) Total Gate Charge at 1V V GS = V to 1 V Q g(5) Total Gate Charge at 5V V GS = V to 5 V nc Q V DD = 3 V g(th) Threshold Gate Charge V GS = V to 1 V nc I D = 8 A Q gs Gate to Source Gate Charge nc I g = 1. ma Q gs2 Gate Charge Threshold to Plateau nc Unit µa mω nc Q gd Gate to Drain Miller Charge nc Switching Characteristics (V GS = 5V) t ON Turn-On Time ns t d(on) Turn-On Delay Time ns t r Rise Time V DD = 3 V, I D = 8 A ns t d(off) Turn-Off Delay Time V GS = 5 V, R GS = 2 Ω ns t f Fall Time ns t OFF Turn-Off Time ns Drain-Source Diode Characteristics V SD Source to Drain Diode Voltage I SD = 8 A V I SD = 4 A V t r Reverse Recovery Time I SD = 6 A, di SD /dt = A/µs ns Q Reverse Recovered Charge I SD = 6 A, di SD /dt = A/µs nc SD Notes: 1: Starting T J = 25 C, L = 1mH, I AS = 36A, V DD = 54V, V GS = 1V. 2: Pulse width = s. 2

3 Typical Characteristics T C = 25 C unless otherwise noted POWER DISSIPATION MULTIPLIER Figure 1. Z θjc, NORMALIZED THERMAL IMPEDANCE T C, CASE TEMPERATURE ( o C) Normalized Power Dissipation vs Case Temperature DUTY CYCLE - DESCENDING ORDER I D, DRAIN CURRENT (A) Figure 2. R θjc =.62 C/W CURRENT LIMITED BY PACKAGE VGS = 5V VGS =1V T C, CASE TEMPERATURE ( C) Maximum Continuous Drain Current vs Case Temperature NOTES: DUTY FACTOR: D = t 1 /t 2 SINGLE PULSE PEAK T J = P DM x R θjc + T C t, RECTANGULAR PULSE DURATION (s) P DM t 1 t 2 Figure 3. Normalized Maximum Transient Thermal Impedance I DM, PEAK CURRENT (A) V GS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION T C = 25 o C FOR TEMPERATURES ABOVE 25 o C DERATE PEAK CURRENT AS FOLLOWS: I = I T C t, PULSE WIDTH (s) Figure 4. Peak Current Capability 3

4 Typical Characteristics T C = 25 C unless otherwise noted I D, DRAIN TCURRENT (A) I D, DRAIN TCURRENT (A) Figure OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) SINGLE PULSE T J = MA o X RATED T C = 25 C 1µs µs 1ms 1ms ms DC 1 1 V DS, DRAIN TO SOURCE VOLTAGE (V) Forward Bias Safe Operating Area PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V DS = 6V T A = 125 o C 4 T A = 25 o C 2 T A = -55 o C V GS, GATE TO SOURCE VOLTAGE (V) I AS, AVALANCHE CURRENT (A) 5 1 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 I D, DRAIN TCURRENT (A) Figure 6. If R = t AV = (L)(I AS )/(1.3*RATED BV DSS - V DD ) If R t AV = (L/R)ln[(I AS *R)/(1.3*RATED BV DSS - V DD ) +1] STARTING T J = 15 o C STARTING T J = 25 o C t AV, TIME IN AVALANCHE (ms) Unclamped Inductive Switching Capability 5.V 1V 4.5V 4.V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 3.5V 3.V V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics R DS(ON), ON-RESISTANCE(OHM) I D = 2A T A = 25 o C PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T A = 175 o C NORMALIZED DRAIN TO SOURCE ON-RESISTANCE I D = 8A V GS = 1V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS, GATE TO SOURCE VOLTAGE (V) T J, AMBIENT TEMPERATURE ( o C) 2 Figure 9. On-Resistance Variation vs Gate-to- Figure 1. Normalized Drain to Source On 4

5 Typical Characteristics T C = 25 C unless otherwise noted NORMALIZED GATE THRESHOLD VOLTAGE T J, AMBIENT TEMPERATURE ( o C) Figure 11. CAPACITANCE (pf) 2 V GS = V DS I D = 25µA Normalized Gate Threshold Voltage vs Junction Temperature f = 1MHz V GS = V C RSS C ISS C OSS NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE V GS, GATE- SOURCE VOLTAGE I D = 25µA T J, AMBIENT TEMPERATURE ( o C) Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature VDD =3V WAVEFORMS IN ASCENDING ORDER: ID = 8A ID = 1A V DS, DRAIN TO SOURCE VOLTAGE (V) Q g, GATE CHARGE (nc) Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Current 5

6 Mechanical Dimensions Figure 15. TO263 (D 2 PAK), Molded, 2-Lead, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: 6

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