DATASHEET HM-65162/883. Features. Description. Ordering Information. Pinouts. 2kx8 Asynchronous CMOS Static RAM. FN3001 Rev.1.

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1 DATASHT HM-65162/3 2kx Asynchronous CMOS Static RAM Features This Circuit is Processed in Accordance to MIL-STD- 3 and is Fully Conformant Under the Provisions of Paragraph Fast Access /90ns Max Low Standby A Max Low Operating mA Max Data Retention at 2.0V A Max TTL Compatible Inputs and Outputs JDC Approved Pinout (216, 6116 Type) No Clocks or Strobes Required ide Temperature Range o C to qual Cycle and Access Single 5V Supply ated Inputs - No Pull-Up or Pull-Down Resistors Required Description FN3001 Rev.1.00 The HM-65162/3 is a CMOS 204 x Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JDC 24 pin DIP, and 32 pad -bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and PROMs. The HM-65162/3 is ideally suited for use in microprocessor based systems with its -bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. ated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors. Ordering Information 0ns/20 A 90ns/40 A 90ns/300 A TMP. RAN PACKA PK. NO. HM B/3 HM /3 HM C/3-55 o C to 125 o C CRDIP 4.6 HM B/3 HM / o C to 125 o C CLCC J32.A Pinouts HM-65162/3 (CRDIP) TOP VI HM-65162/3 (CLCC) TOP VI A A A9 0 DQ DQ1 DQ2 ND DQ5 DQ4 DQ DQ1 DQ2 ND DQ3 DQ4 DQ5 A A A9 0 PIN - 0 VSS/ND - DSCRIPTION No Connect Address Input Chip nable/power Down round Data In/Data Out Power (+5V) DQ6 rite nable Output nable FN3001 Rev.1.00 Page 1 of 9

2 Functional Diagram A RO RO 12 X 12 ADDRSS DCODR 12 MMORY ARRAY BUFFR A A 1 OF 12 COLUMN DCODR AND DATA INPUT / OUTPUT (X) THRU 4 A 4 A COLUMN ADDRSS BUFFR A A9 0 FN3001 Rev.1.00 Page 2 of 9

3 Absolute Maximum Ratings Supply Voltage V Input, Output or I/O Voltage ND -0.3V to +0.3V Typical Derating Factor mA/MHz Increase in ICCOP SD Classification Class 1 Thermal Information Thermal Resistance JA JC CRDIP Package o C/ o C/ CLCC Package o C/ 12 o C/ Maximum Storage Temperature Range o C to +150 o C Maximum Junction Temperature o C Maximum Lead Temperature (Soldering 10s) o C Die Characteristics ate Count ates CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range V to + Operating Temperature Range o C to Input Low Voltage V to +0.V Chip nable High/Low ns (Min) Input High Voltage V to Data Retention Supply Voltage V to 4.5V Input Rise and Fall ns Max TABL /3 DC LCTRICAL PRFORMA SPCIFICATIONS Device uaranteed and 100% Tested PARAMTR High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Input Leakage Standby Supply Standby Supply Operating Supply nable Supply Data Retention Supply SYMBOL (NOT 1) CONDITIONS ROUP A SUBROUPS TMPRATUR MIN LIMITS VOH1 = 4.5V, IO = -1.0mA 1, 2, 3-55 o C T A V VOL = 4.5V, IO = 4.0mA 1, 2, 3-55 o C T A V IIOZ II ICCSB1 ICCSB ICCOP ICCN ICCDR =, = 2.2V, or = 2.2V, VI/O = ND or =, VI = ND or HM-65162B/3, IO = 0mA, =, = -0.3V HM-65162/3, IO = 0mA, =, = - 0.3V HM-65162C/3, IO = 0mA, =, = - 0.3V =, IO = 0mA, = 2.2V =, =, (Note 2), f = 1MHz, = 0.V =, IO = 0mA, = 0.V HM-65162B/3, IO = 0mA, = 2.0V, = - 0.3V HM-65162/3, IO = 0mA, = 2.0V, = - 0.3V HM-65162C/3, IO = 0mA, = 2.0V, = - 0.3V MAX UNITS 1, 2, 3-55 o C T A A 1, 2, 3-55 o C T A A 1, 2, 3-55 o C T A - 50 A 1, 2, 3-55 o C T A A 1, 2, 3-55 o C T A A 1, 2, 3-55 o C T A - ma 1, 2, 3-55 o C T A - 0 ma 1, 2, 3-55 o C T A - 0 ma 1, 2, 3-55 o C T A - 20 A 1, 2, 3-55 o C T A - 40 A 1, 2, 3-55 o C T A A Functional Test FT = 4.5V (Note 3), A, B -55 o C T A NOTS: 1. All voltages referenced to device ND. 2. Input pulse levels: 0.V to - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time by 0.15ns per pf. 3. TAVQV = TLQV + TAVL. FN3001 Rev.1.00 Page 3 of 9

4 Device uaranteed and 100% Tested. TABL 2. HM-65162/3 AC LCTRICAL PRFORMA SPCIFICATIONS LIMITS PARAMTR SYMBOL (NOTS 1, 2) CONDITIONS ROUP A SUB- ROUPS TMPRA- TUR HM-65162B /3 HM /3 HM-65162C /3 MIN MAX MIN MAX MIN MAX UNITS Read/rite/ Cycle Address Access Chip nable Access Output nable Access Chip Selection to nd of rite Address Setup rite nable Pulse rite rite nable Read Setup Data Setup (1) TAVAX = 4.5V (2) TAVQV = 4.5V (3) TLQV = 4.5V (5) TLQV = 4.5V (11) TLH = 4.5V (12) TAVL = 4.5V (13) TLH = 4.5V (14) THAX = 4.5V (1) TDVH = 4.5V 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns 9, 10, ns Data Hold (1) THDX = 4.5V 9, 10, ns rite nable Pulse Setup Chip nable Data Setup Address Valid to nd of rite (20) TLH = 4.5V (21) TDVH = 4.5V (22) TAVH = 4.5V 9, 10, ns 9, 10, ns 9, 10, ns NOTS: 1. All voltages referenced to device ND. 2. Input pulse levels: 0.V to -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pf. 3. TAVQV = TLQV + TAVL. FN3001 Rev.1.00 Page 4 of 9

5 TABL 3. HM-65162/3 LCTRICAL PRFORMA SPCIFICATIONS, AC AND DC LIMITS HM B/3 HM /3 HM C/3 PARAMTR SYMBOL CONDITIONS NOTS TMPRATUR MIN MAX MIN MAX MIN MAX UNITS Input Capacitance CIN = Open, F = 1MHz, All Measurements Referenced To Device round 1, o C pf 1, o C pf I/O Capacitance CI/O = Open, F = 1MHz, All Measurements Referenced To Device round 1, o C pf 1, o C pf Chip nable to Output ON (4) TLQX = 4.5V and ns Output nable to Output ON (6) TLQX = 4.5V and ns Chip nable High to Output In High Z () THQZ = 4.5V and ns Output Disable to Output in High Z () THQZ = 4.5V and ns Output Hold from Address Change (9) TAVQX = 4.5V and ns rite nable to Output in High Z (16) TLQZ = 4.5V and ns rite nable High to Output ON (19) THQX = 4.5V and ns Output High Voltage VOH2 = 4.5V, IO = -100 A - 0.4V V V - V NOTS: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to LCC device types only. TABL 4. APPLICABL SUBROUPS CONFORMA ROUPS MTHOD SUBROUPS Initial Test 100%/ Interim Test 100%/5004 1,, 9 PDA 100%/ Final Test 100%/5004 2, 3,, A, B, 10, 11 roup A Samples/5005 1, 2, 3,, A, B, 9, 10, 11 roups C & D Samples/5005 1,, 9 FN3001 Rev.1.00 Page 5 of 9

6 Timing aveforms (2) TAVQV (1) TAVAX ADDRSS () THQZ (6) TLQX (5) TLQV () THQZ (3) TLQV (9) TAVQX Q (4) TLQX NOT: 1. is High for a Read Cycle. FIUR 1. RAD CYCL Addresses must remain stable for the duration of the read cycle. To read, and must be VIL and VIH. The output buffers can be controlled independently by while is low. To execute consecutive read cycles, may be tied low continuously until all desired locations are accessed. hen is low, addresses must be driven by stable logic levels and must not be in the high impedance state. ADDRSS (10) TAVAX (11) TLH (14) THAX (12) TAVL (13) TLH (20) TLH (16) TLQZ (19) THQX Q (21) TDVH D (1) TDVH (1) THDX (22) TAVH NOT: 1. is Low throughout rite Cycle. FIUR 2. RIT CYCL I To write, addresses must be stable, low and falling low for a period no shorter than TLH. Data in is referenced with the rising edge of, (TDVH and THDX). hile addresses are changing, must be high. hen falls low, the I/O pins are still in the output state for a period of TLQZ and input data of the opposite phase to the outputs must not be applied, (Bus contention). If transitions low simultaneously with the line transitioning low or after the transition, the output will remain in a high impedance state. is held continuously low. FN3001 Rev.1.00 Page 6 of 9

7 Timing aveforms (Continued) (10) TAVAX ADDRSS (22) TAVH (11) TLH (14) THAX (12) TAVL (13) TLH Q THQZ (15) (21) TDVH D (1) TDVH (1) THDX FIUR 3. RIT CYCL II In this write cycle has control of the output after a period, THQZ. switching the output to a high impedance state allows data in to be applied without bus contention after THQZ. hen transitions high, the data in can change after THDX to complete the write cycle. Low Voltage Data Retention Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaran teed over temperature. The following rules ensure data retention: 1. Chip nable () must be held high during data retention; within -0.3V to +0.3V. 2. On RAMs which have selects or output enables (e.g., S, ), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., ) must be kept between +0.3V and 0% of during the power up and down transitions. 4. The RAM can begin operation > 55ns after reaches the minimum operating voltage (4.5V). DATA RTNTION TIMIN V CC 4.5V V CC 02.0V 4.5V >55ns V CC -0.3V TO V CC +0.3V FIUR 4. DATA RTNTION TIMIN FN3001 Rev.1.00 Page of 9

8 Test Circuit DUT (NOT 1) C L IOH V IOL QUIVALNT CIRCUIT NOT: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuits HM-65162/3 CRDIP TOP VI HM-65162/3 CLCC TOP VI F10 F10 F9 F F F6 F5 F4 F3 A DQ1 DQ2 ND A A9 0 DQ6 DQ5 DQ4 DQ3 C F11 F12 F1 F0 F13 F0 F9 F F F6 F5 F4 F3 5 6 A DQ DQ2 ND DQ3 DQ4 DQ5 29 A 2 A DQ6 F11 F12 F1 F0 F13 F C NOTS: All resistors 4k 5%. F0 = 100kHz 10%. F1 = F0 2, = F1 2, F3 = 2... F13 = F12 2. = 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01 F Min. NOTS: All resistors 4k 5%. F0 = 100kHz 10%. F1 = F0 2, = F1 2, F3 = 2... F13 = F12 2. = 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01 F Min. FN3001 Rev.1.00 Page of 9

9 Die Characteristics DI DIMNSIONS: 10.3 x x 19 1mils MTALLIZATION: Type: Si - Al Thickness: 11kÅ 2kÅ LASSIVATION: Type: SiO 2 Thickness: kå 1kÅ ORST CAS CURRNT DNSITY: 1. x 10 5 A/cm 2 Metallization Mask Layout HM-65162/3 A A A9 0 DQ1 DQ2 ND DQ3 DQ4 DQ5 DQ6 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3001 Rev.1.00 Page 9 of 9