HSPICE Applications Manual. Version X , September 2005

Transcription

1 HSPICE Applications Manual Version, September 2005

2 Copyright Notice and Proprietary Information Copyright 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of and its employees. This is copy number. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks ( ) Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE, Hypermodel, in-phase, in-sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, Inc. Trademarks ( ) Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HANEX, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSIM plus, HSPICE-Link, in-tandem, Integrator, Interactive Waveform Viewer, i-virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDLlint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc. Service Marks ( SM ) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. All other product or company names may be trademarks of their respective owners. Printed in the U.S.A. HSPICE Applications Manual, ii HSPICE Applications Manual

3 Contents Inside This Manual The HSPICE Documentation Set Searching Across the HSPICE Documentation Set Other Related Publications Conventions Customer Support ix x xi xii xii xiii 1. Performing Digital Cell Characterization Performing Basic Cell Measurements Rise, Fall, and Delay Calculations Delay versus Fanout Pin Capacitance Measurement Op-amp Characterization of LM Performing Advanced Cell Characterization Cell Examples Input File Examples Timing Analysis Using Bisection Overview of Bisection Bisection Methodology Measurement Optimization Using Bisection Examining the Command Syntax Performing Transient Analyses with Bisections Setup Time Analysis Input Listing HSPICE Applications Manual iii

4 Contents Results Minimum Pulse Width Analysis Input Listing Results Pushout Bisection Methodology Behavioral Modeling Behavioral Design Process Using Behavioral Elements Controlled Sources Digital Stimulus Files Behavioral Examples Op-Amp Subcircuit Generators Libraries Voltage and Current Controlled Elements Modeling with Digital Behavioral Components Behavioral AND and NAND Gates Behavioral D-Latch Behavioral Double-Edge Triggered Flip-Flop Calibrating Digital Behavioral Components Building Behavioral Lookup Tables Subcircuit Definition Behavioral N-Channel MOSFET Creating a Behavioral Inverter Lookup Table Optimizing Behavioral CMOS Inverters Optimizing Behavioral Ring Oscillators Example Five-Stage Ring Oscillator Analog Behavioral Elements Behavioral Integrator Behavioral Differentiator Ideal Transformer Behavioral Tunnel Diode Behavioral Silicon-Controlled Rectifier (SCR) Behavioral Triode Vacuum Tube Subcircuit Behavioral Amplitude Modulator Behavioral Data Sampler iv HSPICE Applications Manual

5 Contents Op-Amps, Comparators, and Oscillators Op-Amp Model Generator Op-Amp Element Statement Format COMP=0 (internal compensation) COMP=1 (external compensation) Op-Amp.MODEL Statement Format Op-Amp Model Parameters Op-Amp Model Parameter Defaults Op-Amp Subcircuit Example AUTOSTOP Option AC Resistance Simulation Results Unity Gain Resistor Divider Mode Op-Amp from Controlled Sources Inverting Comparator with Hysteresis Voltage-Controlled Oscillator (VCO) LC Oscillator Phase-Locked Loops (PLL) Phase Detector, with Multi-Input NAND Gates PLL BJT Behavioral Modeling VCO Example BJT Level Phase Detector References Pole/Zero Analysis Overview of Pole/Zero Analysis Using Pole/Zero Analysis Matrix Approach Muller Method Pole/Zero Analysis Examples Example 1 Low-Pass Filter Example 2 Kerwin s Circuit Example 3 High-Pass Butterworth Filter Example 4 CMOS Differential Amplifier Example 5 Simple Amplifier Example 6 Active Low-Pass Filter References HSPICE Applications Manual v

6 Contents 5. FFT Spectrum Analysis Using Windows in FFT Analysis Using the.fft Statement Examining the FFT Output AM Modulation Input and Output Listing Graphical Output Balanced Modulator and Demodulator Input and Output Listing Signal Detection Test Circuit Input Listing Output References Modeling Filters and Networks Transient Modeling Using G and E Elements Laplace Transform Function Call Element Statement Parameters G and E Element Notes Laplace Band-Reject Filter Laplace Low-Pass Filter Circular Convolution Example Notes Degree Phase Shift Circuit File Laplace and Pole-Zero Modeling Laplace Transform (LAPLACE) Function General Form of the Transfer Function Finding the Transfer Function Determining the Laplace Coefficients Laplace Transform POLE (Pole/Zero) Function POLE Function Call General Form of the Transfer Function Reduced Form of the Transfer Function RC Line Modeling AWE Transfer Function Modeling vi HSPICE Applications Manual

7 Contents Y Parameter Line Modeling Comparison of Circuit and Pole/Zero Models Circuit Model Input Listing Pole/Zero Model Input Listing Simulation Time Summary Modeling Switched Capacitor Filters Switched Capacitor Network Switched Capacitor Network Example Switched Capacitor Filter Example Input File for Switched Capacitor Filter References Library Encryption Library Encryption Controlling the Encryption Process Library Structure Encryption Guidelines Installing and Running the Encryptor Installing the Encryptor Running the Encryptor Metaencrypt Features Byte Key Encryption Encryption Structure sp File Encryption lib File Encryption inc File Encryption load Encryption Encrypting 80+ Columns Statements Not Supported Additional Recommendations for Encryption Encryption Structure Example Converter Utility Converter Features PSF Converter PWL/DATA/VEC Converter HSPICE Applications Manual vii

8 Contents Input Line Dependencies Triple DES Encryption Public and random keys metaencrypt command Syntax Index viii HSPICE Applications Manual

9 About This Manual This contains application examples that show you ways you can use HSPICE. Inside This Manual This manual contains the chapters described below. For descriptions of the other manuals in the HSPICE documentation set, see the next section, The HSPICE Documentation Set. Chapter Chapter 1, Performing Digital Cell Characterization Chapter 2, Timing Analysis Using Bisection Chapter 3, Behavioral Modeling Chapter 4, Pole/Zero Analysis Chapter 5, FFT Spectrum Analysis Chapter 6, Modeling Filters and Networks Description Describes how to characterize cells in data-driven analysis. Also shows you some typical data sheet parameters. Describes how to use the bisection function in timing optimization. Describes how to create behavioral models. Describes how to use pole/zero analysis in HSPICE or HSPICE RF. Describes how to use FFT spectrum analysis to provide the highest FFT accuracy with minimal overhead in simulation time. Describes modeling filters and networks, including Laplace transforms. HSPICE Applications Manual ix

10 About This Manual The HSPICE Documentation Set Chapter Chapter 7, Library Encryption Chapter 8, Converter Utility Chapter 9, Triple DES Encryption Description Describes the Synopsys Library Encryptor and how to use it to protect your intellectual property. Describes how to convert output generated by HSPICE. Introduces and describes the metaencrypt Triple DES Encryption command syntax. The HSPICE Documentation Set This manual is a part of the HSPICE documentation set, which includes the following manuals: Manual HSPICE Simulation and Analysis User Guide HSPICE Signal Integrity Guide HSPICE Applications Manual HSPICE Command Reference HPSPICE Elements and Device Models Manual HPSPICE MOSFET Models Manual Description Describes how to use HSPICE to simulate and analyze your circuit designs. This is the main HSPICE user guide. Describes how to use HSPICE to maintain signal integrity in your chip design. Provides application examples and additional HSPICE user information. Provides reference information for HSPICE commands. Describes standard models you can use when simulating your circuit designs in HSPICE, including passive devices, diodes, JFET and MESFET devices, and BJT devices. Describes standard MOSFET models you can use when simulating your circuit designs in HSPICE. x HSPICE Applications Manual

11 About This Manual Searching Across the HSPICE Documentation Set Manual HSPICE RF Manual AvanWaves User Guide HSPICE Quick Reference Guide HSPICE Device Models Quick Reference Guide Description Describes a special set of analysis and design capabilities added to HSPICE to support RF and high-speed circuit design. Describes the AvanWaves tool, which you can use to display waveforms generated during HSPICE circuit design simulation. Provides key reference information for using HSPICE, including syntax and descriptions for commands, options, parameters, elements, and more. Provides key reference information for using HSPICE device models, including passive devices, diodes, JFET and MESFET devices, and BJT devices. Searching Across the HSPICE Documentation Set Synopsys includes an index with your HSPICE documentation that lets you search the entire HSPICE documentation set for a particular topic or keyword. In a single operation, you can instantly generate a list of hits that are hyperlinked to the occurrences of your search term. For information on how to perform searches across multiple PDF documents, see the HSPICE release notes (available on SolvNet at or the Adobe Reader online help. Note: To use this feature, the HSPICE documentation files, the Index directory, and the index.pdx file must reside in the same directory. (This is the default installation for Synopsys documentation.) Also, Adobe Acrobat must be invoked as a standalone application rather than as a plug-in to your web browser. HSPICE Applications Manual xi

12 About This Manual Other Related Publications Other Related Publications For additional information about HSPICE, see: The HSPICE release notes, available on SolvNet (see Accessing SolvNet on page xiii) Documentation on the Web, which provides HTML and PDF documents and is available through SolvNet at The Synopsys MediaDocs Shop, from which you can order printed copies of Synopsys documents, at You might also want to refer to the documentation for the following related Synopsys products: CosmosScope Aurora Raphael VCS Conventions The following conventions are used in Synopsys documentation: Convention Courier Italic Bold Description Indicates command syntax. Indicates a user-defined value, such as object_name. Indicates user input text you type verbatim in syntax and examples. [ ] Denotes optional parameters, such as write_file [-f filename]... Indicates that a parameter can be repeated as many times as necessary: pin1 [pin2... pinn] xii HSPICE Applications Manual

13 About This Manual Customer Support Convention Description Indicates a choice among alternatives, such as low medium high \ Indicates a continuation of a command line. / Indicates levels of directory structure. Edit > Copy Control-c Indicates a path to a menu command, such as opening the Edit menu and choosing Copy. Indicates a keyboard combination, such as holding down the Control key and pressing c. Customer Support Customer support is available through SolvNet online customer support and through contacting the Synopsys Technical Support Center. Accessing SolvNet SolvNet includes an electronic knowledge base of technical articles and answers to frequently asked questions about Synopsys tools. SolvNet also gives you access to a wide range of Synopsys online services, which include downloading software, viewing Documentation on the Web, and entering a call to the Support Center. To access SolvNet: 1. Go to the SolvNet Web page at 2. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.) If you need help using SolvNet, click SolvNet Help in the Support Resources section. HSPICE Applications Manual xiii

14 About This Manual Customer Support Contacting the Synopsys Technical Support Center If you have problems, questions, or suggestions, you can contact the Synopsys Technical Support Center in the following ways: Open a call to your local support center from the Web by going to (Synopsys user name and password required), then clicking Enter a Call to the Support Center. Send an message to your local support center. support_center@synopsys.com from within North America. Find other local support center addresses at Telephone your local support center. Call (800) from within the continental United States. Call (650) from Canada. Find other local support center telephone numbers at xiv HSPICE Applications Manual

15 1 1Performing Digital Cell Characterization Describes how to characterize cells in data-driven analysis. Also shows you some typical data sheet parameters. Most ASIC vendors use the basic capabilities of the.measure statement in Synopsys HSPICE or HSPICE RF to characterize standard cell libraries, and to prepare data sheets. HSPICE or HSPICE RF stores input sweep parameters and measure output parameter, in measure output data files (design.mt0, design.sw0, and design.ac0). These files store multiple sweep data. You can use AvanWaves to plot this data; for example, to generate fanout plots of delay versus load. You can also use the slope and intercept of the loading curves to calibrate VHDL, Verilog, Lsim, TimeMill, and Synopsys models. This chapter shows you some typical data sheet parameters. By looking at a series of typical data sheet examples, you can see the flexibility of the.measure statement. This chapter also shows you how to characterize cells in data-driven analysis. Data-driven analysis automates cell characterization, including calculating the delay coefficient for the timing-simulator polynomial. You can simultaneously vary an unlimited number of parameters, or the number of analyses to perform. Cell characterization uses a convenient ASCII file format, for automated parameter input to HSPICE or HSPICE RF. HSPICE Applications Manual 1

16 1: Performing Digital Cell Characterization Performing Basic Cell Measurements Performing Basic Cell Measurements This section describes how to perform basic cell measurements. Rise, Fall, and Delay Calculations The following example does the following: 1. Uses the MAX function to calculate vmax, over the time region of interest. 2. Uses the MIN function to calculate vmin. 3. Uses the measured parameters in subsequent calculations, for accurate 10% and 90% points, when determining the rise and fall time. 4. RISE=1 is relative to the time window that the TDval delay forms. 5. Uses a fixed value for the measure threshold, to calculate the Tdelay delay. The following is an example:.meas TRAN vmax MAX V(out) FROM=TDval TO=Tstop.MEAS TRAN vmin MIN V(out) FROM=TDval TO=Tstop.MEAS TRAN Trise TRIG V(out) val= vmin+0.1*vmax + TD=TDval RISE=1 TARG V(out) val= 0.9*vmax RISE=1.MEAS TRAN Tfall TRIG V(out) val= 0.9*vmax TD=TDval + FALL=2 TARG V(out) val= vmin+0.1*vmax FALL=2.MEAS TRAN Tdelay TRIG V(in) val=2.5 TD=TDval FALL=1 + TARG V(out) val=2.5 FALL=2 Figure 1 Rise, Fall, and Delay Time Demonstration volts Trise Tfall 5 v V(in) V(out) Tdelay TDval time Tstop 2 HSPICE Applications Manual

17 1: Performing Digital Cell Characterization Performing Basic Cell Measurements Ripple calculation performs the following: Delimits the wave at the 50% of VCC points Finds the Tmid midpoint Defines a bounded region by finding the pedestal voltage (Vmid) and then finding the first time that the signal crossed this value, Tfrom Measures the ripple in the defined region using the peak-to-peak (PP) measure function from Tfrom to Tmid The following is an example:.meas TRAN Th1 WHEN V(out)= 0.5*vcc CROSS=1.MEAS TRAN Th2 WHEN V(out)= 0.5*vcc CROSS=2.MEAS TRAN Tmid PARAM= (Th1+Th2)/2.MEAS TRAN Vmid FIND V(out) AT= Tmid.MEAS TRAN Tfrom WHEN V(out)= Vmid RISE=1.MEAS TRAN Ripple PP V(out) FROM= Tfrom TO= Tmid Figure 2 Waveform to Demonstrate Ripple Calculation V(out) ripple defined region 5 v vcc Vmid 2.5 v 0 v Th1Tfrom Tmid Th2 time This file sweeps the sigma of the model parameter distribution, while it examines the delay. It shows you the delay derating curve, for the worst cases in the model. This example is based on the demonstration file that is located in the following directory: $installdir/demo/hspice/cchar/sigma.sp. For a description of this technique for building a worst-case sigma library, see the HSPICE Simulation and Analysis User Guide. HSPICE Applications Manual 3

18 1: Performing Digital Cell Characterization Performing Basic Cell Measurements Figure 3 Inverter Pair Transfer Curves and Sigma Sweep vs. Delay INV.TRO Volt [Lin] H H 100.0P 200.0P 300.0P 400.0P 500.0P Time [Lin] 360.0P 340.0P INV.MTO H_DELAY 320.0P 300.0P Param [Lin] 280.0P 260.0P 240.0P 220.0P 200.0P 180.0P 160.0P Sigma [Lin] Delay versus Fanout This example sweeps the sub-circuit multiplier, to quickly generate five load curves. To obtain more accurate results, buffer the input source with one stage. 4 HSPICE Applications Manual

19 1: Performing Digital Cell Characterization Performing Basic Cell Measurements For each second-sweep variable (m_delay and rms_power), the following example calculates: mean variance sigma average deviance This example is based on the demonstration file located in the following directory: <$installdir>/demo/hspice/cchar/load1.sp. This example outputs the following results: meas_variable = m_delay mean = p varian = 1.968e-20 sigma = p avgdev = p meas_variable = rms_power mean = m varian = u sigma = m avgdev = m Figure 4 Inverter Delay and Power, versus Fanout Volt [Lin] Param [Lin] P 300.0P 200.0P 100.0P 8.0N 6.0N 4.0N P 200.0P 400.0P 600.0P 800.0P 1.00P 1.135P Time [Lin] LOAD1.TRO IN 2 3 LOAD1.NTO N_DELAY LOAD1.NTO AMS-POVER 2.0N Fanout [Lin] Pin Capacitance Measurement This example does the following: 1. Shows the effect of dynamic capacitance, at the switch point. 2. Sweeps the DC input voltage (pdcin) to the inverter. HSPICE Applications Manual 5

20 1: Performing Digital Cell Characterization Performing Basic Cell Measurements 3. Performs an AC analysis, at each 0.1 volt increment. 4. Calculates the incap measure parameter, from the imaginary current through the voltage source, at 10 kilohertz in the AC curve (not shown). The peak capacitance (at the switch point) occurs when the voltage at the output side changes, in the direction opposite the input side of the Miller capacitor. This adds the Miller capacitance, times the inverter gain, to the effective capacitance. Example mp out in 1 1 mp w=10u l=3u mn out in 0 0 mn w=5u l=3u vin in 0 DC= pdcin AC 1 0.ac lin 2 10k 100k sweep pdcin measure ac incap find par( -1 * ii(vin)/ + (hertz*twopi) ) AT=10000hertz Figure 5 Graph of Pin Capacitance versus Inverter Input Voltage 150.0F 140.0F INVCAP.NAO INCAP Param [Lin] 130.0F 120.0F 110.0F 100.0F 90.0F 80.0F 70.0F 60.0F 50.0F IN F PDCIN [Lin] 6 HSPICE Applications Manual

21 1: Performing Digital Cell Characterization Performing Basic Cell Measurements Op-amp Characterization of LM124 This example analyzes op-amps. This example uses: 1..MEASURE statements, to present a very complete data sheet. 2. Four.MEASURE statements, to reference the out0 output node of an opamp circuit. These statements use output variable operators for: decibels vdb(out0) voltage magnitude vm(out0) phase vp(out0) The example is based on the demonstration file that is located in the following directory: $installdir/demo/apps/alm124.sp. This example outputs the following results: unitfreq = E+05 targ= E+05 trig= E+00 phasemargin = E+01 gain(db) = E+01 at= E+00 from= E+00 + to= E+07 gain(mag)= E+04 at= E+00 from= E+00 + to= E+07 Figure 6 Magnitude Plot of Op-Amp Gain Volt DB [Lin] ALMI24.ACO VDB[OUT] K 10.0K 100.0K 1.0X 10.0X HERTZ [LOB] HSPICE Applications Manual 7

22 1: Performing Digital Cell Characterization Performing Advanced Cell Characterization Performing Advanced Cell Characterization This section provides example input files, which characterize cells for an inverter, based on 3-micron MOSFET technology. The program finds the propagation delay, and the rise and fall times, for the inverter, using best, worst, and typical cases for different fanouts. You can use this library data for digitalbased simulators, such as those used to simulate gate arrays and standard cells. The example is based on the demonstration file in $installdir/demo/ hspice/apps/cellchar.sp. It demonstrates how to use the following, to characterize a CMOS inverter:.measure statement.data statement AUTOSTOP option Cell Examples Figure 7 and Figure 8 are identical, except that their input signals are complementary. The circuit in Figure 7 calculates the rise time and the low-to-high propagation delay time. The circuit in Figure 8 calculates the fall time and the high-to-low propagation delay time. If you use only one circuit, CPU time increases, because analysis time increases when HSPICE or HSPICE RF calculates both rise and fall times. The XOUTL or XOUTH sub-circuit represents the fanout of the cell (inverter). To modify fanout, specify different multipliers (m) in the sub-circuit calls. You can also specify local and global temperatures. This example characterizes the cell at a global temperature of 27, but the temperature of the M1 and M2 devices is (27+DTEMP). The.DATA statement specifies the DTEMP value. The example uses a transient parameterized sweep, with.data and.measure statements, to determine the inverter timing, for best, typical, and worst cases. 8 HSPICE Applications Manual

23 1: Performing Digital Cell Characterization Performing Advanced Cell Characterization Figure 7 Cell Characterization Circuit 1 VINH XOUTL XINVH 2 3 Figure 8 Cell Characterization Circuit 2 VINL XOUTH XINVL This example varies the following parameters: power supply input rise and fall time fanout MOSFET temperature n-channel and p-channel threshold drawn width and length of the MOSFET HSPICE Applications Manual 9

24 1: Performing Digital Cell Characterization Performing Advanced Cell Characterization 1. Use the.measure statement to specify a parameter to measure. 2. Use the AUTOSTOP option, to speed simulation time. 3. The AUTOSTOP option terminates the transient sweep, although it has not completely swept the specified transient sweep range. The.MEASURE statement uses quoted string parameter variables, to measure the rise time, fall time, and propagation delays. Note:Do not use character strings as parameter values in HSPICE RF. Rise time starts when the voltage at node 3 (the output of the inverter) is equal to 0.1 VDD (that is, V(3) = 0.1VDD). Rise time ends when the voltage at node 3 is equal to 0.9 VDD (that is, V(3) = 0.9VDD). For more accurate results, start the.measure calculation after either: A time delay, or A simulation cycle, specifying delay time in the.measure statement, or An input pulse statement. The following example features: AUTOSTOP and.measure statements. Mean, variance, sigma, and avgdev calculations. Circuit and element temperature. Algebraic equation handling. PAR( ) as an output variable, in the.measure statement. Sub-circuit parameter passing, and sub-circuit multiplier..data statement. Input File Examples This input file example is located in the following directory: $installdir/demo/hspice/apps/cellchar.sp 10 HSPICE Applications Manual

25 1: Performing Digital Cell Characterization Performing Advanced Cell Characterization The cellchar.sp file includes the following samples: SUBCKT definition SUBCKT call models Figure 9 Plotting the Simulation Outputs CELLCHAR.TRO V (2 V ( Volt [Lin] M N 20.0N 30.0N N Time [Lin] HSPICE Applications Manual 11

26 1: Performing Digital Cell Characterization Performing Advanced Cell Characterization Figure 10 Verifying the Measure Statement Results by the Plots CELLCHAR.TRO V (2 V ( Volt [Lin] M N 20.0N 30.0N N Time [Lin] 12 HSPICE Applications Manual

27 2 2Timing Analysis Using Bisection Describes how to use the bisection function in timing optimization. To analyze circuit timing violations, a typical methodology is to generate a set of operational parameters that produce a failure in the required behavior of the circuit. When a circuit timing failure occurs, you can identify a timing constraint, which can lead to a design guideline. You must perform an iterative analysis, to define the violation specification. Typical types of timing constraint violations include: Data setup time, before the clock. Data hold time, after the clock. Minimum pulse width required, for a signal to propagate to the output. Maximum toggle frequency of the component(s). For more information about optimization, see the HSPICE Simulation and Analysis User Guide. Overview of Bisection Before bisection methods were developed, engineers built external drivers to submit multiple parameterized simulations to SPICE-type simulators. Each HSPICE Applications Manual 13

28 2: Timing Analysis Using Bisection Overview of Bisection simulation explored a region of the operating envelope for the circuit. To provide part of the analysis, the driver also post-processed the simulation results, to deduce the limiting conditions. If you characterize small circuits this way, analysis times are relatively small, compared with the overall job time. This method is inefficient, due to overhead of submitting the job, reading and checking the netlist, and setting up the matrix. The newer bisection methods increase efficiency when you analyze timing violations, to find the causes of timing failure. Bisection optimization is an efficient cell-characterization method, in Synopsys HSPICE or HSPICE RF. The bisection methodology saves time in three ways: Reduces multiple jobs to a single characterization job. Removes post-processing requirements. Uses accuracy-driven iterations. Figure 11 on page 15 shows a typical analysis of setup-time constraints. Clock and data input waveforms drive a cell. Two input transitions (rise and fall) occur at times T 1 and T 2. The result is an output transition, when V(out) changes from low to high. The following relationship between the T 1 (data) and T 2 (clock) times must be true, for the V(out) transition to occur: T 2 > (T 1 + setup time) Characterization, or violation analysis, determines the setup time. To do this, HSPICE or HSPICE RF keeps T 2 fixed, repeats the simulation with different T 1 values. It then observes which T 1 values produce an output transition, and which do not. Before bisection, you had to run tight sweeps of the delay, between the data setup and clock edge, looking for the value at which no transition occurs. To do this, you swept a value that specifies how far the data edge precedes a fixed clock edge. This method is time consuming, and is accurate only if the sweep step is very small. Linear search methods cannot accurately determine the setup time value, unless you use extremely small steps from T 1 to T 2 to simulate the circuit at each point, and monitor the outcome. For example, even if you know that the desired transition occurs during a particular five-nanosecond period, you might need to run 50 simulations to search for the setup time, to within 0.1 nanoseconds, over that five nanosecond period. Even after this, the error in the result can be as large as 0.05 nanoseconds. 14 HSPICE Applications Manual

29 2: Timing Analysis Using Bisection Bisection Methodology Figure 11 Determining Setup Time with Bisection Violation Analysis T 1(varies) T 2(fixed) 1 Setup Time = T2 - T1 Clock 0 Early enough to cause a good V(out) transition 1 Data Target value: latest time at which a Data transition results in a V(out) transition Too late for a good transition: V(out) does not change 0 1 V(out) 0 Time T 1 T 2 Setup time is the minimum amount of time by which the Data transition must precede the Clock transition at T2, in order to cause a V(out) transition Bisection can be used to quickly find the latest time T1 at which a Data transition causes a V(out) transition. The bisection feature greatly reduces the amount of work and computational time required, to find an accurate solution for this type of problem. The following pages show examples of using this feature, to identify timing violations for the setup, hold, and minimum clock pulse width. Bisection Methodology Bisection is an optimization method that uses a binary search method, to find the value of an input variable (target value). This variable is associated with a goal value of an output variable. HSPICE Applications Manual 15

30 2: Timing Analysis Using Bisection Bisection Methodology The type of the input and output variables can be voltage, current, delay time, or gain, related by some transfer function. In general, use a binary search to locate the goal value of the output variable, within a search range of the input variable. Then iteratively halve that range, to rapidly converge on the target value. At each iteration, HSPICE or HSPICE RF compares the measured value of the output variable, with the goal value. Both the pass/fail method and the bisection method use bisection (see Using Bisection on page 17). The bisection procedure involves two measurement and optimization steps, when solving the timing violation problem: 1. Detects whether the output transition occurred. 2. Automatically varies the input parameter (T 1 in Figure 11), to find the value for which the transition barely occurs. Measurement Use the MAX measurement function, to detect the success or failure of an output transition. For a low-to-high output transition, a MAX measurement produces zero on failure, or approximately the V dd supply voltage on success. This measurement, using a goal of V dd (minus a suitable small value to ensure a solution), is sufficient to drive the optimization. Optimization The bisection method is straightforward, if you specify a single measurement, with a goal, and known upper and lower boundary values, for the input parameter. The characterization engineer must specify acceptable upper and lower boundary values. 16 HSPICE Applications Manual

31 2: Timing Analysis Using Bisection Using Bisection Using Bisection Before you can use bisection, you must specify the following: A pair of values, for the upper and lower boundaries of the input variables. To find a solution, one of these values must result in an output variable S goal value and the other must result in < goal value. A goal value. Error tolerance value. The bisection process stops, when the difference between successive test values error tolerance. If the other criteria are also met, see below. Related variables. Use a monotonic transfer function to relate variables, where a steadily-progressing time (increase or decrease) results in a single occurrence of the goal value at the target input variable value. HSPICE or HSPICE RF includes the error tolerance in a relation, used as a process-termination criterion. Figure 12 on page 21 shows an example of the binary search process, which the bisection algorithm uses. This example is the pass/fail type, and is appropriate for a setup-time analysis that tests for the presence of an output transition (see Figure 11 on page 15). In this example: 1. A long setup time TS (= T2 - T1) results in a VOUT transition (a pass). 2. A too-short setup time (where the latch has not stabilized the input data, before the clock transition) results in a fail. 3. For example, you might define a pass time value as any setup time, TS, that produces a VOUT output minimum high logic output level of 2.7 V, which is the goal value. 4. The target value is a setup time that just produces the VOUT value of 2.7 V. Finding the exact value is impractical, if not impossible, so specify an error tolerance, to calculate a solution arbitrarily close to the target value. 5. The bisection algorithm performs tests for each specified boundary value, to determine the direction in which to pursue the target value, after the first bisection. In this example, the upper boundary has a pass value, and the lower boundary has a fail value. HSPICE Applications Manual 17

32 2: Timing Analysis Using Bisection Using Bisection 6. To start the binary search, specify the lower and upper boundaries. The program tests the point midway between the lower and upper boundaries (see Figure 12 on page 21). If the initial value passes the test, the target value must be less than the tested value (in this example). The bisection algorithm moves the upper search limit to the value that it just tested. If the test fails, the target value must be greater than the tested value. Bisection moves the lower limit to the value that it just tested. 7. The algorithm tests a value midway between the new limits. 8. The search continues in this manner, moving one limit or the other to the last midpoint, and testing the value midway between the new limits. 9. The process stops when the difference between the latest test values is less than or equal to the error tolerance that you specified. To normalize this value, multiply by the initial boundary range. For more information about using the.model statement for bisection, see the HSPICE Command Reference. Examining the Command Syntax The following syntax is used for bisection:.model <OptModelName> OPT METHOD=BISECTION... or.model <OptModelName> OPT METHOD=PASSFAIL... OptModelName is the model to be used. Refer to the HSPICE Simulation and Analysis User Guide for name information on specifying optimization models in HSPICE. The METHOD keyword indicates which optimization method to use. The OPT keyword indicates that optimization is to be performed For bisection, the method can be one of the following: BISECTION When the difference between the two latest test input values is within the error tolerance and the latest measured value exceeds the goal, bisection has succeeded and then ends. This process reports the optimized parameter that corresponded to the test value that satisfies this error tolerance and this goal (passes). 18 HSPICE Applications Manual

33 2: Timing Analysis Using Bisection Using Bisection PASSFAIL When the difference between the two latest test input values is within the error tolerance and one of the values >= goal (passes) and the other fails, bisection has succeeded and then ends. The process reports the input parameter value associated with the "pass" measurement. The parameters are passed in a normal optimization specification:.param <ParamName>=<OptParFun> (<Initial>, <Lower>, <Upper>) In the BISECTION method, the measure results for <Lower> and <Upper> limits of <ParamName> must be on opposite sides of the goal value in the.measure statement. In the PASSFAIL method, the measure must pass for one limit and fail for the other limit. The process ignores the value of the <Initial> field. The error tolerance is a parameter in the model being optimized. In both methods, bisectional search is applied to only one parameter. When the OPTLST option is set (.OPTION OPTLST=1), the process outputs the following information for the BISECTION method: bisec-opt iter = <num_iterations> xlo = <low_val> xhi = <high_val> x = <result_low_val> xnew = <result_high_val> err = <error_tolerance> The x is the old parameter value and xnew is the new parameter value. When.OPTION OPTLST=1, the process outputs the following information for the PASSFAIL method: bisec-opt iter = <num_iterations> xlo = <low_val> xhi = <high_val> x = <result_low_val> xnew = <result_high_val> measfail = 1 In this syntax, measfail = 0 for a test failure for the x value. Performing Transient Analyses with Bisections When performing transient analysis bisection with the.tran statement, use the following syntax:.tran <TranStep> <TranTime> SWEEP OPTIMIZE=<OptParFun> + RESULTS=<MeasureNames> MODEL=<OptModelName> When performing a transient analysis bisection with the.measure statement, use the following syntax:.measure TRAN <MeasureName> <MeasureClause> GOAL=<GoalValue> HSPICE Applications Manual 19

34 2: Timing Analysis Using Bisection Setup Time Analysis Setup Time Analysis This example uses a bisectional search, to find the minimum setup time for a D flip-flop. The circuit for this example is /bisect/dff_top.sp in the HSPICE <$installdir>/demo/hspice (or hspicext for HSPICE RF) demonstration file directory. The files in Figure 12 and Figure 13 show the results of this demo. HSPICE or HSPICE RF does not directly optimize the setup time, but extracts it from its relationship with the DelayTime parameter (the time before the data signal), which is the parameter to optimize. Input Listing The complete input listing file is located in the following directory: $installdir/demo/hspice/bisect/dff_top.sp The following portion of the input listing shows how.tran analysis, the DelayTime parameter, and.measure statements are used in bisection: * DFF_top Bisection Search for Setup Time * PWL Stimulus v28 data gnd PWL + 0s 5v + 1n 5v + 2n 0v + Td = DelayTime $ Offsets Data from time 0 + by DelayTime v27 clock gnd PWL + 0s 0v + 3n 0v + 4n 5v * Specify DelayTime as the search parameter and provide * the lower and upper limits..param DelayTime= Opt1 ( 0.0n, 0.0n, 5.0n ) * Transient simulation with Bisection Optimization.TRAN 1n 8n SweepOptimize = Opt1 + Result = MaxVout$ Look at measure + Model = OptMod * This measure finds the transition if it exists.measure Tran MaxVout Max v(d_output) Goal = v(vdd) * This measure calculates the setup time value.measure Tran SetupTimeTrig v(data)val = v(vdd)/2 + Fall = 1 + Targ v(clock)val = v(vdd)/2 + Rise = 1 * Optimization Model 20 HSPICE Applications Manual

35 2: Timing Analysis Using Bisection Setup Time Analysis.MODEL OptMod Opt + Method = Bisection.OPTION Post Brief NoMod Figure 12 Bisection Example for Three Iterations First bisection value is mid-way between specified boundaries. First test value passes because measured value > goal value (2.7 V in this case). Measured value Y - volts in this case ~5V Goal = 2.7V X 1 = (X U + X L )/2 Output signal present for all T S target value Lower boundary X L - test fails Target value First test value - passes Upper boundary X U - test passes Input variable X - Setup time T s in this case First test value becomes new upper test limit. Second test value is mid-way between new upper limit and lower boundary. Second test value fails. v X 2 = (X 1 + X L )/2 X L Target X 1 X U X Second test value - fails Second test value becomes new lower limit. Third test value is mid-way between new lower limit and current upper limit. v X 2 = (X 1 + X 2 )/2 X L X 2 X 1 X U X Third test value - passes Continue halving the test region until the interval between successive test values meets the criterion: then report the value X, (associated with the measured value the passed). If you select the bisection method, the reported value must correspond with the condition: measured value - goal > 0 HSPICE Applications Manual 21