An Energy-Aware CMOS Receiver Front end for Low-Power 2.4-GHz Applications

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1 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < An Energy-Aware CMOS Receiver Front end or Low-Power.4-Hz Applications Aaron. Do, Member, IEEE, Chirn Chye Boon, Member, IEEE, Manh Anh Do, Senior Member, IEEE, Kiat Seng Yeo, Member, IEEE, Alper Cabuk, Member, IEEE Abstract A receiver ront end designed in.8-µm CMOS consisting o an L A and IQ mixers is presented. The ront end s power consumption is controllable rom 5. ma down to.4 ma. It is proposed to push the receiver requirements to the ront-end in order to eiciently control the overall power consumption based on the real-time required noise perormance. We show that under good channel conditions, this ront end can save up to 7% o its nominal power consumption. Index Terms RF Front End, CMOS RF Integrated Circuits, Low Power, System on Chip. T I. INTRODUCTION HE last decade has seen the near complete integration o the wireless transceiver, and the rise o CMOS as the choice technology in consumer-based wireless applications such as mobile phones and wireless local area network (WLAN). Full system integration continues to be a topic o interest in the research ield in order to minimize both the cost and the orm-actor o wireless transceivers. However, a new trend is emerging in RFIC System on Chip (SoC) design. In the interests o longer battery lie, ultra-low power design has recently become a hot topic or applications such as wireless personal area networks (WPAN), and wireless sensor nodes. The IEEE standard has been speciically designed to cater to this demand. Transceivers which ollow this standard have been designed to operate using less than ma o current []. These designs have relied on simpliied circuit conigurations to minimize power consumption []-[5].Despite their relative successes, we believe that signiicantly more power consumption can be saved both by urther simpliying the circuit structures, and dynamically adjusting the perormance o the receiver (RX). The latter method is termed energy-aware design and our proposed energy-aware scheme was introduced in [6]. While a radio is designed around its sensitivity, it normally operates under signiicantly better conditions. The average path loss varies depending on the environment, availability o line o sight (LOS) and distance between the RX and transmitter (TX), Manuscript received December 9 th, 9. The authors are with Nanyang Technological University, Singapore ( doaaron@ntu.edu.sg; eccboon@ntu.edu.sg; emado@ntu.edu.sg; eksyeo@ntu.edu.sg; ACabuk@ntu.edu.sg). among other things [7]. An energy-aware transceiver adjusts its perormance according to the amount o received signal strength and uses the optimum power to receive the signal in a given situation. This work presents the implementation o an energy-aware RX ront end or low power, low data-rate applications. We propose to dynamically control the power consumption o an RX ront end based on the real-time required noise igure (NF). As a basis or comparison, we will design around the IEEE standard which operates in the.4-hz Industrial, Scientiic and Medical (ISM) band. We ocus on the design o the RX ront end which generally consumes a large portion o the total RX power. The standard eatures relaxed requirements in terms o intererence rejection, and noise perormance which simpliies ront end design and will allow us to implement dynamic power control circuitry. Section II o this work will discuss energy-saving schemes and compare the proposed energy-aware scheme to state-o-the-art methods. Section III will discuss the distribution o power consumption in an RX and how much power can practically be saved. Section I will present the receiver design methodology and details o the individual circuit blocks. Section will present measured results and Section I will conclude our work. II. ENERY-SAIN SCHEMES A. Proposed Energy Aware Design The proposed energy-aware scheme involves adjusting the RX ront end s power consumption based on its in-situ required NF. While the inal design merit or an RX is its bit-error rate (BER), RFIC designers generally split the perormance requirements up into nearly independent speciications. In general, signal non-idealities arise due to linear distortion [8], intererence, and random noise. An example o linear distortion is non-ideal iltering. In general, RF components such as the low-noise ampliier (LNA), and down-conversion mixer produce scarce linear distortion as they are generally designed to pass a much greater bandwidth than the signal bandwidth. For example, an ront end must pass the entire 83.5 MHz system bandwidth where the signal bandwidth is only MHz []. The eect o intererence on a signal s quality is described by the RX n th order intercept (IIP n ), phase noise, image rejection

2 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < F total F F = + (3) Fig.. Tolerable NF versus Received Input power or the IEEE standard. ratio (IRR), and -db gain compression (P -db ). Such perormance parameters are not suitable or energy-aware control or several reasons. Starting with linearity, we note that IIP n and P -db are linked, and in principle the P -db is approximately 9.6 db lower than the IIP 3 [9]. As the received signal strength increases, the required gain o the system drops. Reducing the system gain generally improves both its IIP n and P -db. However, the required IIP n reduces making it impractical to control. Phase noise is a parameter o the requency synthesizer whose power consumption is impractical to control without aecting the loop dynamics o the requency synthesizer. Lastly, image rejection ratio (IRR), is determined by the matching between the I and Q paths and is not directly related to RX power consumption. NF on the other hand is directly related to the RX power consumption. The input-reerred noise o a MOSFET is approximately (only channel noise is considered), ktγ n in 4, () αg m where k is Boltzmann s constant, T is temperature in Kelvin, γ is a parameter approximately equal to /3 in saturation or long-channel devices, α is the ratio o g m to the transconductance when the drain source voltage is zero, and g m is the device transconductance []. Since g m improves with current consumption, W g m = µ Cox I DS () L where µ C ox is process dependent, W/L is the aspect ratio, and I DS is the drain-source current, current consumption can be directly linked to NF. NF is also indirectly related to current consumption through the gain o a cascaded system. The cascaded NF can be calculated as, where F total is the noise actor o the system, F is the noise actor o the irst stage, F is the combined noise actor o all subsequent stages, and is the power gain (which is proportional to the square o the voltage gain) o the irst stage. When F is small compared to F total, F total is inversely proportional to the irst stage s squared-gain. Assuming we have a common-source LNA representing, its voltage gain is proportional to the square-root o the current consumption, and thereore, F total is inversely proportional to the current consumption. The tolerable system NF o an IEEE RX is shown versus received signal strength in Fig. and is based on system simulations in [] which include the eects o a multipath environment. The bit-error-rate o the system is directly related to the received SNR and hence the system NF. In practice, we can also expect the curve to deviate slightly due to the inite output SNR o the transmitter. Our discussion suggests that while an ideal energy-aware RX would be able to independently control its noise and intererence perormance, a sub-optimal design should be able to control its noise perormance without degrading its intererence perormance. B. An Alternate Energy-Aware Design An energy-aware method involving control o a transceiver s power consumption based on the required error-vector magnitude (EM) was proposed in []. The principle behind the choice o EM as a perormance measure is its strong correlation to BER. The authors proposed to control the EM by controlling the biasing and power supply o the RF ront end. However, in [], no attempt to treat noise and intererence independently was made. This method would thereore be suboptimal in situations where noise perormance is good but intererence perormance is poor (or vice versa) since the EM would relect the poorer o the two perormances. As discussed in the previous section, we advocate a two-dimensional approach to energy aware design. However, in this work we concentrate solely on adjusting the RX noise perormance. C. ariable Data Rate Standards Certain standards such as the mobile WiMax [3] standard support multiple data rates. When channel conditions are good, the receiver can switch to a higher-data-rate modulation scheme and thereore, or the same amount o data, the transceiver is on or a shorter duration. Unortunately, the channel conditions must be good both in terms o noise and intererence simultaneously in order or the transceiver to communicate at higher data rates. The proposed energy-aware method does not suer such limitations. D. Other Energy-Saving Schemes Two other interesting methods or saving power in RX design are the wake-up RX (WuRX) [4], [5] and energy harvesting

3 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 Fig.. Typical low-if integrated receiver. [6]. Because a RX generally does not know when it will receive a signal, it is normally on. I the device only receives inormation or a small period o the time that it is on, then a lot o power is wasted. One method to get around this problem is to use a WuRX. The WuRX has been studied in [4] and [5] or use in wireless sensor nodes where the role o the WuRX is implied in its name. Another possible energy saving scheme is to use energy harvesting. An obvious energy harvesting scheme is to use solar cells to power the RX. However, it is potentially cost saving to harvest electromagnetic energy i an external battery can be avoided. This was used in [6] to power a demodulating circuit or wireless sensor nodes. Intuitively, both o these energy-saving schemes can be used in conjunction with energy-aware design. It is well known that the gain requirement scales with input power and this act was exploited in [7] to scale the power consumption o the receiver with the gain requirement. However, the additional link between NF and input power proposed here was not made. The authors in [7] also proposed ultra-low start-up time in order to minimize the total energy used by a receiver. III. PRACTICAL ENERY AWARE LIMITATIONS A typical low-if integrated receiver is shown in Fig.. Energy-aware receiver design relies on a receiver s ability to regulate its power consumption based on the in-situ required speciications. However, any practical receiver design has overhead power requirements which can be considered ixed. For example, the power consumption o the requency synthesizer has little correlation with the overall NF o the receiver. Although we can conceivably adjust the requency synthesizer s output power based on the required NF, there is still a minimum power consumption required by such circuit blocks as the requency dividers and phase-requency detector. The goal o the receiver designer thereore should be to minimize the overhead power consumptions, and try to compensate or the degraded noise perormance using blocks whose noise perormance depends heavily on power consumption. This leads to our proposed design methodology. By pushing the requirements o the receiver to the ront-end LNA, we can increase the amount o controllable power consumption in the receiver. This obviously leads to a more energy-aware design. Fig. 3. Model o the proposed RF ront end. The LO is supplied by an external signal generator. In order to push the requirements to the LNA, the LNA must be able to provide a high voltage gain. Furthermore, in order to compensate or the high LNA gain, all subsequent blocks up to and including the channel-select ilter must exhibit high linearity. High linearity can be achieved in the down-conversion and channel iltering stages by using passive mixers and active-rc iltering []. The biggest limitation on the controllability o the receiver power consumption is in the power consumption required by the requency synthesizer. In [], and [8], the requency synthesizer required 9.7 mw, and mw, respectively, while in [9] it required just.4 mw. All requency synthesizers were designed using CMOS or the IEEE standard but [] and [8] used.8 µm technology and [9] used.3 µm technology. Improving technology and requency synthesizer architectures can thereore lead to very low power overhead or the requency synthesizer. Another required power overhead is due to the bandwidth requirements o the op-amps used in the channel ilter. In order to prevent intermodulation o high requency intererers, the channel ilter must be linear over the entire system bandwidth which is 83.5 MHz in the case o the IEEE standard []. This system bandwidth directly relects on the bandwidth requirements o the op-amps. Lastly there is some power overhead required by support blocks such as bandgap reerences and calibration circuitry. I. FRONT END DESIN AND ANALYSIS A model o the proposed energy-aware ront end is shown in Fig. 3. The LNA consists o a step-up impedance transormer ollowed by a variable gain/power transconductor. The transconductor is loaded by the output impedance o the LNA and the input impedance o the quadrature passive mixers. The quadrature passive mixers provide current-mode outputs to a pair o op-amp based transimpedance ampliiers (TIA). The LO signal is split into I and Q phases using a two-stage poly-phase ilter (PPF) which is not shown. The phase splitter reduces the signal swing o the LO which degrades the noise and conversion gain perormance o the down-conversion mixer. Rather than buer the LO, we chose to compensate or the reduced down-conversion mixer perormance with a higher gain

4 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 operating requency in radians per second, C gs is the gate source capacitance o M /M and α is a constant approximately equal to one. I, or example, ω T /ω is equal to times, we can expect a quality actor o around 5 which is signiicantly higher than the quality actor o the matching inductor. Thereore to irst-order, we can ignore the contributions o the series gate resistance to the input impedance. The impedance transormation results in a voltage gain o, ω LQ L = (5) Rs Fig. 4. The proposed Energy-Aware LNA with biasing shown. The biasing voltages are ed rom current mirrors. LNA. This leaves more room or gain control o the LNA. A. Low- oise Ampliier Design As the perormance requirements o the receiver were pushed back to the LNA, the LNA is by ar the most critical block in this design. The LNA must achieve high gain and low power consumption while allowing variable power control. At the same time, the LNA should be matched to 5 Ω and the input impedance should be independent o the gain state. We chose a two-stage design with current reuse in order to maximize the gain per power dissipation. Deep n-well transistors were used in order to tie the transistor bulk terminals to their respective sources. This was necessary to prevent an increase in the threshold voltage o the cascade transistors due to the body eect []. By keeping a low threshold voltage, the transit requency ( T ) o the devices is maintained at a high value. All three inductors are 6.9 nh with a quality actor (Q) o 8. at the operating requency. Additional resistors were added in parallel to the inductors (not shown in Fig. 3) in order to broaden the matching-bandwidth or the matching inductor, and the gain-bandwidth or the load inductors. ) Input Matching The input o the LNA was matched to a 5-Ω source using a high-pass LC matching network. Compared to a low-pass matching network [], a high-pass matching network requires only a single inductor (versus two) which can make use o mutual coupling between the coils to boost the eective inductance resulting in considerably smaller die area usage. An additional -kω resistor (not shown in Fig. 3) was added in parallel with the input inductor in order to broaden the matching bandwidth. The overall Q o the matching network is thereore approximately.6. Note that we can consider the input impedance o M /M as a capacitor with a quality actor o Q Cgs 5g d 5ω T (4) ω C αω gs which is equal to.3 db or this design. L is the inductance, Q L is the quality actor o the inductor including the additional parallel resistor, and R s is the source resistance. From (4), we can see that in order to get a wide matching bandwidth and high gain, we need a large inductor, however, this is only true or the irst order matching network used. Higher-order networks can oer high gain over a broader bandwidth while maintaining matched input impedance [3], [4]. As the power consumption o the LNA is changed with the gain state, the device capacitances o all transistors and most importantly, M and M, are also changed. These changing device capacitances could potentially alter the requency at which the LNA is matched to the 5- Ω source. We can reduce this eect by ensuring that the resonant requency between the matching inductor and the device capacitances is signiicantly higher than the operating requency (.4 Hz). The same holds true or the two load inductors. Obviously this puts a restraint on the minimum T o the devices. ) oltage ain The LNA actually consists o three isolated gain stages with the last stage being a transconductance stage loaded by a inite Q inductor and the passive mixer. The irst stage is due to the matching network described above. The second gain stage consists o a -I conversion by M and M, and an I- conversion by the irst load inductor. The output impedance o the cascode -I converter consisting o M -M 4 is signiicantly higher than the parallel parasitic resistance o the irst load inductor. As a result, the gain o the second stage can be closely approximated as, = g m ω LQ (6) L where g m is the transconductance o M and M, and Q L is the quality actor o the load inductor. The inal stage o the LNA is loaded by the quadrature passive mixer and an inductor o the same inductance and Q as the previous stage. The biasing and device sizes are the same as the second stage resulting in the same g m. Thereore, with mix as the input conductance o the passive mixer, the overall voltage gain is, where g d is the zero-ds drain-source conductance, ω is the

5 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 Fig. 5. Simulation o the settling time o the receiver. The receiver settles to the desired state within approximately µs. Fig. 6. A model o the LNA-mixer-TIA interace. A Norton equivalent circuit o the LNA is used with an R-L output impedance. ( g ω LQ ) m L ωlql L A ωlqlmix + Rs = (7) In order to achieve suicient gain-bandwidth, Q L was reduced rom 8. to approximately 3.4 using additional resistors parallel to the load inductors. Our expression, (7), shows that the LNA gain is proportional to g m. 3) oise Perormance Under matched conditions, the NF o an LC matching network is 3 db. This sets the minimum NF o the LNA. However, with suicient voltage gain in the matching network, the noise contributions o the rest o the circuit can be made small. Inductive degeneration [5] can be considered as an alternative to simple LC matching in order to optimize the noise perormance, however, there are tradeos. Firstly, with inductive degeneration, the matching gain is still determined by the inductance. With the same total inductance (6.9 nh, or the same gain) and Q (8.) actor, the series resistance o the inductance is 3.7 Ω. This is enough to achieve -3 db return loss making the addition o a degeneration inductor pointless. In order to enjoy the low-noise beneits o inductive degeneration, the largest inductor would need to be implemented o-chip (bondwire perhaps). Secondly, inductive degeneration requires at least one additional inductor. Lastly, and perhaps most importantly, the input resistance oered by inductive degeneration is proportional to the transit requency o the device [5]. As pointed out previously, an energy-aware LNA requires a changeable operating point. Changing the operating point aects the transit requency o the devices and thereore indirectly changes the input resistance. 4) Switching Time As changing the gain state o the receiver involves a change in the operating point, the receiver must be able to change state ast enough to meet requirements. The IEEE standard speciies a 8 µs preamble [] at the head o each data packet which can be used or the PLL and AC to lock. An advantage o designing the gain control in the RF section is that RF circuitry is designed with short time constants. Thereore, the circuits can reach steady-state quickly. Fig. 5 illustrates the settling time o the receiver power consumption as the receiver goes rom the highest gain state to the lowest gain state. The receiver requires approximately µs or the current consumption to be within % o the steady-state value leaving ample time or the PLL to lock. B. The Passive Mixer Passive down-conversion was chosen over active down-conversion or the better licker noise perormance, linearity and power consumption. The tradeo is lower input impedance and conversion gain, and poorer thermal noise perormance. A double-balanced passive mixer is shown in Fig. 6. The passive mixer provides a current-mode output to an IF TIA. In a ull RX design, the TIA can be replaced by an active-rc ilter [] using a similar op-amp. Ignoring the requency translation, to irst order, the current-output passive mixer can be analyzed as a simple op-amp in shunt-shunt eedback. Although the perormance will be somewhat dierent, we can use this simpliication to make a ew general statements about the eatures o the topology. Increasing the conductance o the switches lowers the input impedance, improves the conversion gain, and improves the noise perormance. However, this also reduces the loop-gain and increases the loading to the CO. At requencies below the dominant pole requency o the loop-gain, this degrades linearity (IIP 3 or example). Above the dominant pole requency, the loop-gain is almost independent o the switch conductance. This is an important dierence between direct-conversion and low-if (MHz-range IF) receivers. As previously pointed out, the requency translation introduces an additional dimension to the analysis which reduces the accuracy o the simple eedback op-amp model. The next ew subsections will discuss the dierences in the context o conversion gain by looking at three main parts: the LNA-mixer interace, the mixer core, and the mixer-tia interace. For the LNA-mixer interace, we are mainly concerned with the passive mixer s input impedance since (7) shows that it will aect the LNA voltage gain. For the passive

6 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 6 convolution matrices or T () to T4 () [6]. I only the irst two harmonics are considered, then the result is, Fig. 7. Decomposition o g T(t) in the time and requency domain. (a) g T(t) (b) T() (c) pulse train in time (d) pulse train in requency (e) the sampling unction in time () the sampling unction in requency. (e) and () show the sampling unction or two dierent sampling unction widths. mixer core, we will concentrate on the conversion gain rom the switching transistors to the IF. For the mixer-tia interace, we are mainly concerned with the output impedance which as mentioned, aects loop stability and linearity. We will set up our analyses by briely discussing convolution matrices [6]. ) Convolution Matrices A simple model or the time-varying conductance o a single switch (Fig. 6) in the ON state is, g ( t) = K ( cos( ω t) + ) (8) T LO LO T where K is a constant which depends on the switch sizes and the technology, LO is the LO signal swing, is the bias voltage across the gate and source o the switches, and T is the threshold voltage o the switches. In the OFF state, g T (t) =. As the LO is available in quadrature phases, we can deine LOI p by (8). For the switches driven by LOI m, LOQ p and LOQ m, the cosine in (8) is replaced by negative cosine, positive sine and negative sine respectively. The conductance o these switches are g T (t), g T3 (t) and g T4 (t). It should be noted that (8) assumes that the LO signal appearing at the sources o the switching transistors is negligible, which is true or typical biasing conditions. In practice, LO leakage to the mixer input is dependent on the output impedance o the LNA, and it can in turn change the conductance o the switching transistors. However, since we have assumed no leakage, the mixers operation is independent o the LNA output impedance. From Fig. 7, we can see how g T (t) to g T4 (t) can be mapped into the requency domain. g T (t) is a convolution between an impulse train and a sampling unction which in the requency domain is represented by a multiplication between a requency domain impulse train and a requency domain sampling unction. A mixer multiplies in the time domain, and hence the output in the requency domain is a convolution o the input and T (). T () only has values at discrete requencies because we assumed that the LO is periodic. We can thereore write = T () (9) = T () () j = T 3() j j j () j = T 4() j j () j where we have limited T () to a three-by-three matrix or simplicity. Note how the - in (9) and () is in-phase while it is out-o-phase in () and (). This is a simpliication since in a real MOSFET, the internal capacitances o the device result in both in-phase and out-o-phase components or each term in (9)-(). The subscripts, n, or each entry correspond to RF + n LO. The convolution matrix components or T () to T4 () are given in terms o those calculated or T (). As an example o how to use the convolution matrices, assume we apply a small voltage, A which has a spectral component at RF, across a switch governed by (9). We can calculate the output components at the zero, positive and negative sidebands as, I A, I I A, RF LO A, RF RF + LO = A (3) This is obviously just a simple extension o Ohm s law. We can then use Kirchho s laws to analyze the entire mixer. The TIA s op-amp is assumed to be ideal at IF requencies and hence the IF bandwidth is not apparent rom our derivations. Let Y TIA be the TIA input admittance, and RF the voltage across the mixer input terminals. Thereore, we can write, X Y = = ( T + T + Y TIA ) ( T T ) RF ( T3 + T4 + Y TIA ) ( T3 T4 ) RF (4) (5) where X and Y are deined in Fig. 6. At high requencies, the op-amp gain tends to zero, and we can approximate the TIA input admittance as R in parallel with some node capacitance,

7 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 7 Fig. 8 Comparison between theoretically calculated and simulated conversion gain (C in /), input conductance ( mix) and output conductance ( out). In simulation, the LO was.45 Hz, 5 m pk per phase. C X. ) The L A Mixer Interace Based on the above discussion, we can derive the passive mixer s dierential input conductance as, mix 4 + R ( s C + ) R X (6) where s equals to π( RF + LO ). The irst term,, can be seen by inspection. However, an additional term arises ollowing our assumption that the TIA input impedance tends towards R C X at high requencies. From Fig. 6, the input signal is up-converted due to T and orms a voltage at X. This high requency signal then gets down-converted through T which is out-o-phase o T resulting in an overall negative input admittance term. Similar paths exist through T3 and T4. I the op-amp bandwidth were ininite, this additional term would not arise. The additional term in (6) is beneicial in that it increases the input impedance o the passive mixer, and it would seem that i R is large and s C X is minimized, can be made equal to, the input impedance would be ininite. The ratio / is dependent on the peak to average conductance o the switches, and tends towards a value o one as the duty cycle o the switches is reduced [7]. The ratio o to s C X will depend on the technology used and the requency o operation. Clearly or s C X to be considered negligible, the technology s T would have to be at least an order o magnitude higher than the operation requency. Taking into account the op-amp s input capacitance, s C X was ound to be signiicantly greater than in our design. 3) The Mixer Core As with our analysis o the input admittance, we can calculate the conversion gain o the passive mixer as, IFI RF IFQ RF R j R R ( s C + ) 4 j + R R X ( s C + ) R X (7) (8) The term - R can be seen on inspection due to the shunt-shunt eedback coniguration. Needless to say, solving the problem using higher order matrices will lead to more complex solutions. Once again we note that s C X is large and it thereore limits the inluence o the term involving. 4) The Mixer TIA Interace The op-amp is conveniently designed as a two-stage ampliier where the irst stage provides gain and the second stage is used to drive the output impedance. Assuming the second stage is a transconductance, m, and the irst stage provides gain, A, it is easy to see that the loop-gain o the TIA is A m / out, where out is the output conductance o the passive mixer. Reducing out improves the loop-gain thereby improving the linearity o the TIA while also degrading its phase margin. The resonator at the output o the LNA can be approximated as having conductance L A (equal to (ω LQL ) - ) at RF and ininity at other requencies. We can then calculate out as, out + L A + mix (9) We can see rom (9) that the output impedance o the passive mixer depends not only on the conductance o the switches, but on the output impedance o the LNA. Note that C X was assumed to be part o the TIA. The second term in (9) results rom mixing up and then back down in requency. The output impedance was calculated using three-by-three matrices rather than ive-by-ive due to the computational diiculty. 5) Accuracy o the Analysis Equations (6), (7), and (9) and their simulated counterparts are plotted versus the switch width in microns ( n were extracted rom the simulation o a single MOSFET). They are plotted on a log scale to illustrate how the theoretical results can be itter to the simulated data by adding a multiplicative actor. Ignoring the accuracy, the trend derived in the equations holds true in simulation. As mentioned earlier, a real MOSFET includes a distribution o capacitances and resistances which were not modeled by our simple model, and this is the biggest actor contributing to the equations inaccuracy. 6) Overall Implementation Based on the preceding analyses, we can optimize the switch size, LO strength, and R. Increasing the LO voltage improves the conductance o the switches without greatly aecting the switches capacitance. Thereore, or minimum capacitive loading to the requency synthesizer and LNA, we should maximize the LO voltage. We chose a 5 m peak per LO phase as this value does not require excessive driving capability o the LO. For R, we note rom the section above that R, to irst order, does not aect the op-amp loop-gain. However, i the non-dominant pole is at the output o the op-amp, then a smaller R leads to higher op-amp unity-gain bandwidth. As a compromise between overall voltage gain ((7) and (8)), and bandwidth, we selected R as 4 kω. The simulation data in Fig. 9 illustrates the optimization o the switch width. When using

8 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 8 Fig. 9 Switch width optimization including input-reerred noise (IRN), op-amp loop-gain, and voltage gain. The LO was.45 Hz, 5 m pk per phase. Fig. A micrograph o the abricated design. Fig. The op-amp or the transimpedance ampliier Fig. 9, we must take into account the increasing mix (Fig. 8) loads down the LNA thereby reducing the LNA voltage gain (this is evident rom (7)). Thereore, there is an optimum width or minimum overall NF. For the LNA output impedance, o 88 Ω, this was ound to be 4 µm, but because larger switch size is more orgiving in terms o process variation, we chose a switch width o 5 µm. C. The Transimpedance Ampliier The ully-dierential op-amp is shown in Fig.. The input dierential pair uses parasitic NPN transistors which provide better matching, -oset and licker noise perormance than MOS devices [8]. In a CMOS process, NPN bipolar junction transistors (BJT) are ormed using the deep n-well, p-well and n-well layers. The current consumption o the op-amp is deined by PMOS current sources, and common-mode eedback (CMFB) is used in the output stage to set the input and output common-mode voltages to. This common-mode voltage propagates back to the input o the passive mixer. Miller compensation was used to set the phase margin to 6 degrees. The TIAs were designed to consume µa each rom the.8 supply.. IMPLEMENTATION AND MEASUREMENT The system described in Fig. 3 was implemented in a Fig. NF o the LNA in all our gain modes. low-cost 6 metal poly.8 µm RF CMOS process with a.5 µm top metal. Fig. shows a micrograph o the abricated design. The LO polyphase splitter was implemented on-chip as a two-stage RC polyphase splitter. This was done in order to reduce the pad count. Due to the limitation on the number o RF probes which could be used, the biasing circuitry was implemented using on-chip resistors. The drawback is that current consumption o the chip can deviate signiicantly rom the designed value. We used a constant-g m biasing circuit [] or the LNA with a resistor which could be varied in three steps. This is an extremely simplistic method or gain tuning and in retrospect, a more robust method involving power detection should have been used. Such circuits are readily ound or gain control in automatic gain-control (AC) loops [] and oten involve decision making by the digital signal processor (DSP). A. Measured L A Perormance The LNA was characterized or matching, noise, gain and linearity perormance. The NF in all our gain modes is shown in Fig.. The LNA achieves a 6 db NF in the 5 ma mode. The input relection coeicient and gain are shown in Fig. 3. From Fig. 3, the LNA matching requency shited down to.5 Hz. However, the two other resonating nodes in the LNA did not experience the same requency shit. As a result, the voltage gain requency response is somewhat distorted. The result was a decreased center requency gain, and a corresponding increase in the minimum NF. The IIP 3 was measured to be -.5 dbm in

9 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 9 Fig. 3 oltage gain and input relection coeicient o the LNA in all our gain modes. Fig. 5 SSB NF o the ront end in all our gain modes. LO was ixed at.3 Hz, dbm. Fig. 4 Measured IIP 3 (dbm) versus gain mode (ma) or the LNA only and the ull ront end. the highest gain mode and showed slight improvement ( db) in lower gain modes. This is shown in Fig. 4. Although the gain drops in lower gain modes, the bias point changes somewhat osetting the improvement in IIP 3. The LNA was designed or a gain step o 6 db. However, as previously mentioned, the biasing network was designed using on-chip resistors due to a limitation on the number o probes. Unortunately, the measured bias current deviated signiicantly (around 5 % in 5 ma mode) rom the nominal value resulting in a change in the gain step. Future iterations o this work will use a more accurate gain-step. B. Measured Front End Perormance The ront end was characterized or noise, gain, linearity and power consumption perormance. The noise igure and conversion gain o the ront end were measured using the Agilent E447B spectrum analyzer which has a built in noise igure personality. Unortunately, neither the spectrum analyzer nor our noise source were designed to be used below MHz. The current consumption in the highest to lowest power modes are 5. ma,.97 ma,.88 ma, and.39 ma respectively with a.8 supply. From Fig. 5, the ront-end single-sideband (SSB) NF is around 9 db (approximately 6 db double sideband (DSB) NF) in the highest gain mode and increases with the reduced LNA gain. The ront end gain, as seen in Fig. 6, agrees with the LNA gain. The IIP 3 or the ront end is -3 dbm in the highest gain mode and improves with lower LNA gain. This is Fig. 6 Conversion gain o the ront end in all our gain modes. LO was ixed at.3 Hz, dbm. shown in Fig. 4.This was suicient or our application but can be improved by increasing the loop-gain o the op-amps. The ront end gain o 35 db in the highest gain mode is suicient such that the noise perormance o the subsequent blocks can be made insigniicant without requiring high power consumption. Table I shows a comparison between the proposed design and current literature. The NF quoted in this work is SSB NF while that in [] is DSB NF. [] and [9] use image-reject mixers which are able to suppress the noise in the image band, however, The work in [9] uses two IFs and it is not clear how well the irst image noise is suppressed. The authors o [] used high Q input matching and active mixing to achieve excellent NF or its current consumption. This came at the cost o a low IIP 3 and possibly high licker noise corner requency. It should be noted that the key point in [9] was the innovative use o a digital demodulator which allowed the authors to achieve a low overall power consumption and good perormance. I. CONCLUSION Communication between a mobile device and a ixed hub allows or energy-aware design o the mobile RX and TX where the mobile TX s output power is optimized and the mobile RX s sensitivity is optimized. This work has discussed the design and implementation o an energy-aware RX involving optimization based on several dierent input conditions rather than the

10 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < minimum sensitivity. A design methodology which simpliies the RX design was presented which involves pushing NF requirements to the ront end while only maintaining suicient bandwidth or proper iltering in the IF section. This allows greater control o the ront end power consumption. Following circuit analysis o the ront end blocks, measurement results o the proposed ront end were presented. The ront end power consumption exhibited up to 7 % reduction in power consumption with high input power. APPENDIX For a sinusoidal LO, and were calculated to be equal to LO = cos π sin cos = T LO π LO sin cos π TABLE I COMPARISON TO PRIOR PUBLISHED WORK Reerence This Work [] [] [9] Frequency (Hz) Current (ma) A.6.39 Noise Figure (db) 8.8 B 9.3 B.7 B 6.5 B IIP3 (dbm) oltage ain (db) C 43 - Technology (µm) A Entire analog ront-end included B SSB NF which is approximately 3 db higher than DSB NF C Only LNA gain included T T LO cos T LO + ( ) π LO + sin cos 4π T LO T T LO () +. () From () and (), i we were to bias the voltage-output passive mixer at the threshold voltage o the transistor (i.e. = T ), the ratio / would equal to π/4 which is -. db. This agrees with the analysis in [7]. ACKNOWLEDMENT The authors would like to acknowledge MediaTek Inc, Singapore or supporting this work. The authors would also like to acknowledge the help o W. M. Lim, and T. S. Wong, Nanyang Technological University, Singapore, in the on-waer measurement. Finally we would like to acknowledge members o the Designer s uide Community or many useul discussions. REFERENCES [] W. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, D. Eggert, A Fully Integrated.4-Hz IEEE Compliant Transceiver or ZigBee TM Applications, IEEE Journal o Solid-State Circuits, vol. 4, issue, pp , Dec, 6. [] I. Nam, K. Choi, J. Lee, H. K. Cha, B. I. Seo, K. Kwon, K. Lee, A.4-Hz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in.8-µm CMOS or IEEE WPAN Applications, IEEE Transactions on Microwave Theory and Techniques, o. 55, No. 4, pp , April, 7 [3] T K. Nguyen, N J. Oh,. H. Hoang, S.. Lee, A Low-Power CMOS Direct Conversion Receiver With 3-dB NF and 3-kHz Flicker Noise Corner or 95-MHz Band IEEE ZigBee standard, IEEE Transactions on Microwave Theory and Techniques, vol. 54, no., pp , Feb, 6, [4] T.-K. Nguyen,. Krizhanovskii, J. Lee, S. K. Han, S.. Lee, N. S. Kim, C. S. Pyo, A Low-Power RF Direct-Conversion Receiver/Transmitter or.4-hz-band IEEE Standard in.8- µm CMOS Technology, IEEE Transactions on Microwave Theory and Techniques, vol. 54, issue, pp , Dec, 6. [5] M. Camus, B. Butaye, L. arcia, M. Sié, B. Pellat, T. Parra, A 5.4 mw/.7 mm.4 Hz Front end Receiver in 9 nm CMOS or IEEE WPAN Standard, IEEE Journal o Solid-State Circuits, vol. 43, no. 6, pp , June 8. [6] A.. Do, C. C. Boon, M. A. Do, K. S. Yeo, A. Cabuk, An Energy Aware CMOS Front End or.4-hz ISM Band Low Power Applications, IFIP/IEEE International Conerence on ery Large Scale Integration, Oct 8 [7] T. S. Rappaport, Mobile Radio Propagation: Large-Scale Path Loss, Wireless Communications Principles and Practice, Second Edition, Upper Saddle River, NJ/USA: Prentice Hall PTR,, Chapter 4, pp [8] W. Sansen, Distortion in Elementary Transistor Circuits, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 3, March 999, pp [9] B. Razavi, Basic Concepts in RF Design, RF Microelectronics, Upper Saddle River, NJ/USA: Prentice Hall PTR, 998, Chapter, Section.., pp.. [] T. H. Lee, Noise, The Design o CMOS Radio-Frequency Integrated Circuits, nd Ed., Cambridge, UK: Cambridge University Press, 4, Chapter, pp [] P. orday, Multipath, Internet: ultipath.ppt, July 4 [Oct. 9]. [] R. Senguttuvan, S. Sen, A. Chatterjee, Multidimensional Adaptive Power Management or Low-Power Operation o Wireless Devices, IEEE Transactions on Circuits and Systems II: Express Bries, vol. 55, no. 9, Sept 8, pp [3] S. Lloyd, Challenges o Mobile WiMAX RF Transceivers, International Conerence on Solid-State and Integrated Circuit Technology, Oct. 6, pp [4] N. Pletcher, S. ambini, J. Rabaey, "A 65uW,.9 Hz RF to Digital Baseband Wakeup Receiver or Wireless Sensor Nodes, Custom Integrated Circuits Conerence (CICC) September 6-9, 7, San Jose, CA. [5] N. Pletcher, S. ambini, J. Rabaey, A Hz 5pW Wake-Up Receiver with -7dBm Sensitivity Using Uncertain-IF Architecture, IEEE International Solid-State Circuits Conerence, Feb. 8, pp [6] T.S. Salter, Bo Yang; N. oldsman, Low power receiver design utilizing weak inversion and RF energy harvesting or demodulation, International Semiconductor Device Research Symposium, Dec 7, pp. -. [7] D. Daly, A. P. Chandrakasan, "An energy-eicient OOK transceiver or wireless sensor networks", IEEE Journal o Solid-State Circuits, vol. 4, no. 5, May 7, pp. 3-. [8] P. Choi et al., An Experimental Coin-Sized Radio or Extremely Low-Power WPAN (IEEE 8.5.4) Application at.4 Hz, IEEE Journal o Solid-State Circuits, vol. 38, no., Dec 3, pp [9] C. Bernier, F. Hameau,. Billiot, E. de Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. incent, L. Ouvry, D. Lattard, M. ary, C. Bour, J. Prouvee, S. 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11 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < [] IEEE Standard For Local and Metropolitan Area Networks, 3. [] B. Razavi, Basic MOS Device Physics, Bandgap Reerences, Design o Analog CMOS Integrated Circuits, International Edition, Singapore: Mcraw-Hill,, Chapters and, Section.3 and., pp. 3-4 and 379. [] B.. Perumana, R. Mukhopadhyay, S. Chakraborty, C.-H. Lee, and J. Laskar, A low-power ully monolithic subthreshold CMOS receiver with integrated LO generation or.4 Hz wireless PAN applications, IEEE J. Solid-State Circuits, vol. 43, no., pp. 9 38, Oct. 8. [3] C. Bowick, Impedance Matching, RF Circuit Design, First Edition, Indianapolis, Indiana, Howard W. Sams & Co., Inc, 98, Chapter 4, pp [4] A. Ismail, A. A. Abidi, A 3- Hz Low-Noise Ampliier with Wideband LC-Ladder Matching Network, IEEE Journal o Solid-State Circuits, ol. 39, No., pp , Dec 4. [5] D. K. Shaeer, T. H. Lee, A.5-,.5-Hz CMOS Low-Noise Ampliier, IEEE Journal o Solid-State Circuits, ol. 3, No. 5, pp , May 997, [6] S. A. Mass, Harmonic Balance Analysis and Related Methods, onlinear Microwave and RF Circuits, nd Ed., Artech House, 685 Canton Street Norwood, MA 6, 3, Chapter 3, pp [7] A. R. Shahani, D. K. Shaeer, T. H. Lee, A -mw Wide Dynamic Range CMOS Front end or a Portable PS Receiver, IEEE Journal o Solid-State Circuits, vol. 3, no., pp. 6-7, Dec [8] I. Nam, K. Lee, High Perormance RF Mixer and Operational Ampliier BiCMOS Circuits Using Parasitic ertical Bipolar Transistors in CMOS Technology, IEEE Journal o Solid-State Circuits, ol. 4, No., pp. 39-4, Feb 5. [9] C. P. Chen, M. J. Yang, H. H. Huang, T. Y. Chiang, J. L. Chen, M. C. Chen, K. A. Wen, A Low-Power.4-Hz CMOS FSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion, IEEE Transactions on Circuits and Systems I: Regular Papers, ol. 56, No., Dec 9, pp Aaron. Do was born in Wellington, New Zealand in 98. He received the B.Sc degree rom The University o Texas at Austin in Electrical Engineering and the M.Eng degree rom Nanyang Technological University in Electrical and Electronic Engineering in 4 and 6 respectively. For the M.Eng degree, he specialized in LNA and Passive Mixer design or direct conversion receivers. He is currently working as a research associate in Nanyang Technological University, Singapore, while pursuing a Ph.D. part-time. His research ocuses on ultra-low power RF ront-end circuit and system design. Manh Anh Do obtained his BSc (Physics) rom University o Saigon, ietnam in 969, and BE (Elect) in 973, and PhD in 977 both rom University o Canterbury, New Zealand. Between 977 and 989, he held various positions including: design engineer, production manager, and research scientist in New Zealand, and senior lecturer at National University o Singapore. He joined the School o Electrical and Electronic Engineering, Nanyang Technological University (NTU) as a senior lecturer in 989, and obtained the Associate Proessorship in 996 and Proessorship in. He has been a consultant or many projects in the electronics industry, and was a key consultant or the implementation o the $ million Electronic Road Pricing (ERP) project in Singapore, rom 99 to. His current research is on mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. He has authored and co-authored 5 papers in leading journals and 4 papers in international conerences. Between 995 and 5, he was Head o Division o Circuits and Systems, NTU. Proessor Do was a council member o IET, UK rom to 4, and an Associate Editor or the IEEE Transactions on Microwave Theory and Techniques in 5 and 6. He is a Senior Member o IEEE, a Fellow o IET, and a Chartered Engineer. Currently, he is the Director o Centre or Integrated Circuits and Systems, NTU. Kiat Seng Yeo received his B.E. (Hons) (Elect) in 993, and Ph.D. (Elect. Eng.) in 996 both rom Nanyang Technological University, Singapore. Head o Division o Circuits and Systems and Proessor o Electrical and Electronic Engineering at Nanyang Technological University, he is a recognized expert in CMOS technology and low-power CMOS IC design. He gives consulting to multinational corporations and serves in the organizing and program committee o several international conerences as eneral Chair, Co-Chair, Technical Chair etc. Proessor Yeo s research interests include device modeling, low-power circuit design and RF IC design. He holds 5 patents and has published 4 books (International editions) and over 5 papers in his areas o expertise. Alper Cabuk received the B.Sc. degree in electrical engineering rom the Middle East Technical University (METU), Ankara, Turkey, in 999, and the M. Eng. and Ph.D. degrees in electrical and electronic engineering rom Nanyang Technological University (NTU), Singapore, in and 6. He was with the Inormation Technologies Institute (Bilten), Ankara, Turkey rom 998 to 999. Currently he is a research ellow in NTU, Singapore. His research interests include CMOS RF IC design, low-voltage low-power analog/baseband circuit design, and clock and data recovery circuits or SONET systems. Chirn Chye Boon received the B.E. (Hons.) (Elect.) in and Ph.D. (Elect. Eng.) in 4 rom Nanyang Technological University (NTU), Singapore. In 5, he joined NTU as a Research Fellow and became an Assistant Proessor in the same year. Beore that, he was with Advanced RFIC, where he worked as a Senior Engineer. He specializes in direct conversion RF transceiver ront end design, phase-locked-loop requency synthesizer, clock and data recovery circuit, and requency divider. Proessor Boon is a reviewer or IEEE Transactions o Circuits and Systems I, IEEE Microwave and Wireless Components Letters and IEEE Transactions on Microwave Theory and Techniques.