CprE 583 Reconfigurable Computing

Transcription

1 Project Proposals CprE / ComS 583 Reconfigurable Computing Group FPG Implementation of Frequency- Domain udio Effects Processor Five-band equalizer Frequency shifter Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State niversity ecture #5 Midterm Review October, 26 ect-5.2 Group 2 Transparent FPG-ased Network nalyzer ayer I pass-through ayer II passive analyzer Group 3 FPG-ased ibrary Design for inear lgebra pplications Floating-point sparse matri-vector multiplication Floating-point banded matri-vector multiplication Floating-point lower-upper matri decomposition October, 26 ect-5.3 October, 26 ect-5.4 Group 4 n Improved pproach of Configuration Compression for FPG-ased Embedded Systems Improved compression algorithms T-reordering techniques Others Projects: Group 5 FPG Ternary Data Conversion Group 6 nalysis of Sobel Edge Detection Implementations Group 7 Design and nalysis of rtificial Neural Networks on FPGs Reminders: /6 Project pdates ( minutes) 2/5-2/7 Final Presentations (25 minutes) 2/5 Final Reports October, 26 ect-5.5 October, 26 ect-5.6

2 Midterm Review sing the Silicon Computational Density (Qualitative) Intel Pentium 4 ctel ProSIC MMX SSE FFT ES MPP More Cache CISC Superscalar Vector Reconfigurable Fabric Reconfigurable Processor FPGs can complete more work per unit time than a processor or DSP: ess instruction overhead More active computation onto the same silicon area (allows for more parallelism) Can control operations at the bit level (as opposed to word level) October, 26 ect-5.7 October, 26 ect-5.8 Coupling in a Reconfigurable System Workstation Coprocessor ttached Processing nit Standalone Processing nit Generic FPG rchitecture FPG = Field-Programmable Gate rray CP F October, 26 Caches I/O Many places to put reconfigurable computing components Most implementations involve multiple discrete devices How should these devices be connected together? ect-5.9 Input/Output uffers (IOs) Configurable ogic locks (Cs) Programmable interconnect mesh October, 26 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Island-style FPG architecture ect-5. IO IO IO IO IO FPG Technology Various FPG programming technologies (nti-fuse, (E)EPROM, Flash, SRM): SRM most popular Ts and Digital ogic k inputs 2 k possible input values k-t corresponds to 2 k bit memory Truth table is stored 2 2k possible functions O(2 2k / k!) unique F = 2 ĀĀ2 Ā Ā Ā October, 26 ect-5. October, 26 ect-5.2 2

3 October, 26 rchitectural Issues [hmros4] What values of N, I, and K minimize the following parameters? rea Delay rea-delay product ssumptions ll routing wires length 4 Fully populated IMX Wiring is half pass transistor, half tri-state ect-5.3 October, 26 FPG rithmetic Traditional microprocessors, DSPs, etc. don t use Ts Instead use a w-bit rithmetic and ogic nit () Carry connections are hard-wired No switches, no stubs, short wires () ND2 OR2 XOR2 (2) DD S CMP Op (, 2) Out () 2-T Out Cin 3-T 3-T Cout Cout / Cin (2) 3-T 3-T Sum Sum ect-5.4 FPG rithmetic (cont.) rithmetic (cont.) X 3 X 2 X X Y Hard-wired carry logic support Carry save multiplication X 3 X 2 X X Y Y 2 Y 3 ltera FEX 8 Xilin XCV4 Z 2 Z Z October, 26 ect-5.5 October, 26 ect-5.6 N N 7 4-T October, 26 T-ased Constant Multipliers NNNNNNNN (N * (SN)) (N * (MSN)) SSSSSSSSSSSSSSSS Product N N 7 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T Constants can be changed in the Ts to program new multipliers 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4-T 4 5 S S 5 ect-5.7 Xilin Device Compleity Capacity Trends Virte-5 55 MHz 24M gates* Virte-II Pro Virte-4 45 MHz 5 MHz 8M gates* 6M gates* Virte-II 45 MHz Spartan-3 8M gates 326 MHz Virte-E 5M gates 24 MHz 4M gates Virte XC4 2 MHz Spartan-II MHz M gates 2 MHz 25K gates 2K gates Spartan 8 MHz XC3 XC52 4K gates 85 MHz 5 MHz 7.5K gates 23K gates XC2 5 MHz K gates Year October, 26 ect-5.8 3

4 Splash rchitecture VME us FIFO IN Control FIFO OT F 3 F 2 F F F 3 M 3 M 2 M M M 3 M 4 M 5 M 6 M 7 M 24 VS us F 3 F 29 F 28 M 3 M 29 M 28 M 25 M 26 M 27 FPG-based Router WGS Switch ackplane Connector OSC OSC MHz MHz JTG VRM:.8V Switcher OSC 62.5 MHz SRM 8Mbit ZT SDRM (backside) RD Reprogrammable pplication Device VirteE fg68 SRM 8Mbit ZT (backside) SDRM FPX Wash / R July, 2 J / MR RD Program SRM NID Network Device NID EPROM OC3 / OC2 / OC48 inecard Connector Reprog F 4 F M M 2 F 2 F 5 F M M 3 F 3 F 6 F 9 M 9 M 4 F 4 F 7 F 8 M 8 M 5 F 5 F 24 F 23 M 23 M 6 F 6 F 25 F 22 M 22 M 7 F 7 F 26 F 2 M 2 M 8 F 8 F 27 F 2 M 2 M 9 F 9 RD/NID Status FPX module contains two FPGs NID network interface device Performs data queuing RD reprogrammable application device Specialized control sequences October, 26 ect-5.9 October, 26 ect-5.2 Mesh Topology Chips are connected in a nearest-neighbor pattern Simplicity is key inear array is essentially a - dimensional mesh C D E F G H I Other Topologies Crossbar topology: Devices -D are routing only Gives predictable performance Potential waste of resources for near-neighbor connections C D W X Y Z October, 26 ect-5.2 October, 26 ect-5.22 ogic Emulation Emulation takes a sizable amount of resources Compilation time can be large due to FPG compiles Systolic rchitectures Goal general methodology for mapping computations into hardware (spatial computing) structures Composition: Simple compute cells (e.g. add, sub, ma, min) Regular interconnect pattern Pipelined communication between cells I/O at boundaries min c October, 26 ect-5.23 October, 26 ect

5 Finite Impulse Response Sequential bandwidth per output 2k O(k) cycles per output O() hardware Systolic bandwidth per output 2 O() cycles per output O(k) hardware Matri-Vector Product t = 4 a 4 a 23 a 23 a 4 t = 3 t = 2 t = a 3 a 2 a a 22 a 2 a 3 i n y t = n w w 2 w 3 w 4 y 2 t = n y 3 t = n2 y i y 4 t = n3 October, 26 ect-5.25 October, 26 ect-5.26 Circuit Netlist and Mapping T T4 Placing and Routing Programmable Connections FPG T T2 T5 FF T3 FF2 October, 26 ect-5.27 October, 26 ect-5.28 October, 26 Net Steps IRRY ieee ; SE ieee.std_logic_64.all ; ENTITY implied IS PORT (, : IN STD_OGIC ; eq : OT STD_OGIC ) ; END implied ; RCHITECTRE ehavior OF implied IS EGIN PROCESS (, ) EGIN IF = THEN eq <= '' ; END IF ; END PROCESS ; END ehavior ; VHD / VHD for Synthesis eq ect-5.29 October, 26 HW/SW Co-Design RM Core Cache RM ocal RMulator RM core simulator RMulator PI Comm. uffer Socket Handler Mem. ccess Socket Handler SOCKET # SOCKET #2 Modelsim FI H Slave H Master Modelsim H Slave M H Slave HD simulator H Master Comm. uffer SIC / FPG Shared ect-5.3 5

6 Multi-Contet FPGs Function nit rchitectures Input Streams Output Streams Multiply Custom Function Multiply RaPiD: Reconfigurable Pipelined Datapath inear array of function units Function type determined by application Function units are connected together as needed using segmented buses Data enters the pipeline via input streams and eits via output streams October, 26 ect-5.3 October, 26 ect-5.32 High-evel Compilation Other Topics? C Program SIF frontend C ibraries on various Targets Second course survey net week Provide general feedback, suggest additional topics Directives and utomation HW / SW Partitioner SIF to GCC C to RT VHD/Verilog C to RT VHD/Verilog GCC compiler for embedded VHD to FPG Synthesis VHD to SIC Synthesis Object code for Embedded (S) inaries for FPGs (Xilin) Chip layouts (.8u TSMC) October, 26 ect-5.33 October, 26 ect-5.34 Midterm Eam Three questions Review nalysis Etension ny paper mentioned in class is fair game Due in 48 hours (/2 2:pm) No class on Thursday! Some restrictions: Work alone Can ask if something is unclear ( what does this mean? questions, not how do I do this? questions) No late submissions strict WebCT deadline October, 26 ect