Design of A Novel Inductor less Low Noise Amplifier

Transcription

1 International Journal of Computer Sciences and Enineerin Open Access esearch Paper Volume-4, Issue- E-ISSN: Desin of A Novel Inductor less Low Noise Amplifier Parisa Tahizadeh, Abbas Kamaly*, Department of Electrical Enineerin, asa Branch, Islamic Azad University, asa, Iran Available online at: eceived: /Nov/6 evised: 6/Dec/6 Accepted: /Dec/6 Published: 3/Dec/6 Abstract A novel low noise amplifier is proposed usin low cost.8 µm CMOS technoloy. A resistive-capacitive feedback is used to extend the bandwidth of the amplifier. As the structure is inductor less, it is suitable for low cost interated optical interconnects. In this paper Improved Particle Swarm Optimization have applied to determine optimal trans-resistance and noise of proposed structure of amplifier. Simulation results showed a -3 db bandwidth of 5 GHZ with a trans-impedance ain of 6 db ohms. The total voltae source power dissipation is less than 5 mw that is much less than that of conventional transimpedances. The output noise voltae spectral density is 9.5 nv/sqrt(hz) with a peak of 5nV/sqrt(Hz), while, the input referred noise current spectral density is below pa/sqrt(hz) within the amplifier frequency band. Keywords TIA, CMOS, Noise, Amplifier. Introduction Low cost and hih performance are two important aspects to desin fiber-optic systems for local area networks (LANs). Clearly, this is not an easy task as such conditions are stronly dependent on technoloy as well as on the desin of the whole optical network. ecently optical electrical interated circuits have been successfully implemented by usin various technoloies such as SiGe, GaAs, Bipolar and CMOS. However usin CMOS technoloy provides advantaes such as: lower power dissipation, hiher level of interation and lower cost of fabrication. So, if a low price is the aim, the best choice is the use of CMOS technoloy [, ]. The liht propaatin throuh a fiber experiences a lot of loss at the end of the fiber before reachin a photodiode (PD). The PD transforms the liht into a proportional current. The photocurrent enerated by the PD must be converted to a usable sinal for further processin with a minimum amount of noise. A trans-impedance amplifier (TIA) converts and amplifies the photocurrent to a voltae sinal. TIAs are critical components in an optical receiver because of the speed, sensitivity and the noise performance of optical communication systems are mainly determined by the TIA. Desinin of TIA imposes several restrictive desin conditions: lare bandwidth, hih ain, low noise, and low power consumption. Amon all the preamplifiers reported in literature, those based on the current mode approach and shunt feedback TIAs present the best tradeoff between all desin conditions [3]. However, the current-mode preamplifiers consume hiher power and have larer noise. So, the shunt-feedback TIA offers the best trade-off between sinal-to-noise ratio and frequency response. The topoloy of a shunt-feedback TIA is shown in iure. It consists of a voltae amplifier with a resistive feedback loop where A(s) represents the transfer function of the open-loop amplifier and implements the feedback loop [4]. i.. Topoloy of a shunt-feedback TIA TIAs usually limit the receiver noise, and solutions beyond 5 Gb/s with noise performance adequate for the applications are challenin. Common-ate (CG) staes are known for their superior hih-frequency operation but they show unfavourable noise [5]. A modified approach miht alleviate the noise problem but at the price of power consumption [6]. The shunt-feedback TIA, traditionally has a low noise, but its bandwidth is limited [7]. In [8], capacitive-matchin technique [5], [6] is used, but still noise is unfavourable. Input series peakin is also used to cancel portions of the capacitance and lower noise at hih frequency [7]. In this work a new shunt-feedback TIA based on resistivecapacitive feedback is proposed. As the structure is inductor less, it is suitable for low cost interated optical interconnects. esistive-capacitive feedback is used to extend the bandwidth of the amplifier and minimize the noise. By selectin a suitable value for resistances, w/l of 6, IJCSE All ihts eserved

2 International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: all transistors and bias current the maximum transresistance and minimum noise could be achieved. This optimization problem is solved usin an evaluation alorithm named Improved Particle Swarm Optimization. This paper is oranized as follows. The desin of the proposed preamplifier is described in Sect.. The simulation results and optimizin procedure of the structure are summarized in Sect. 3. inally, the paper is concluded in Sect. 4.. Proposed preamplifier topoloy iure shows the topoloy of the proposed TIA. The transistor M acts as a common ate amplifier. The p-i-n photodiode converts optical sinal received by the amplifier into a current input. The circuit model for the external p-i-n photodiode [9] is shown in iure 3. The width of the input device M is optimized for noise operation []. The resistor is selected to supply the bias current for M and the thermal noise [, ]. The resistor is selected so that the bias current of M is almost the same as the photodiode current. So, should be much smaller than /m (>>/m). The resistor is the load of transistor M. Another alternative is to use NMOS or PMOS transistors in the linear reion. However, the short channel CMOS technoloies provide conventional poly resistors which usually need a much larer area. So, hih resistivity resistors reduce the required area and parasitic capacitance considerably. The value of is chosen hih enouh to provide sufficient output ain while not too hih to alter the low input impedance at the source node of M (/m). i. 3. Equivalent circuit model of photodiode. The source follower M alon with common ate stae M3 provide the second stae of TIA. A much larer fraction of the tail current flows throuh M compared to that flowin throuh M3 because M provides a hiher overdrive compared to M3. This helps to reduce the voltae division at the source of M. The tail current I tail is provided usin the circuit shown in iure 4. i. 4. The equivalent circuit model of the tail current. Vb photodiode 4 M5 Vb3 M4 M7 3 M6 Vb M M3 M Itail i.. Topoloy of proposed TIA. M8 Vout 5 The transistors M4 and M5 are selected for bandwidth extension. The impedance (Z L ) seen from the sources of M4 can be approximated by: sc s4 Cd4 ZL s C C C m4 m4 d4 s4 () Where C s4, C d4, and C L are the ate source, ate drain and load capacitances respectively. m4 is the transconductance of the transistor M4 and is the PMOS resistance. In this case the transfer function has two poles P, P and a zero Zp. By settin the zero to P, P becomes the dominant pole and improves the bandwidth. M6 and M7 act as the cascade stae to provide some additional ain alon with wide bandwidth. inally, source-follower (M8) is used to provide low impedance output. The resistive feedback () is applied from the drain of M7 to the drain of M thus helpin to lower the C time-constants at these hih-impedance drain nodes and avoid bandwidth bottlenecks. This ives total isolation L 6, IJCSE All ihts eserved

3 International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: of the hih photodiode input capacitance from determinin the 3dB bandwidth of the amplifier []. 3. Desin and optimization of preamplifier dominates the input referred noise. The input referred noise current of the trans-impedance amplifier can be written as [3, 5]: Trans-resistance, bandwidth, and noise are the key parameters for a preamplifier. However, the transresistance can depend only on by makin the open loop ain of the active part hih enouh causin to be set accurately [3]. So, as the ain of TIA is desined by settin of, two other parameters (noise and bandwidth) could be optimized by active part. Therefore, the active part should employ two staes, one optimized for noise and the other optimized for bandwidth. The first stae of proposed preamplifier is a common ate (CG) stae. The second part comprises of a common-drain (CD) stae and a CG stae. The desin of preamplifier is described as followin: A. Trans-resistance: The photocurrent enerated by the PD may be converted into a voltae by TIA. The trans-resistance is the relationship between these two electrical manitudes. As mentioned before, the value of may be chosen equals the trans-resistance of the proposed TIA. However, the open loop ain of the preamplifier may not be hih enouh so that the value of trans-resistance is exactly the value of. So, the value of should be selected and then be optimized. One important factor to select transresistance is the output sinal level which is dependent on the input current level, power supply, and the architecture. The input current level depends on the optical system, on the fiber and on the PD. An exact estimation of the amount of photocurrent is not easy. In the model used here for photodiode (iure 3) as input optical power varies from.mw to mw the photocurrent varies from 44 na to 4.4 μa respectively []. The architecture chosen here consists of three staes which provide the hih open loop ain. The open loop ain from the output voltae to current drain of M is shown in Eq. (). iure shows the sources of input referred noise for a common-ate stae. Since the common ate stae directly refers back the drain noise current to the input, the current noise source dominates the input referred noise. The input referred noise current of the trans-impedance amplifier can be written as Eq.(3) [3, 5] : m. m3. m6. m8 A.. 5 m8 m m3 B. Noise analysis: iure shows the sources of input referred noise for a common-ate stae. Since the common ate stae directly refers back the drain noise current to the input, the current noise source M Vn,in i.. Input noise sources for the common ate stae. In, in 3 m 3 m / 4KT / / / / In,in 4KT / (f ). C (f ). C qi db db C C qi s s C The first two terms in the above noise equation represents thermal noise contribution due to and. The next two terms in the equation are the noise contributions due to the ate leakae currents and are mostly neliible as their values are very small [3]. The last two terms in the equation are the channel thermal noises of the MOS transistors of M and M. The feedback resistor,, has been optimized for trans-resistance. The channel width of M has been optimized for frequency bandwidth. So the noise could be optimized by optimizin of the channel width of M. In fact, as in our case, if the active part of the TIA has a hih trans-resistance, the noise is mainly determined by the first stae [4]. So, the device of the input stae with the stronest impact on the total noise contribution is M, and optimizin the noise by optimizin W is loical. The noise values as a function of W is shown in iure. These results show that if the width of the input transistor is larer than µm the noise dependence on the channel width is low. To make a trade-off between the output voltae noise and input current noise, the channel width of M is selected w=5 µm. The frequency response of final structure is plotted in i.. Trans-resistance and bandwidth of final desined TIA are 63 dbω and 5.83 GHZ respectively. The output rms noise is.7 mvrms. s 6, IJCSE All ihts eserved 3

4 Az (Ohm) International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: Now that the trans-resistance and noise are introduced by their objective functions, so they could be optimized. 3- Desin and optimization of preamplifier 3-- Improved Particle Swarm Optimization (IPSO) Alorithms Intellient techniques have eneral acceptance because of their ability to find optimal results of complex and nonlinear optimization problems. A newer method named IPSO has been used for solvin the optimization problem. One of the advantaes of PSO method over older methods is more converence speed []. IPSO alorithm is an improved version of the PSO []. in some problems To enhance the converence of the PSO alorithm and to prevent losin of some important information in search space due to much emphasis on the best position for each particle (Pbest) and the best position for each particle (best), the information of other individuals should be considered and be shared durin the searchin process. This is the main idea in IPSO []. In each iteration exclude the best position of the m particles (Gbest) and the worst position of the m particles (Gworst), the averae of another (m - ) particles, called nominal averae position P of the swarm, ak, expressed as: m- X i( t) Pak = i m () So the velocity of the IPSO is updated as follow: ( t) v wv c r ( Pbest x ) () c r ( best x ) c r ( P x ) 3 3 ak Where c 3 is a constant and r 3 is a random number between and. The inertia weiht Eq., the position Eq.3 and other constants are as same as oriinal PSO. wmax wmin w wmax * iter iter max (3) x ( t) x v ( t) 3-- Objective function j =,,,n, =,,,m (4) The objective function is consistin of two terms: transimpedance and input referred noise current of the transimpedance amplifier for noise modelin. A..... m m 3 m6 m8 5. m8. m m3 () In, in 3 m 3 m / 4KT / / / / 4KT / ( f ). C (f ). C qi db db C C qi s s C s So the problem becomes an optimization problem which is solved usin IPSO. The control variables are, 3, 5, m m, m3, m6, m8 and f. Typical ranes of the optimized parameters are [. 5] for, [. ] for, [. ] for K, [. ] for K, [. ] for K, [. ] for K. As the power supply is equal to.8 V, the closed loop ain should be around KΩ to provide output levels of around mv. Takin this fact into account, must be in the order of kω. The value of could be optimized after the desin is completed. However, to show the influence of the value of on Trans-resistance, the ac analysis is performed for different values of. The result of this simulation is plotted in iure 5. As is clear from the fiure, the best value for is about 3 KΩ. The hiher values cause to reduce the -3 db bandwidth and lower values reduce the trans-resistance. The other parameters that can chane the trans-resistance are, 3, 4, and 5. The values of these resistors are selected in similar way. The values of these resistors are selected so that the hihest trans-resistance and bandwidth could be achieved. The optimum values of, 3, 4, and 5 are 3.5 K,.4 K,.8 K, and K respectively requency (HZ) x 9 =.5 K = K =.5 K =3 K =3.5 K i. 5. The trans-resistance of proposed TIA as a function of frequency for different values of. B. requency analysis: Now that trans-resistance is optimized by proper selectin of,, 3, 4, and 5, it is time to optimize the bandwidth. There are two complementary ways to achieve this oal; () by a proper choice of W/L and Ibias, and () by considerin frequency compensation. 6, IJCSE All ihts eserved 4

5 Power consumption (mw) 3 db bandwidth (GHZ) 3 db bandwidth (GHZ) International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: A startin point for bandwidth optimization should be to set both, W/L and I B,Mi, to those values at which the operatin frequency coincides with the maximum value of the transition frequency, f tmax. The Transistors M, M (and M3), and the bias transistor M9 have the most sinificant impact on transition frequency in proposed structure shown in iure. On the other hand, the power consumption is related to the width of M9. To optimize the frequency response, the W/L of M (M3) and M9 would be optimized. A trade-off also will be considered between power consumption and the bandwidth by proper selectin of M9. The W/L of M will be left for noise optimization in the followin subsection. or simplicity, the W/L of M, and M3 will be selected equally. The channel lenth is selected.8 µm for all transistors. The 3 db bandwidth of proposed structure as a function of W,3 is plotted in iure 6. As is clear from the fiure, the optimized value of W,3 is 5 µm W,3 (Micron) i. 6. The bandwidth of proposed TIA as a function of channel width of M,3 (W,3 ). The channel width of M9 also could be optimized to reach the hihest bandwidth and the lowest power consumption. iure 7 shows the 3db bandwidth and power consumption as a function of channel width of M9. These results show that if W9 is larer than 6 µm the 3 db bandwidth doesn t chane and is almost constant. This analysis reveals that the best trade-off between power consumption and bandwidth is achieved be choosin the W9=6 µm W9 (Micron) i. 7. The power consumption (top) and the bandwidth (bottom) as a function of channel width of M 9 (W 9 ). The second way for the frequency optimization is introducin frequency compensation. The proposed method in this work is based on a hih frequency compensation technique known as phantom zeros [4, 4]. This technique is one of the most efficient ways of frequency compensation [4, 4]. In this method, a zero is created somewhere in the feedback loop at the ede of the pass band. This zero is visible in the loop transfer function but not in the system transfer function. This zero allows placin the system poles in convenient positions. The quantitative analysis of the proposed structure in the hih frequency rane is both hihly complicated and ineffective. However, usin a qualitative analysis this work is made easier. Qualitatively, there are two critical nodes involved in the loop transfer function of the proposed structure. These nodes are located on either sides of. iure 8 shows the location of C used in phantom zeros technique. It should be pointed out that the previous results are simulated in presence of optimized value of C. In fact, without compensation, a peak will appear in the transimpedance frequency response of the circuit. To show the impact of C on frequency response of the circuit, the ac analysis is performed for some different values of C. The result shown in iure 9 reveals that the optimized value of C is f. The smaller values cause a hih peak in the frequency response and the bandwidth decreases. The larer values, on the other hand, decrease the bandwidth W9 (Micron) 6, IJCSE All ihts eserved 5

6 Trans-resistance (db ohm) International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: M5 4 M4 Vb3 M7 M8 Vo 3 5 M6 M M3 Vb Vb M Itail Photodiode C i. 8. The location of C used in phantom zeros technique Cf=. f Cf= f Cf=4 f Cf=6 f requency (HZ) x 9 i. 9. requency response with different values of C 6, IJCSE All ihts eserved 6

7 International Journal of Computer Sciences and Enineerin Vol.-4(), Dec 6, E-ISSN: Table summarizes the experimental results of the proposed topoloy and compares our structure with other recently published works. Performance [3] [6] [7] [8] [9] This work Technoloy (nm) Supply Voltae (V) Power (mw) Trans-resistance (dbω) NA 4 6 Bit rate (Gb/s) Output rms noise (mv rms ) NA NA.7 5. CONCLUSION This work has presented a preamplifier intended for fibre optic receivers. Low-cost is one of the most important advantaes of our proposed preamplifier thanks to the use of cheap CMOS technoloy. A ood trade-off between ain, noise, bandwidth, and power consumption has been achieved leadin to a hih performance desin. These characteristics make the proposed block a preferential option for LANs where all these characteristics are critical desin criteria. More concretely, the preamplifier is based on a resistive shunt-feedback topoloy and employs a frequency compensation technique, phantom zeros. The circuit is desined in a.8 V.8 µm CMOS process. Simulation results report a value for the trans-resistance of 6 dbω and a bandwidth of 5.83 GHz, respectively. eferences [] Z.Nosal, Interated circuits for hih speed optoelectronics International Conference on Microwaves, adar and Wireless Communications,, , (4). [] J. Pekarik, et. al., CMOS technoloy from.5 µm to 65 nm: The state of the art In Proceedins of IEEE Custom Interated Circuits Conference, pp. 7 4, (4). [3] B. azavi, Desin of interated circuits for optical communications McGraw Hill, (3). [4] Naderbeii, Mohamadreza Soltani, Iman Chaharmahali, "Optimization of a esistive Capacitive eedback Transimpedance Amplifier Usin IPSO Alorithm", International Journal of Computer Sciences and Enineerin, Volume-4, Issue-7, Pae No (-7), Jul -6 [5] Hamid Niyazi, akhralsadat asteari, Majid Pourahmadi, "Desin of A Novel esistive Capacitive eedback Transimpedance Amplifier", International Journal of Computer Sciences and Enineerin, Volume-4, Issue-6, Pae No (-7), Jun -6 [6]T.Takemoto,H.Yamashita,T.Yazaki,N.Chujo,Y.Lee,andY.Mats uoka, A 4 5-to-8 Gb/s 4.9 mw/gb/s -9.7 dbm hihsensitivity optical receiver based on 65 nm CMOS for boardto-board interconnects, in IEEE ISSCC Di. Tech. Papers, 3, pp [7] Dan Li, Gabriele Minoia, Matteo epossi, Daniele Baldi, and Enrico Temporiti, A Low-Noise Desin Technique for Hih-Speed CMOS Optical eceivers, IEEE JOUNAL O SOLID-STATE CICUITS, VOL. 49, NO. 6, JUNE 4. [8] Parnika De and Shailendra Sinh, "Enhancin Properties of iber Amplifier usin Quantum Dots", International Journal of Computer Sciences and Enineerin, Volume-4, Issue- 6, Pae No (3-3), Jun -6 [9] C. Toumazou, and S. M. Park, Wideband low noise CMOS transimpedance amplifier for iahertz operation, Electronics Letters, Vol. 3, No.3, pp , (996). [] Z. Chan, and W. M. C. Sansen, Low-noise, low distortion CMOS AM wide-band amplifiers matchin a capacitive source, IEEE Journal of Solid-State Circuits, Vol.5, No. 3, pp (99). [] B. azavi, Microelectronics,Prentice Hall, (998). [] Mohammad Emadi and Mohammad Baher Tavakoli, "Hih Gain, Wide Bandwidth and Optimal Swin op-amp in CMOS Technoloy", International Journal of Computer Sciences and Enineerin, Volume-, Issue-, Pae No (-5), Dec -4 [3] J. M. Garcia del Pozo, S. Celma, M. T. Sanz, and J. P Alere, CMOS tunable TIA for.5 Gbit/s optical Giabit Ethernet, Electronics Letters, Vol. 43(3), pp , (7). [4] C. Verhoeven, A. V. Staveren, G. Monna, M. Kouwenhoven, and E. Yildiz, Structured electronic desin Neative feedback amplifiers, Dordrecht: Kluwer Academic Publishers, (3). [5] D. A. Johns, and K. Martin, Analo Interated Circuit Desin, John Wiley and Sons, Inc., (997). [6] X. Chen, G. Wei, and L. Peh, Desin of low-power short distance opto-electronic transceiver front-ends with scalable supply voltaes and frequencies, In International Symposium on Low Power Electronics and Desin, pp. 77 8, (8). [7]. Aznar, W. Gaberl, and H. Zimmermann, A hihly sensitive.5 Gb/s transimpedance amplifier in CMOS technoloy, In IEEE International Symposium on Circuits and Systems, pp. 89 9, (9). 6, IJCSE All ihts eserved 7