A12 10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array

Transcription

1 . RESEARCH PAPER. SCIENCE CHINA Information Sciences June 2012 Vol. 55 No. 6: doi: /s A12 10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array LI ZhiQun, CHEN LiLi, LI Wei & ZHANG Li Institute of RF & OE ICs, Southeast University, Nanjing , China Received January 21, 2011; accepted May 27, 2011; published online September 17, 2011 Abstract This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 µm CMOS technology. Each channel incorporated a transimpedance amplifier and a limiting amplifier. To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s, an optimized circuit topology was proposed and some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, and active negative feedback. Against the power consumption, crosstalk and noise, some corresponding solutions were presented such as applying isolation structure for parallel amplifier array, and optimization of noise and circuit parameters for 10 Gb/s applications. The on-wafer measurements revealed that this chip s operation speed reached up to 10 Gb/s per channel, and 120 Gb/s with 12-channel in parallel operation. Consuming a DC power of 853 mw from a 1.8 V supply voltage, the chip exhibits a conversion gain of up to 92.6 dbω, and a 3 db bandwidth of 8 GHz, the output swing and input sensitivity for a bit-error rate of at 10 Gb/s are 310 mv and 10 mvpp, respectively. The chip size is 1142 µm 3816 µm including on-wafer testing pads. Keywords CMOS, parallel optical receiver, amplifier array, transimpedance amplifier, limiting amplifier, crosstalk, isolation structure, noise current Citation Li Z Q, Chen L L, Li W, et al. A Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array. Sci China Inf Sci, 2012, 55: , doi: /s Introduction The drastically increasing demands for large data capacity require high-speed interconnections with everincreasing data transmission rate. Multimode parallel optic-fiber links appear to be the most promising favored solution. Figure 1 shows the simplified block diagram of such a parallel link. In the transmitting module, 12 vertical-cavity surface-emitting lasers (VCSELs) are driven by an array of laser drivers to realize the electronic-to-optical conversion. At the end of the fiber-ribbon cable consisting of parallel multimode fibers, a receiver module receives the optical signal and recovers the original electric signal. The convert IC implements data processing including 8b/10b coding, parallel-to-series conversion, etc. This paper presents a complete front-end amplifier array that incorporates both transimpedance amplifiers (TIAs) and limiting amplifiers (LAs) in a 10 Gb/s 12-channel link, located in the receiver module driven by a linear photodiode array. Corresponding author ( zhiqunli@seu.edu.cn) c Science China Press and Springer-Verlag Berlin Heidelberg 2011 info.scichina.com

2 1416 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 1 Simplified block diagram of a parallel optic-fiber link. Figure 2 Optical receiver front-end amplifier architecture in a row of the array. For optoelectronic integrated circuits (OEICs) with high operation speed up to beyond 10 Gb/s, the design for low cost, low power consumption and high integration level becomes a real challenge. The frontend amplifier is the most critical element in an optical receiver affecting the whole system performance such as speed, sensitivity, and signal-to-noise ratio. Hence, the design mandates careful optimization of a number of tradeoffs among bandwidth, gain, and noise. The receiver front-end circuits operating at such high data rates are mainly dominated by SiGe, GaAs, and InP technologies [1, 2]. However, submicron CMOS technologies have recently become very attractive due to their low cost and high integration level characteristics. Therefore, such an amplifier array was designed and fabricated in a standard 0.18 μm CMOS technology. The paper is organized as follows. The circuit principle and architecture is presented in Section 2. Section 3 discusses the design aspects in detail. Noise optimization for each channel is separately described in Section 4. Finally, the simulated and measured results are presented in Section 5. Section 6 concludes this work. 2 Principle and architecture Figure 2 shows the single receiver channel architecture. The front-end circuit is driven by the photodiode (PD) and terminated by 50 Ω transmission lines. Herein, the PD is modeled by a current source i pd in parallel with a parasitic capacitance C pd with typical value of 0.5 pf. L bw and R bw represent the inductance and series resistance of the bonding wire, which are about 2.5 nh and 1.25 Ω, respectively. C pad denotes the parasitic capacitance of the bonding pad, which is about 0.1 pf. To alleviate bandwidth degradation caused by the input parasitic capacitance, a regulated cascode (RGC) input topology [3] is adopted in the TIA. Besides, the TIA employs active inductor peaking [4] and shunt feed-back technique

3 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No to widen the bandwidth. The single-ended TIA output is converted to a fully differential signal by the amplifier (A sd ) in conjunction with the low-pass filter (R sd and C sd ), which can be treated as a single-todifferential converter. The LA consists of a chain of three similar gain stages (A 1 A 2 and A 3 ), an offset cancellation amplifier (A 0 ), a low-pass feedback filter (R F, C F ) and an output buffer. The gain stage is chosen as a compromise between gain and bandwidth requirements. In this design, the TIA converts the photocurrent from the PD into a voltage signal for succeeding amplification, and LA amplifies the voltage swing to a logic level for data recovery. As explained in [5], the bandwidth of the amplifier must be minimized so as to reduce the total integrated noise while the limited bandwidth introduces intersymbol interference (ISI) in random data. The noise-isi trade-off appears to improve as the bandwidth goes from 0.7R b to 0.5R b where R b denotes the bit rate of data streams. In this design, 0.8R b is chosen because actual circuits may contain more poles, in addition process and temperature variations mandate additional margin. 3 Circuit design 3.1 Transimedance amplifier It is well known that the input parasitic components deteriorate the bandwidth and noise performance of the TIA. Especially, the photodiode capacitance is the main limitation. Figure 3 depicts a detailed circuit schematic of the TIA, which is composed of an RGC input stage (M 1,M 1, R S,M B, R B ), three cascaded common-source (CS) gain stage (M 2 M 5, R 2 R 4 ) with a shunt negative feedback (R f ) and an active inductor peaking (M 5, R 3 ). Employing the RGC topology as the input stage of TIA has the advantage of keeping the bias current stable. According to the small-signal analysis, as another important feature, which is useful for high-speed amplifier design, the RGC input mechanism obviously enhances the input effective transconductance. As a result, the input impedance of the amplifier is quite small, which is given by Z i = 1/[gm1 (1 + g mb R B )], (1) where 1+g mb R B is the voltage gain of the local feedback stage (M B, R B ) Obviously, the input impedance is 1+g mb R B times smaller than that of common-gate (CG) input. Thus, this RGC input stage relaxes the large input parasitic capacitance from the bandwidth determination than CG configuration. In addition, the enhanced input transconductance reduces the high-frequency noise contribution relating with the large input parasitic capacitance, which also can be seen from noise analysis in Section 4. With existence of RGC, the input node exhibits a nondominant pole at frequency f nd given by (2), and the dominant pole of the amplifier is decided by a high impedance node that is the drain of M 1. Meanwhile, the local feedback stage inherently produces a zero, causing a peaking in the frequency response at the frequency of f peak. In order to avoid this peaking from the bandwidth, either the resistance R B or the gate width W M1 of M 1 should be reduced. Through noise analysis in Section 4, W M1 should be carefully determined, and in this work, f peak is pushed beyond 16 GHz. } f nd C tot = 1/ {2π, (2) g m1 (1 + g mb R B ) f peak =1/[2πR B (C gs1 + C gdb )]. (3) Since the RGC input stage operates as a current buffer, a second-voltage-gain stage is required. In this work, three cascaded common-source-type voltage-gain stages are chosen to promise an enough high gain when proper bandwidth is guaranteed. With the negative feedback applied to the drain of M 1,the dominant pole moves to a higher frequency f d, and thus wider bandwidth can be achieved. Increasing R f properly while satisfying certain bandwidth can not only increase the transimpedance gain but also decrease the input noise current. According to the small-signal analysis of the proposed TIA, the 3 db bandwidth is approximately given by ( ) } f 3dB = fd Rf = 1/ {2π [C f (1 + A v )+C gd1 + C g2 ], (4) 1+A v

4 1418 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 3 TIA circuit schematic. Figure 4 frequency. Active inductor. (a) schematic; (b) small signal model; (c) the equivalent impedance Z ai as the function of where C g2 is the capacitance at the gate of M 2, which is given by C g2 C gs2 + C gd2 (1+A v ), C gd1 and C gd2 is the gate-drain capacitance of M 1 and M 2,C gs2 is the gate-source capacitance of M 2, C f is the parasitic capacitance of the feedback resistor, and A v is the open-loop voltage gain of the voltage-gain stage. If A v is so large to nullify the effect of C gd1 +C g2, the amplifier bandwidth becomes mainly limited by the feedback time constant R f C f. Additionally, the active inductor (M 5, R 3 ) in Figure 4(a) provides the proper shunt peaking as the load at the drain of M 3. From the small signal model in Figure 4(b), the equivalent impedance Z ai can be derived by (5). The impedance as the function of frequency is plotted in Figure 4(c). Z ai = 1+sC gs5 R 3 g m5 (1 + sc gs5 /g m5 ). (5) The inductive equivalent impedance between zero and pole causes a peaking increasing the bandwidth. Thus, the active inductor introduces a zero f z and a pair of complex conjugate poles to the transfer function of the TIA, and the part of the transfer function Z load3 becomes Z load3 = 1 g m5 1+sC gs5 R 3 1+s Cg4+Cgs5 g m5 + s 2 R3Cgs5 g m5. (6) The equation indicates that the numerator includes a zero ω z =1/(R 3 C gs5 ) and the denominator contains a pair of complex conjugate poles ω p1 and ω p2, which can be written as s 2 + s C g4 + C gs5 R 3 C gs5 + g m5 R 3 C gs5 =(s + ω p1 ) (s + ω p1 )=s 2 + s2ζω n + ω 2 n, (7) where ζ and ω n are the damping factor and the corner frequency of the complex poles, respectively. Note that the frequency response can be affected by the value of ζ. Forζ smaller than 1/ 2, a gain-peaking

5 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No characteristic can be observed at around ω n. Therefore, the bandwidth can be enhanced not only by zero but also complex poles. Thus, the bandwidth of the TIA is no longer mainly decided by (4) with the tuning of the active inductors. But the bandwidth cannot be increased indefinitely without stability problems by gain-peaking. In addition, this active inductor load is located away from RGC input to reduce dominating noise resources. Further noise analysis and optimization is important and necessary to improve the noise characteristics of the amplifier, which will be discussed in detail in Section Limiting amplifier As illustrated in Figure 5, the LA is composed of an amplifier core, a DC offset cancellation feedback circuit and an output buffer. The circuit principles and the design aspects used are similar to that of the 10-Gb/s limiting amplifier described in [6], in which a stage number of 4 is chosen for the LA circuit to achieve a balanced performance between the gain-bandwidth product and the noise figure. In this design, to save more power consumption and maintain appropriate gain and bandwidth, three cascaded 3rd-order gain stages adopting interleaving active feedback are utilized for the amplifier core see Figure 6. Each amplifier cell is realized by identical differential pairs with resistive load R while the active feedback is provided by the G mf cells. Considering the specifications such as time constant, voltage gain and output swing, the resistive load R L of 300 Ω and the transimpedance G m of 10.9 ms are therefore employed for the differential pairs in the amplifier cells. Particularly, the transimpedance of the first differential pair in the first gain stage G m0 is scaled down to 7.9 ms. It is significant to suppress the degradation of the bandwidth for the input high speed signal. The direct coupling is used between cascaded gain cells in the design. The DC offset cancellation, which is composed of an offset cancellation amplifier (A 0 )andalow-pass feedback filter (R F and C F ), is used to prevent the amplifier from being saturated by the offset voltage due to device mismatch. R F and C F are the passive elements used in the low-pass filter to extract the output DC level of the amplifier stages. The transconductance cell (M 3,M 4 ) in the feedback path is incorporated with the input differential gain pair (M 1,M 2 ), acting as a DC subtractor circuit for offset cancellation. Note that the feedback network presents a lower 3 db end of the bandwidth f c of the LA. And f c must keep as low as possible to eliminate the output droop in the presence of long runs of data. As aresult,τ = R F C F must be sufficiently grater than the longest permissible run to ensure negligible droop, that is to say, the required resistance and capacitance values must be enormous to minimize the effect of this droop. Considering the chip area occupied by the passive elements especially the capacitors, the tradeoff between the performance and area should be paid much attention to. To drive the testing instruments with 50 Ω transmission lines, an output buffer is included in the design. Considering the inherently low equivalent impedance at the output node, the buffer has to steer a high current to maintain a sufficient output swing. A pre-driver stage is therefore necessary to drive the output stage with fast transitions. However, the use of the output buffer presents a bandwidth bottleneck resulting from the large excess capacitive loading to the amplifier stages. To alleviate the bandwidth limitation, the output stage can be configured as a f T doubler [7], which reduces the capacitive loading by half. In Figure 7, a low-pass filtering network (R CM, C CM )isusedtoprovidem 2 and M 3 the same DC level (V CM )withm 1 and M 4. And the capacitive loading at node X and Y is two gate-source capacitance in series i.e. C gs /2 respectively. Thus the f T doubler circuit can help overcome the bandwidth limitation due to the use of large transistor sizes. The resistive load of output stage is scaled up from Ω, so that the current provided from I ss2 can be reduced effectively while maintaining the acceptable impedance matching. 3.3 Single-to-differential converter The TIA has a single-ended output, but the LA is required to provide a standard LVDS (low-voltage differential signals) level, so a single-to-differential converter is needed to insert between the TIA and

6 1420 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 5 LA architecture. Figure 6 circuit. Amplifier core schematic, consisting of three cascaded 3rd-order gain stages and interleaving active feedback Figure 7 Output buffer circuit. Figure 8 Single-to-differential converter circuit. the LA as shown in Figure 8, where the active inductor peaking is adopted to alleviate the bandwidth degradation. 4 Noise analysis and optimization The input node of each amplifier channel is most noise sensitive. Figure 9 gives the noise equivalent circuit of the TIA with an RGC input configuration including the channel thermal noise sources of the active devices and the thermal noise sources of the resistors. For simplicity, the noise contributions of two cascaded CS gain stages (M 3 M 5,R 3 R 4 ) are reasonably omitted. Using Kirchhoff s current law and the superposition theorem, the equivalent input noise current spectral density i n,eq of the proposed TIA is approximately given by (8) and (9),

7 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No Figure 9 Noise equivalent circuit of the TIA. R f1 = R f (1/g m1 ),C tot = Cpad + C gsb + C sb1,c 1 = Cgs1 + C gdb, C 2 = Cf + C gs2 + C gs1 +(1+g m2 R 2 )C gd2, and C 3 = Cgs3 + C gd3. In (8), k is Boltzmann s constant, T is the absolute temperature, γ is the noise factor of the MOSFET, and g d0 is the zero-bias drain conductance. Besides, C gsb (C gs1, C gs1, C gs2, C gs3 )andc gdb (C gd1,/, C gd2, C gd3 ) represent the gate-source capacitance and the gate-drain capacitance of M B (M 1,M 1,M 2, M 3 ) while C sb1 is the source-substrate capacitance of M 1,andC f is the parasitic capacitance of the feedback resistor. In addition, i n,eq and i n,i are the equivalent noise current spectral density at nodes 1 and 2, respectively. In the above calculations, it is assumed that all noise sources are uncorrelated. ( ) i 2 (1/R n,i = i 2 n,r s + i 2 n,r f + i 2 n,m1 + i 2 2 n,mb + s + ω 2 C i2 tot 2 ) n,r B (g mb +1/R B ) 2 ( ) ω + i 2 n,m1 + i2 n,r f + i 2 2 C 2 ( 1 n,m1 gm1 2 + = 4kT + 4kT +4kTγg d0,1 + 4kT(γg d0,b +1/R B ) R s R f + 4kTω2 C 2 1 g 2 m1 i 2 n,m2 + i2 n,r 2 ) (1/R 2 f1 + ω 2 C 2 2 ) g 2 m2 ( 1 (g mb +1/R B ) 2 Rs 2 ) (γg d0,1 + γg d0,1 + 1Rf + 4kT(1/R2 f1 + ω2 C2) 2 gm2 2 + ω 2 C 2 tot ) (γg d0,2 + 1R2 ), (8) i 2 n,eq =(ωc pd R bw ) 2 i 2 n,r bw +[(1 ω 2 L pd C pd ) 2 +(ωc pd R bw ) 2 ]i 2 n,i. (9) (8) and (9) implies two major methods that can be used to optimize the noise current i n,eq : a) Try to enlarge R s and R f to decrease the total equivalent input noise current spectral density while satisfying a required transimpedance gain and bandwidth of the TIA. b) Increase the gate width of M B to enlarge the value of g mb, nevertheless C gsb and C gdb keep increasing at the same time. From the g mb related item in (8), the gate width W MB of M B has an optimization value to minimize the equivalent input noise current spectral density. Similarly, W M1 and W M2 also have their optimization values according to (8) and (9). Taking W MB for example, the average input noise current spectral density versus the gate width of M B is simulated in Figure 10, which shows that the optimized width of M B is 80 μm. However, further optimizations of W M1, W MB and W M2 are necessary to achieve proper power allocation and tradeoffs between gain, bandwidth, and stability. 5 Simulation, realization and experimental results The proposed circuits in this paper are all fabricated by using 0.18 μm CMOS technology and measured on-wafer on the Cascade probe station by using 40 GHz microwave probes. Using an Agilent network analyzer E8363B, the S-parameters were taken from 0.1 to 10.1 GHz. To measure the transient response at 10 Gb/s, a pseudorandom bit stream (PRBS) is applied, which is generated from an Advantest D3186 pulse pattern generator. With an Agilent 86100A wide-bandwidth oscilloscope, the output eye diagrams at 5 and 10 Gb/s are measured. Using Agilent N8975A noise figure analyzer, the noise figure (NF) was measured from 0.1 to 10.1 GHz. To exam the performance of sub-blocks, we realized the individual TIA and LA circuit for on-wafer measurements, respectively. The chip photographs of the fabricated TIA and LA is shown in Figure 11.

8 1422 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 10 Average noise current spectral density as the function of W MB. 5.1 Sub-block TIA realization Figure 12 shows the measured response of the transimpedance gain Z T. This figure reveals that the transimpedance gain and the f 3-dB are 50 dbω and 7 GHz with an on-chip buffer on chip. The phase of Z T is linearly decreased with frequency as also illustrated in Figure 12. Figures 13(a) and 13(b) show the measured differential output eye diagrams at 5 Gb/s with the input voltage swing of 10 and 500 mv pp. Figures 14(a) and 14(b) show the measured differential output eye diagrams at 10 Gb/s with the input voltage swing of 10 and 500 mv pp. The measured RMS jitter proportion of the TIA in all cases above is less than 0.56 UI (unit interval). Operating under a 1.8-V supply, the TIA consumes about 29.2 mw, of which the output buffer plays a considerable part The noise characteristic of the TIA can be represented by a single noise current source referred to the input: i 2 n,eq = i2 n,in = v2 n,out ZT 2, (10) where v n,out is the total output noise voltage of the amplifier. The input-referred noise current which is equivalent to i n,eq in Section 4, i n,in of a TIA determines the minimum input current that yields a given bit error rate, directly impacting the link budget. Based on the definition of the noise factor F,the calculation formula of F can be transformed to (11). F = v2 n,out (v out /v in ) 2 1. (11) 4kTR s Thus, the equivalent noise current i n,in can be extracted from (10) and (11) as illustrated in Figure 15, and the calculation is under a 50-Ω condition, which is consistent with the on-wafer measurement environment. As can be seen, the measured and simulated i n,in exhibit a good agreement within the operation bandwidth. To investigate the effect of C pd on the noise characteristic, the simulated i n,in with different C pd values is presented in Figure 15. As predicted by (8) and (9), the capacitance related terms increase the noise current as the frequency increases. When a large C pd is applied, the C pd -related terms become dominant and noise current increases with frequency. In addition, the root mean square (RMS) noise current can be calculated by i rms n,in = 1 vn,out 2 (f)df. (12) R T 0

9 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No Figure 11 Microphotograph of the fabricated. (a) TIA; (b) LA. Figure 12 Measured transimpedance gain. Figure 13 5 Gb/s eye diagram with input swing of 10 mv pp (a) and 500 mv pp (b). (Horizontal scale: 50 ps/div, vertical scale: 50 mv/div) Figure Gb/s eye diagram with input swing of 10 mv pp (a) and 500 mv pp (b). (Horizontal scale: 20 ps/div, vertical scale: 50 mv/div) Figure 15 Measured i n,in and the simulated i n,in with different values of C pd.

10 1424 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 16 The gain-bandwith response of LA. Figure 17 5 Gb/s eye diagram with input swing of 5 mv pp (a) and 500 mv pp (b). (Horizontal scale: 50 ps/div, vertical scale: 50 mv/div) Figure Gb/s eye diagram with input swing of 6mV pp (a) and 500 mv pp (b). (Horizontal scale: 20 ps/div, vertical scale: 50 mv/div) In (12), R T is the midband value of Z T. By integrating (12) up to 10.1 GHz, the measured RMS noise current is 2.5 μa. A corresponding averaged input noise current spectral density of 29.9 pa/ Hz can be obtained, and the estimated sensitivity of the proposed TIA for bit error rate (BER) of is 35 μa for 10 Gb/s operation by extrapolation using the Q function [5]. 5.2 Sub-block LA realization Figure 16 shows the gain-bandwidth response of the LA circuit with the voltage gain of 42 db and bandwidth of 8.5 GHz. Figures 17(a) and 17(b) show the measured differential output eye diagrams at 5 Gb/s with the input voltage swing of 5 and 500 mv pp. Figures 18(a) and 18(b) show the measured differential output eye diagrams at 10 Gb/s with the input voltage swing of 6 and 500 mv pp.operating under a 1.8 V supply, the LA consumes about 68.4 mw. The differential output swing is about 310 mv. 5.3 Array realization The front-end amplifier array was implemented with a chip area of 1142 μm 3816 μm with on-wafer testing pads. Figure 19 shows the microphotograph of the fabricated chip. The crosstalk between the channels is a severe problem of such an array due to the high number of interacting channels, the high bandwidth and high gain of the amplifiers, the small channel pitch, and the long on-chip power supply and ground lines. Therefore, a PGR+NGR+DNW isolation structure [8] shown in Figure 20 was utilized to reduce the crosstalk between channels and suppress the substrate noise coupling, which had been verified by our experiments. Figure 21 shows the post-layout simulated gain response of the TIA, the LA and the whole front-end amplifier. Figure 21 reveals that the conversion gain and the f 3-dB of the TIA and the LA are 53 dbω, 7.9 GHz and 41.7 db, 8.5 GHz, respectively. And the front-end amplifier (FEA) provides a total gain of 92.6 dbω and 3 db bandwidth of 8 GHz. The low cutoff frequency of the amplifier is about 1 MHz for the trade-off of the chip area occupied by the low-pass filter passive elements.

11 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No Figure μm. Chip photograph of the amplifier array with the on-wafer testing pads. The size of the chip is 1142 μm Figure 20 PGR+NGR+DNW isolation structure. Figure 21 Simulated gain-bandwidth response of the optical receiver FEA. Figures 22(a) and 22(b) show the measured output eye diagrams of two adjacent amplifier channels at 5 Gb/s with the input voltage swing of 2 and 500 mv pp respectively. The output eye diagrams of two adjacent channels are very clear without obvious crosstalk. Typical measurement results are listed in Table 1, which shows that the adopted isolation structure isolates the parallel FEA effectively. Figures 23(a) and 23(b) show the measured output eye diagrams of a single amplifier channel with differential outputs at 10 Gb/s with the input swing of 10 and 100 mv pp, respectively. The eye diagram measurement results are listed in Table 2. And, the amplifier provides output voltage swing of 310 mv pp The measured

12 1426 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No. 6 Figure 22 5 Gb/s eye diagram with the input swing of 2 mv pp (a) and 500 mv pp (b). (Horizontal scale: 50 ps/div, vertical scale: 50 mv/div) Figure Gb/s eye diagram with the input swingof10mv pp (a) and 100 mv pp (b). (Horizontal scale: 20 ps/div, vertical scale: 50 mv/div) Table 1 Eye diagram measurement results of two adjacent FEAs at 5 Gb/s Channel No. Jitter RMS Single-ended output eye amplitude ps@2mV pp 139 mv@2 mv pp 8.1 ps@500 mv pp 137 mv@500 mv pp 11.7 ps@2 mv pp 142 mv@2 mv pp 5.9 ps@500 mv pp 139 mv@500 mv pp Table 2 Eye diagram measurement results of single FEA at 10 Gb/s Differential output Jitter RMS Single-ended output eye amplitude V out mv pp mv pp mv pp mv pp V out mv pp mv pp mv pp mv pp Table 3 Performance summary and comparison with other works Design This work Ref. [9] Ref. [10] Ref. [11] Process 0.18 μmcmos 0.18μmCMOS 0.18μmCMOS 0.35μmCMOS Function TIA+LA TIA+LA TIA TIA+LA BW (GHz) Speed (Gb/s) Gain (dbω) V dd (V) Power (mw) 73.8 per channel C pd (ff) Input-referred noise (µa rms) Inductor counts Chip area (mm 2 ) excluding pads of FEA Table 4 Design parameters of the TIA Design parameters (W/L) M1 15 µm/0.18 µm (W/L) M1 10 µm/0.18 µm (W/L) MB 32 µm/0.18 µm (W/L) M2 30 µm/0.18 µm (W/L) M3 30 µm/0.18 µm (W/L) M4 40 µm/0.18 µm R s 1.2 kω R B 150 Ω R Ω R Ω R Ω R Ω

13 Li Z Q, et al. Sci China Inf Sci June 2012 Vol. 55 No Table 5 Design parameters of the LA s amplifier core Design parameters (W/L) Gm0 (W/L) Gm (W/L) Gmf I ss I ssf R L 20 μm/0.18 μm 32 μm/0.18 μm 3.6 μm/0.18 μm 2.6 ma 0.43 ma 300 Ω Table 6 Design parameters of the LA s output buffer Design parameters (W/L) Gm0 (W/L) Gm (W/L) Gmf I ss I ssf R L 50 μm/0.18 μm 20 μm/0.18 μm 200 Ω 50 μm/0.18 μm 20 μm/0.18 μm 200 Ω Table 7 Design parameters of the single-to-differential converter Design parameters (W/L) M1,2 (W/L) M3,4 R sd C sd R L 20 μm/0.18 μm 20 μm/0.18 μm 1.5 kω 1pF 800 Ω RMS jitter proportion is less than 0.07 UI. Operating under a 1.8-V supply, the single front-end amplifier consumes about 73.8 mw. The circuit performance of this 10-Gb/s front-end amplifier is summarized in Table 3 together with prior works in [9 11]. Obviously, the proposed FEA is power, cost, and area efficient while manifesting comparable or even better performance. In addition, the design parameters of the total circuit are listed in Tables Conclusions A single-chip optical receiver front-end amplifier array for a Gb/s parallel optic-fiber link is developed using a standard 0.18 μm CMOS technology. The front-end amplifier provides a conversion gain of 92.6 dbω and 3 db bandwidth of about 8 GHz. An RGC input stage has been utilized to decouple the loading effect at the input node, and a wide bandwidth is achieved by means of shunt feedback and active inductor peaking. Design concepts have been discussed in detail and analyses of the noise current characteristics have been provided. In addition, an effective isolation structure has been employed to arrange parallel arrays of the FEA. From the measured results, the proposed circuit architecture is suitable for low-cost, low-noise, and low-consumption high-speed parallel data transmitting applications. To the best of the authors knowledge, the front-end chip consumes the least power from 1.8 V voltage supply based on CMOS technology. Acknowledgements This work was supported by National High-Tech Research & Development Program of China (Grant No. 2007A- A03Z454).

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