ESD. Circuits and Devices. Steven H. Voldman Vermont, USA

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1 ESD Circuits and Devices Steven H. Voldman Vermont, USA

3 ESD

5 ESD Circuits and Devices Steven H. Voldman Vermont, USA

6 Copyright ß 2006 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (þ44) (for orders and customer service enquiries): Visit our Home Page on All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or ed to permreq@wiley.co.uk, or faxed to (þ44) Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The Publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the Publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Other Wiley Editorial Offices John Wiley & Sons Inc., 111 River Street, Hoboken, NJ 07030, USA Jossey-Bass, 989 Market Street, San Francisco, CA , USA Wiley-VCH Verlag GmbH, Boschstr. 12, D Weinheim, Germany John Wiley & Sons Australia Ltd, 42 McDougall Street, Milton, Queensland 4064, Australia John Wiley & Sons (Asia) Pte Ltd, 2 Clementi Loop #02-01, Jin Xing Distripark, Singapore John Wiley & Sons Canada Ltd, 22 Worcester Road, Etobicoke, Ontario, Canada M9W 1L1 Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic books. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN (HB) ISBN (HB) Typeset in 10/12pt Times by Thomson Press (India) Limited, New Delhi, India. Printed and bound in Great Britain by Antony Rowe Ltd., Chippenham, Wiltshire. This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production.

7 To My Parents Carl and Blossom Voldman To My Grandparents Hannah Berger Branstetter Hershke Branstetter Esther Florescue Goodman Nathan (Naftali) Goodman Beatrice Goldman Voldman Samuel (Yesheyahu) Voldman

9 Contents About the Author Preface Acknowledgments xvii xix xxv Chapter 1 Electrostatic Discharge Electricity and Electrostatics Discharge Electricity and Electrostatics Electrostatic Discharge Key ESD Patents, Inventions, and Innovations Table of ESD Defect Mechanisms Fundamental Concepts of ESD Design Concepts of ESD Design Device Response to External Events Alternate Current Loops Switches Decoupling of Current Paths Decoupling of Feedback Loops Decoupling of Power Rails Local and Global Distribution Usage of Parasitic Elements Buffering Ballasting Unused Sections of a Semiconductor Device, Circuit or Chip Function Impedance Matching Between Floating and Non-Floating Networks Unconnected Structures Utilization of Dummy Structures and Dummy Circuits Non-Scalable Source Events Area Efficiency Time Constants Characteristic Times Electrostatic and Magnetostatic Time Constants Charge Relaxation Time 19

10 viii CONTENTS Magnetic Diffusion Time Electromagnetic Wave Transit Time Thermal Time Constants Heat Capacity Thermal Diffusion Heat Transport Equation Thermal Physics Time Constants Adiabatic, Thermal Diffusion Time Scale and Steady State Semiconductor Device Time Constants Depletion Region Transit Time Silicon Diode Storage Delay Time Bipolar Base Transit Time Bipolar Turn-on Transient Time Bipolar Turn-off Transient Time Bipolar Emitter Transition Capacitance Charging Time Bipolar Collector Capacitance Charging Time Silicon Controlled Rectifier (SCR) Time Response MOSFET Transit Time MOSFET Drain Charging Time MOSFET Gate Charging Time MOSFET Parasitic Bipolar Response Time Circuit Time Constants Pad Capacitance Half-pass Transmission Gates (TG) n-channel Half-pass Transistor Charging Time Constant Half-pass Transistor Transmission Gate Discharge Time Constant p-channel Half-pass Transistor Charging Time Constant Inverter Propagation Delay Time Constants High-to-low and Low-to-high Transition Time Inverter Propagation Delay Time Series n-channel MOSFETs Discharge Delay Time Series p-channel MOSFETs Charge Delay Time Chip Level Time Constants Peripheral I/O Power Bus Time Constant Core Chip Time Constant Substrate Time Constants Package Time Constants ESD Time Constants ESD Time Constants ESD Events Human Body Model Characteristic Time Machine Model Characteristic Time Charged Device Model Characteristic Time 36

11 CONTENTS Charged Cable Model Characteristic Time Cable Discharge Event (CDE) Model Charged Cassette Model Characteristic Time Transmission Line Pulse (TLP) Model Characteristic Time Very Fast Transmission Line Lulse (VF-TLP) Model Characteristic Time Capacitance, Resistance and Inductance and ESD The Role of Capacitance The Role of Resistance The Role of Inductance Rules of Thumb and ESD ESD Design an ESD Ohm s Law : A Simple ESD Rule-of-Thumb Design Approach Lumped versus Distributed Analysis and ESD Current and Voltage Distributions Lumped versus Distributed Systems Distributed Systems: Ladder Network Analysis Resistor Inductor Capacitor (RLC) Distributed Systems Resistor Capacitor (RC) Distributed Systems Resistor Conductance (RG) Distributed Systems ESD Metrics and Figures of Merit Chip level ESD Metrics Chip Mean Pin Power-To-Failure Chip Pin Standard Deviation Power-To-Failure Chip Mean Pin Power-To-Failure to ESD Specification Margin Worst Case Pin Power-To-Failure to Specification ESD Margin Total ESD Area to Total Chip Area Ratio ESD Area to I/O Area Ratio Circuit Level ESD Metrics Circuit ESD Protection Level to ESD Loading Effect Circuit Performance to ESD Loading Effect ESD Area to Total Circuit Area Ratio Circuit ESD Level to Specification Margin Device ESD Metric ESD Area Percentage Utilization Factor ESD Robustness to ESD Loading Effect Ratio Power-to-Failure to Maximum Power Condition ESD Quality and Reliability Business Metrics Twelve Steps to Building an ESD Strategy Summary and Closing Comments 64 Problems 65 References 66 ix

12 x CONTENTS Chapter 2 Design Synthesis Synthesis and Architecture of a Semiconductor Chip for ESD Protection Electrical and Spatial Connectivity Electrical Connectivity Thermal Connectivity Spatial Connectivity ESD, Latchup, and Noise Noise Latchup Interface Circuits and ESD Elements ESD Power Clamps Networks Placement of ESD Power Clamps ESD Rail-to-Rail Devices Placement of ESD Rail-to-Rail Networks Peripheral and Array I/O Guard Rings Pads, Floating Pads, and No Connect Pads Structures Under Bond Pads Summary and Closing Comments 90 Problems 90 References 91 Chapter 3 Electrostatic Discharge (ESD) Design: MOSFET Design Basic ESD Design Concepts Channel Length and Linewidth Control ACLV Control MOSFET ESD Design Practices ESD MOSFET Design: Channel Width n-channel MOSFET Design: Channel Width ESD MOSFET Design: Contact Gate-To-Contact Spacing Contact-To-Contact Space End Contacts Contacts to Isolation Edge ESD MOSFET Design: Metal Distribution MOSFET Metal Bus Design and Current Distribution MOSFET Ladder Network Model MOSFET Wiring: Anti-Parallel Current Distribution MOSFET Wiring: Parallel Current Distribution ESD MOSFET Design: Silicide Masking Silicide Mask Design Silicide Mask Design Over Source and Drain Silicide Mask Design Over Gate Silicide and Segmentation ESD MOSFET Design: Series Cascode Configurations Series Cascode MOSFET Integrated Cascode MOSFETs 134

13 CONTENTS 3.7 ESD MOSFET Design: Multi-Finger Design Integration of Coupling and Ballasting Techniques Grounded-Gate Resistor-Ballasted MOSFET Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET Gate-Coupled Domino Resistor-Ballasted MOSFET MOSFET Source-Initiated Gate-Bootstrapped Resistor- Ballasted multi-finger MOSFET With MOSFET MOSFET Source-Initiated Gate-Bootstrapped Resistor Ballasted Multi-Finger MOSFET With Diode ESD MOSFET Design: Enclosed Drain Design Practice ESD MOSFET Interconnect Ballasting Design ESD MOSFET Design: Source and Drain Segmentation Summary and Closing Comments 148 Problems 149 References 150 Chapter 4 Electrostatic Discharge (ESD) Design: Diode Design ESD Diode Design: ESD Basic Basic ESD Design Concepts ESD Diode Design: ESD Diode Operation ESD Diode Design: Anode p þ Diffusion Anode Width Effect p þ Anode Contacts p þ Anode Silicide to Edge Design p þ Anode to n þ Cathode Isolation Spacing p þ Anode Diode End Effects Circular and Octagonal ESD Diode Design ESD Diode Design: Interconnect Wiring Parallel Wiring Design Anti-Parallel Wiring Design Quantized Tapered Parallel and Anti-Parallel Wiring Continuous Tapered Anti-Parallel and Parallel Wiring Perpendicular (or Broadside) Wiring with Center-Fed Design Perpendicular (or Broadside) with Uniform Metal Width Perpendicular (or Broadside) Wiring with T-Shaped Extensions Metal Design for Structures Under Bond Pads ESD Diode Design: Polysilicon-Bound Diode Designs ESD Design Issues with Polysilicon-Bound Diode Structures ESD Diode Design: n-well Diode Design n-well Diode Wiring Design n-well Contact Density n-well ESD Design, Guard Rings, and Adjacent Structures ESD Diode Design: n þ /p Substrate Diode Design ESD Diode Design: Diode String ESD Design: Diode String Current Voltage Relationship ESD Design: Diode String Design Architecture and the Design Diode String Elements in Multiple I/O Environments 183 xi

14 xii CONTENTS Integration of Signal Pads ESD Design: Diode String Design Darlington Amplification ESD Design: Diode String Design Area Scaling ESD Diode Design: Triple-Well Diodes ESD Design: BiCMOS ESD Design p þ /n-well Diode ESD Structure with High Resistance Implanted Sub-Collector STI-Bound p þ /n-well Diode with Deep Trench (DT) Isolation Structure STI-Bound p þ /n-well Diode with Trench Isolation (TI) Structure Summary and Closing Comments 203 Problems 203 References 204 Chapter 5 Silicon on Insulator (SOI) ESD Design SOI ESD Basic Concepts SOI ESD Design: MOSFET with Body Contact (T-Shaped Layout) SOI ESD Design: SOI Lateral Diode Structure SOI Lateral Diode Design SOI Lateral Diode Perimeter Design SOI Lateral Diode Channel Length Design SOI Lateral p þ /n /n þ Diode Structure SOI Lateral p þ /p /n þ Diode Structure SOI Lateral p þ /p /n /n þ Diode Structure Ungated SOI Lateral p þ /p /n /n þ Diode Structure SOI Lateral Diode Structures and SOI MOSFET Halos SOI ESD Design: Buried Resistors (BR) Elements SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS) SOI ESD Design: Dual-Gate (DG) MOSFETs SOI ESD Design: FinFET Structure SOI ESD Design: Structures in the Bulk Substrate SOI ESD Design: SOI-To-Bulk Contact Structures Summary and Closing Comments 229 Problems 230 References 231 Chapter 6 Off-Chip Drivers (OCD) and ESD Off-Chip Drivers (OCD) Off Chip Drivers I/O Standards and ESD OCD: ESD Design Basics OCD: CMOS Asymmetric Pull-Up/Pull-Down OCD: CMOS Symmetric Pull-Up/Pull-Down OCD: Gunning Transceiver Logic (GTL) OCD: High Speed Transceiver Logic (HSTL) OCD: Stub Series Transceiver Logic (SSTL) Off-Chip Drivers: Mixed-Voltage Interface 244

15 CONTENTS 6.3 Off-Chip Drivers Self-Bias Well OCD Networks OCD: Self-Bias Well OCD Networks ESD Protection Networks for Self-Bias Well OCD Networks Off-Chip Drivers: Programmable Impedance (PIMP) OCD Networks OCD: Programmable Impedance (PIMP) OCD Networks ESD Input Protection Networks for PIMP OCDs Off-Chip Drivers: Universal OCDs Off-Chip Drivers: Gate-Array OCD Design Gate-Array OCD ESD Design Practices Gate-Array OCD Design: Usage of Unused Elements Gate-Array OCD Design: Impedance Matching of Unused Elements OCD ESD Design: Power Rails Over Multi-Finger MOSFETs Off-Chip Drivers: Gate Modulated Networks OCD Gate-Modulated MOSFET ESD Network OCD Simplified Gate-Modulated Network Off-Chip Driver ESD Design: Integration of Coupling and Ballasting Techniques Ballasting and Coupling MOSFET Source-Initiated Gate-Bootstrapped Resistor- Ballasted Multi-Finger MOSFET with Diode MOSFET Source-Initiated Gate-Bootstrapped Resistor- Ballasted Multi-Finger MOSFET with MOSFET Gate-Coupled Domino Resistor-Ballasted MOSFET Off-Chip Driver ESD Design: Substrate-Modulated Resistor- Ballasted MOSFET Summary and Closing Comments 264 Problems 265 References 267 Chapter 7 Receiver Circuits and ESD Receivers and ESD Receivers and Receiver Delay Time Receiver Performance and ESD Loading Effect Receivers and ESD Receivers and HBM Receivers and CDM Receivers and Receiver Evolution Receiver Circuits with Half-Pass Transmission Gate Receivers with Full-Pass Transmission Gate Receivers, Half-Pass Transmission Gate, and Keeper Network Receivers, Half-Pass Transmission Gate, and the Modified Keeper Network Receiver Circuits with Pseudo-Zero V T Half-Pass Transmission Gates Receiver Circuits with Zero Transmission Gate Receiver Circuits with Bleed Transistors 291 xiii

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