Design for Test of Digital Systems TDDC33

Transcription

1 ourse Outline Design for Test of Digital Systems TDD33 rik Larsson Department of omputer Science! Introduction; Manufacturing, afer sort, Final test, oard and System Test, Defects, and Faults! Test generation; combinational and sequential test generation! Design-for-Test techniques; test point insertion, scan, enhanced scan! Test data compression, uilt-in Self-Test; Logic IST and memory IST! System hip Test; test architectures, test planning, test scheduling, and power constraints! System Test and oundary Scan 2 System-on-hip Die System-on-hip! Processor ores! AM, MIPS, PowerP! Memories! SAM, OM, Flash, DAM UDL SAM! Viper 2.0 ev! Analog/Digital TV Processor! 10mm x 10 mm (100 mm 2 )!! ~10 M gates! ~50 M transistors! ~100 clock domains! DSP ores! Peripherals! DMA ontrollers, MMU! Interface! PI, US, UAT! Multimedia! JPG compression, MPG decoder! Networking DSP PI DSP DAM OM! thernet controller

2 5 Productivity Gap Modular Test Design Logic Transistors per hip (K) M 10M 1M 100K 10K 1K %/Yr. compound omplexity growth rate x x 1987 x 1989 x x x 1991 Transistor/Staff Month 21%/Yr. compound Productivity growth rate 1993 x M 10M 1M 100K 10K 1K Productivity Trans./Staff - Month! Test Quality! Different parts (logic, memory, analog, F) need different test methods! lack-boxed mbedded ore! Implementation is not known, forced to use tests developed by provider! Divide-and-onquer! Very large SOs are intractable for ATPG/FSim tools! Modular test approach allows concurrent development/engineering! Test euse! Module will be reused in other designs 5 6 hallenges Scan Test Application! Distributed Design and Test Development! Standardized set of deliverables! Test Access to mbedded Modules! Standardized on-chip test access hardware! Tools for test translation! hip-level Test Optimization! Tools to evaluate trade-offs; minimal impact on design (extra silicon, delay) at minimizing test application time and AT memory requirement Scan chain 1 (20 FFs) Scan chain 0 (20 FFs) ore1 Scan chain 1 (10 FFs) Scan chain 0 (10 FFs) Test vectors: 10 Test vectors: 20 Scan in + capture + scan out/scan in + capture + scan out capture + scan out -> (sc+1)*p+sc ore2 Non-modular alternative: Test time= ( )*20+(10+20)=650 Modular alternative: ore1: sc=20, p=10 -> (20+1)*10+20=230 ore2: sc=10, p=20 -> (10+1)*20+10=230 Total = Time(ore1)+Time(ore2)=460 (30% cut) 7 8

3 9 Non-modular Alternative Modular Alternative ore 1 ore 2 Scan chain 1 (20 FFs) Scan chain 1 (10 FFs) Scan chain 1 (20 FFs) Scan chain 1 (10 FFs) Scan chain 0 (20 FFs) Scan chain 0 (10 FFs) Scan chain 0 (20 FFs) Scan chain 0 (10 FFs) Test vectors: 10 Test vectors: 20 Test vectors: 10 Test vectors: 20 Non-modular alternative: Test time= ( )*20+(20+10)=650 ore 1: Test time= (20+1)*10+(20)=230 apture Max(10,20) apture ore 2: Test time= (10+1)*20+(20)=230 Total test time: Generic Test Access Architecture Test Planning source TAM SAM UDL DSP DAM MUT TAM wrapper PI OM! Test pattern Source and Sink! Store/generate test stimuli and store/evaluate test responses! Test Access Mechanism (TAM)! Transports test patterns to/from module under test (MUT)! Test rapper! Provides test access to MUT sink! Objectives: Optimizing test access to cores and scheduling test hardware Test software planning Test hardware planning ore import ore integration Test wrapper & TAM design ore test import Top-level ATPG Glue logic, soft cores Test wrappers Test scheduling! Isolates MUT at test 11 Test assembly 12

4 13 I 1500 ore Test Standard I 1500 rapper! Goals! Define test interface between core and SO! ore isolation! Plug-and-play protocols! Scope! Standardize core isolation protocols and test modes Test stimuli Functional data ore Test responses Functional data! TAM design! Type of test to be applied! Test scheduling Test control+ test stimuli wrapper Y I Test control+ test responses IP 14 Test rapper rapper oundary ell shift wci! Test wrapper! Interface between module and the rest of the chip! makes it possible access core and isolate core from rest of the system. Input cell From chip From SI/PI FF To core To SO/PO! Test modes! Normal: Functional mode, InTest: test of module itself, xtest: test of interconnection to other core! I 1500 Standard for mbedded ore Test From core Output cell From SI/PI lk shift wci To chip FF To SO/PO lk 15 16

5 17 Test rapper Test rapper! Test wrapper! Interface between module and the rest of the chip! makes it possible access core and isolate core from rest of the system.! Test modes PI P ore PP (optional) PO SP: rapper Serial Port SI: rapper Serial Input S: rapper Serial ontrol SO: rapper Serial Output PP: rapper Parallel Port PI: rapper Parallel Input P: rapper Parallel ontrol PO: rapper Parallel Output! Normal: Functional mode, InTest: test of module itself, xtest: test of interconnection to other core SI wrapper SO! I 1500 Standard for mbedded ore Test S SP (mandatory) 18 Test rapper Test rapper: Functional Operation FI TI TO SI FI (User-defined PP = PI+PO+P) wrapper FI FI ore FI FI Test enable Y I S: K, ST, Select, Shift, apture, Update FI SO TI: ell Test Input TO: ell Test Output FI: ell Functional Input : ell Functional Output FI: Functional Input : Functional Output FI: rapper Functional Input : rapper Functional Output : rapper oundary ell : rapper oundary egister Y: rapper ypass egister I: rapper Instruction egister SP: rapper Serial Port SI: rapper Serial Input S: rapper Serial ontrol SO: rapper Serial Output PP: rapper Parallel Port PI: rapper Parallel Input P: rapper Parallel ontrol PO: rapper Parallel Output Test wrapper is in functional mode; hence the test wrapper is transparent (invisible) SI FI wrapper FI ore FI Test enable Y I S FI SO 19 20

6 21 Test rapper: S_ypass Test rapper: S_XTST Test data (test stimuli and test responses) are bypassed. Test data (test stimuli and test responses) are bypassed. Normal mode Normal mode ore FI FI Test enable Y Normal mode Normal mode UDL UDL ore FI FI Test enable UDL UDL SI wrapper I S SO SI wrapper Y I SO S 22 Test rapper: S_INTST Multiplexed TAM rapper cells are programmed to perform internal test, testing of the core itself. P PI TAM PO ore FI FI Test enable PP orea PP ore PP ore SI wrapper Y I S SO SI System hip SP SP SP SO 23 24

7 25 Direct Access TAM Dasiy-hained TAM PI P PO PO P PI TAM PO P PI P PI TAM PO PP PP PP PP PP PP orea ore ore orea ore ore SI SP SP SP SO SI SP SP SP SO System hip System hip 26 Architecture Design Architecture Design Multiplex TAM AT channels orea ore ore Multiplex TAM + Direct Access TAM ore orea ore Test bus 1 Test bus 2 Test time Direct Access TAM orea ore ore Flexible Architecture ore ore orea Daisy-hained TAM orea+ore+ore

8 29 Problem Architecture Design! For a given So:! form wrapper chains out of the scan-chains and the wrapper cells at every core! connect the wrapper chains to TAMs, and! assign a time for testing each core,! such that the total test time is minimized. Mem 1 Mem 2 So A D TAM 1 TAM 1 TAM 2 TAM 2 TAM 3 TAM 3 31 rapper Design rapper Design Scan chain 0 Scan chain 1 Scan chain 0 (100 FFs) Scan chain 1 (100 FFs) SI[0:3] SO[0:3] Scan chain 2 (100 FFs) Scan chain 3 (100 FFs) ore1 S Test time (T) = (sc+1)*p+sc Scan chain 2 Scan chain 3 T=(200+1)*10+200=2210 Scan chain 0 Scan chain 2 Scan chain 1 Scan chain 3 p=10 T=(200+1)*10+200=2210 Scan chain 0 Scan chain 1 Scan chain 2 Scan chain 3 Longest wrapper scan chain" TAM width" 1. Minimize length of longest wrapper scan in/out chain 2. Minimize number of wrapper scan chains T=(400+1)*10+400=

9 34 Test rapper Optimization Priority 1: alanced rapper Scan hains educing TAM idth Priority 2: Minimize wrapper scan chains created ore" ore" Scan chain 32 FF 4 FF! 8 FF! 4 FF! 8 FF! I I I I 8 FF 8 FF 8 FF O O 4 rapper scan chains rapper" rapper" Unbalanced alanced Minimize length of longest wrapper scan in/out chain Scan chain 32 FF 2 rapper scan chains I I I I 8 FF 8 FF 8 FF O O 35 ore To TAM Assignment Test us Architecture Mem 1 Mem 2 A D Architecture A Schedule: Serial So D TAM 1 Mem 1 A TAM 1 F TAM 2 Mem 2 TAM 2 TAM 3 D TAM 3 " ombination of multiplexing and distribution " Supports only serial schedule " ore-external testing is cumbersome or impossible 36 37

10 38 Test Scheduling Test Scheduling AT Mem1 Logic2 Mem 1 Mem 2 So A D AT Mem1 Logic2 Mem 1 Mem 2 So A D 39 Test Scheduling Problem! For a given So: AT Mem 1 Mem 2 A D! form wrapper chains out of the scan-chains and the wrapper cells at every core! connect the wrapper chains to TAMs, and! assign a time for testing each core,! such that the total test time is minimized. So Total time and/or expected test time (abort-on-fail) 40 41

11 Test Scheduling Test Scheduling AT Mem1 Logic2 Mem 1 Mem 2 So A D AT Mem1 Logic2 Mem 1 Mem 2 So A D Test Scheduling Test Scheduling AT (produced response) AT Mem 1 Mem 2 So A D Mem1 Logic2 AT (expected response) Mem1 Logic2 Fault at module Mem1 Logic2

12 Abort-on-fail testing Abort-on-fail testing AT (produced response) AT (stimuli) Mem1 Logic2 Over a large set of Is, minimize overall test time Me m1 Me m2 So A D Logic 2 P U AT (produced response) Mem1 AT (expected response) Mem1 Logic2 Mem1 AT (expected response) Mem1 Logic2 Fault at module Mem1 Abort-on-fail testing Time to determine a possible fault in module ithout Abort-on-Fail ith Abort-on-Fail AT (produced response) Mem1 Logic2 Test time AT (produced response) Mem1 Test time Abort-on-fail testing Idea! Spend less time on faulty circuits! If the test fails, it is aborted early! Low-yielding and short tests should be performed early Problem! Find a test schedule that minimizes the expected test time. Assumptions! Abort-on-fail: when a fault occur, testing terminates.! Defect probability for each testable unit is given.! Sequential testing and concurrent testing.! rik Larsson, Julien Pouget, and Zebo Peng, Abort-on-Fail ased Test Scheduling, Journal of lectronic Testing; Theory and Applications (JTTA), Vol. 21, Nr 6, Dec. 2005, pages ! Urban Ingelsson, Sandeep Goel, rik Larsson, and rik Jan Marinissen, Test Scheduling for Modular SOs in an Abort-on-Fail nvironment, uropean Test Symposium (TS'05), 2005, pages 8-13

13 xample ore2 ore3 ore4 ore1 So ore Test time Sequential testing! ithout abort-on-fail: 15 ore Test time Pass probability " Test time: 15. ore4 ore3 ore2 ore1 ore1 ore2 ore3 ore4! 1 =2! 2 =4! 3 =3! 4 =6 Time! xpected test time: 13.6 Time ore4 ore2 ore3 ore1 ore1 ore2 ore3 ore4! 4 =6! 2 =4! 3 =3! 1 =2 Time Time! xpected test time: 9.5 Sequential testing Sequential testing p 1 =0.7 ore1 ore2 ore3 ore4! 1 =2 Time p 1 =0.7 p 2 =0.8 ore1 ore2 ore3 ore4 fault! 1 +! 2 Time abort testing At time point! 1 :! Probability to pass, p 1 =0.7.! eighted probability to pass,! 1 xp 1 : 2x0.7=1.4 At time point! 1 +! 2 : " Probability to pass -> pass test at core 1 and test at core 2. " Probability to fail -> pass test at core 1 and fail test at core 2.! Probability to fail (1-p 1 )=0.3.! eighted probability to fail,! 1 x(1-p 1 ): 2x0.3= 0.6

14 Sequential testing oncurrent testing p 1 =0.7 p 2 =0.8 p 3 = 0.9 p 4 = 0.95 TAM ore1 ore2 ore3 ore4 3 ore1 Time 2 1 ore2 ore3 ore4 Time At! 1 :! 1 x(1-p 1 )=0.6! 11 At! 1 +! 2 : (! 1 +! 2 )xp 1 (1-p 2 )=0.84 At! 1 +! 2 +! 3 : (! 1 +! 2 +! 3 )xp 1 xp 2 (1-p 3 )=0.50 At! 1 +! 2 +! 3 +! 4 : (! 1 +! 2 +! 3 +! 4 )xp 1 xp 2 xp 3 (1-p 4 )=0.38 (! 1 +! 2 +! 3 +! 4 )xp 1 xp 2 xp 3 xp 4 =7.2 Total expected time : =9.5 Probability to pass at time point! 11 (=2):! ore 1: p 1 =0.7 p 11! ore 2: p 2k, k=! 11 /! 2 = 0.82/4 p 21! ore 3: p 3k, k=! 11 /! 3 = 0.92/3 p 31 Probability to fail at time point! 11 (=2):! 11 x((1-p 11 )xp 21 xp 31 ) onstraints to consider I Test! Power consumption! An SO is designed according to functional power consumption! In testing, switch as many sites as possible in order to test as much as possible in a short time! Power consumed during testing is! Higher and different from functional -mode power AT SO! urn an I or getting wrong results! So Test Planning including Test Data ompression TST STIMULUS PODUD SPONS 56

15 ffect of Test Power onsumption Power-Aware Test Approaches! Peak power consumption! Average power consumption Onsen! Design SO to handle test power consumption! Design SO with test power reducing techniques! SO test planning to handle test power consumption! Test planning is a low-cost alternative to:! xplore ordering of tests to lower the test application time! Guide the search for bottlenecks where! design for low-power techniques are to be included or! (over) design for test power is needed Test Data ompression Test Data ompression for ore-based SOs I/ASI SO Decoder m sc 1 sc 2 sc 3. sc m ompactor! TAM wires are expanded two m scan chains (m>>)! educes test time and test data volume Decoder m O1 O3 O2 ompactor O4! Major drawback! High number of TAM wires (m) are routed to all cores 60 61

16 62 Test Data ompression for ore-based SOs SO! TAM wires () are partitioned into test buses! ores are connected to test buses! Few TAM wires () are routed to the cores! Decoder design at core-level m 1 w 1 m 2 O2 w 2 m 3 O1 O3 m 4 O4 Test-data volume (Mbits) Analysis of ompression Techniques Vector epeat Selective ncoding Selective ncoding & Vector epeat Selective ncoding & Vector epeat No. of TAM wires (w) Test time (clock cycles) 4.5 x Vector epeat Selective ncoding Selective ncoding & Vector epeat Vector epeat No. of TAM wires (w) 63 Analysis of ompression Techniques! At core-level define! number of TAM wires (w),! number of wrapper-chains (mi),! compression technique, and! decoder! such that the core s test time and test-data! At SO-level define! number of test buses,! width (wj) of test buses,! core s assignment to test buses, and! compression technique, and! decoder! such that the SO s test time and test-data volume are minimized. 64