Fully-Integrated Digital Average Current-Mode Control Voltage Regulator Module IC. Mor M. Peretz

Transcription

1 Fully ntegrated Digital AM VRM [1] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Fully-ntegrated Digital Average urrent-mode ontrol Voltage Regulator Module Mor M. Peretz The enter for Power Electronics and Mixed-Signal Department of Electrical and omputer Engineering Ben-Gurion University of the Negev, SRAEL s: Website:

2 Fully ntegrated Digital AM VRM [2] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY ontributors Mr. Eli Abramov, PEM - Mr. Timur Vekslender, PEM - division of Vishay Ltd. (Siliconix)

3 Fully ntegrated Digital AM VRM [3] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY ontrollers for VRMs and PoLs ontrol Objectives Regulate the output voltage Obtain zero or small steadystate (D) error Fast recovery from input and load changes Reasonable overshoot LDO 1 LDO 2 LDO 3 ore ontrol OS Err gen ompensation Logic Voltage Sense urrent Sense SYN Logic Protection ommunication 2 PMBUS SP Memory Power Management Soft Start Phase Dist. alibration nit. omp. OVP, UVP, OP, UP

4 Fully ntegrated Digital AM VRM [4] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Analog ontrollers +++ Still in the lead Accurate and efficient Fast response wide bandwidth High (continuous) resolution Lower costs (<3A All analog) Labor intensive Tailored compensation Pin count Limited flexibility/scalability ommunication and interface Big D + Big A

5 Fully ntegrated Digital AM VRM [5] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Digital ontrollers omparable or better dynamics Reduced size of overall solution Scalable and flexible Auto-tuning - No compensation Plug-and-play Lower pin count Efficiency optimization Different design Power hungry

6 Fully ntegrated Digital AM VRM [6] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY What do we really trade for a digital controller Mimicking analog controller operation by a digital one onventional ADs are too expansive High-res PWM is power hungry Do we settle for voltagemode How lean can we go? MOD MOD OMP Ref V ref A/D Protection, power management, etc. are still in

7 Fully ntegrated Digital AM VRM [7] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Digital Architecture Bottom up reate an attractive alternative to analog control Hardware redesign Focus on the benefits of digital electronics Specifically targeted to power management Avoid sensitive analog units Standard-cell digital design (no custom design) Standardize the design flow Reduce labor efforts Easier testing Faster development One step ahead: Entire controller created through code

8 Fully ntegrated Digital AM VRM [8] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Digital Process Synchronous Asynchronous Reliable Well-defined behavior Sequential or parallel Low power Ultrafast Area saving Power hungry (HS clk) Synchronization hardware (e.g., clock tree) Different design method

9 Fully ntegrated Digital AM VRM [9] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Objective Develop a compact All-digital controller architecture for VRM or PoL Entire hardware described through HDL All standard digital design flow No analog part ntegrated switches (12V nominal input) Minimize analog labor (drive)

10 Fully ntegrated Digital AM VRM [10] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY ompensation type Voltage-mode urrent-mode D[ n] D[ n 1] av [ n] bv [ n 1] cv [ n 2] err err err Ts d[ n] d[ n 1] k ierr[ n] (1 ) ierr[ n 1] t D[ n] D[ n 1] a * v [ n] b * v [ n 1] c * v [ n 2] err err err 3 multiplications + accumulator Single multiplication

11 Demux Mux P EM Fully ntegrated Digital AM VRM [11] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Buck onceptual diagram ore controller Single-multiplier P comp. Shared hardware 6-bit window AD 12-bit HR-DPWM Periphery SP Programmable deadtime Mixed Signal Peripherals onfiguration Serial ommunication nterface 12-bit HR-DPWM d[n] 12-bit urrent P ompensator c(t) Digital ontroller Prog. Dead Time V DD BST Diode High Side Drive Low Side Drive Power - Stage /V loop-selector i err [n] K (i L -i ref )[n] to-6 bit 12-bit Voltage i c [n] casting P ompensator v err [n] Q HS Q LS V in 6-bit Window AD V ref / ref V sw BST L K One- Shot i L (t) L R L v out (t) K V One- Shot

12 Fully ntegrated Digital AM VRM [12] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY ontrol flow V ref [n] - + v err [n] Voltage i c [n] i err [n] urrent d[n] c(t) Power-Stage i L (t) v Power-Stage out (t) DPWM ompensator ompensator urrent Loop Voltage Loop - + K AD K v v out [n] K AD K i L [n] AD K i L (t) K i L (t) AD K V v out (t) K V v out (t) v [ n] v [ n 1] av [ n] bv [ n 1] c c err err a k, b k 1 T / T p p S i

13 Fully ntegrated Digital AM VRM [13] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY urrent (inner) loop Ts d[ n] d[ n 1] k ierr[ n] (1 ) ierr[ n 1] t

14 Fully ntegrated Digital AM VRM [14] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Voltage (outer) loop Ts ve[ n] ve[ n 1] k verr[ n] (1 ) verr[ n 1] t

15 Fully ntegrated Digital AM VRM [15] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Timing sequence key waveforms Ring-osc. generates mid-range frequency (10-20 MHz) i L_avg i L Time-interleaved AD Time scheduling P operation Ring OS Reference PWM Signal c(t) Each unit is designed as an asynchronous block AD Sampling v err [n] i err [n] P alculation i c [n] d[n] PWM Update t blank t conv_v t calc t dead-zone t conv_i t calc t pwm T S

16 Fully ntegrated Digital AM VRM [16] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY V sense (analog input) Delay-Line AD Delay cells V start N-1 V stop D Q 0 lk D Q 1 lk D Q 2 lk D Q 3 lk D Q 4 lk D Q N-1 lk Q 0 Q 1 Q 2 Q 3 Q 4 Q n-1 Encoder Voltage-controlled delay Key factor custom design of the delay cell Not suitable for standard-cell synthesis Difficult scalability More complex layout e (error)

17 Fully ntegrated Digital AM VRM [17] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY onstant-supply DL AD 2-phase conversion: AT + TD AT outside the buffer string Realized by OS-timer Digital gates R creates the analog link No S&H Analog n Analog-to-Time Unit Analog Signal t t t-e t+e K V v out Time -to-digital Unit Digital Out Quantisized Signal v trigger G 1 R G 1,out G 2,in G 2,out G 2

18 Fully ntegrated Digital AM VRM [18] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Window DL AD Reference Pulse V ref / ref Differential Pulse Delay-Line V Sample Sample Ready Sample Ready Sample Ready Delay-Line Status Register Stable Pulse Sample Rate t One-Shot Timer Error Decoder 64 6bit Variable Pulse AD Result Error Value Error Value Error Value t t Sampled Signal v out (t) / i L (t) AD Result t

19 Fully ntegrated Digital AM VRM [19] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY HR-DPWM HS clock High power consumption High accuracy very high clk freq

20 Fully ntegrated Digital AM VRM [20] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Area demanding HR-DPWM Delay-Line lk Duty ycle Delay elements string N N-1 MUX N-1 : 0 Delay element S R Q DPWM Out Segmented DL lk oarse delay cell Medium delay cell Fine delay cell MUX 4:1 MUX 4:1 MUX 4:1 D[5:4] D[3:2] D[1:0] Delay element S R Q DPWM Out

21 Fully ntegrated Digital AM VRM [21] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY HR-DPWM Segmented DL Ref Freq oarse Delay Module Delayed lock hain d[11-0] Duty ommand : N D 0 N D N-1:0 MUX 8:1 DLY oarse Fine Delay Module 256 ells Delay-Line MUX 256:1 DLY Fine ombination Logic Module MUX 2:1 3 d[10-8] 8 d[7-0] d[11] c(t) PWM Out D 0 DLY oarse DLY Fine c(t) { Ring Oscillator Reference D < 0.5 c(t) = D 0 & DLY Fine D 0.5 c(t) = D 0 DLY Fine T s (a) (b) t Low power consumption High accuracy

22 Fully ntegrated Digital AM VRM [22] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Gate driver Extended drain - similar to LDMOS structure Enabling the use of high drain-to-source voltages ompatible with ESD scenario V DD Buffer 1 Buffer 2 Buffer 3 Gate Signal Wg,P 5 W g, P 25 W g,p 125 W g,p 625 W g,p 625 W g,p Drive Signal W g,n 5 W g,n 25 W g,n 125 W g,n 625 W g,n 625 W g,n Asymmetric diffusions layout

23 Fully ntegrated Digital AM VRM [23] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY HS drive level shifter apacitive method apacitive coupling level shifter Short delay For higher shifting ratios (>2V DD ) ladder configuration is essential 2V DD M7 M8 HS Driver VDD M 5 M 6 VDD UP1 M3 M4 UP2 PWM M1 M2 PWM

24 Fully ntegrated Digital AM VRM [24] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Level Shifter current biased BST Voltage V N M5 M M 6 9 M10 V P HS Driver Bias circuitry Bias V DD V sw DM 3 DM 4 M7 M8 R s V ref + - M ref DM 1 DM 2 Bias irciutry PWM VDD Edge Detector Bias PWM M3 M4 M1 M2 Bias Bias V R ref ref R ref

25 Fully ntegrated Digital AM VRM [25] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Lean Level shifter Biasing circuitry (Analog) removed BST Voltage V N M5 M M 6 9 M10 V P HS Driver V sw DM 3 DM 4 M7 M8 R s V DD DM 1 DM 2 PWM VDD Edge Detector PWM M3 M4 V DD M1 M2

26 Fully ntegrated Digital AM VRM [26] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Fabricated SP Digital - ontroller Ring OS Dead Time HR DPWM P ompensators Win AD 2mm Drive ircuitry Power- Stage 2.2mm

27 Fully ntegrated Digital AM VRM [27] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Experimental results V out 1.5V L f SW = 620KHz V SW 12V Specifications Value Package 5x5 QFN - MLP V in 12V Power-stage R on ~160mΩ Nominal V out 1.5V Nominal out 1.5A Off-chip L filter Switching frequency f sw Peak efficiency 2.2µH, 50μF 1.25MHz (620KHz) 70% (76%) ***package limited Total chip Si area 4.4mm 2 V out 1.5V L V SW f SW = 1.25MHz 12V

28 Fully ntegrated Digital AM VRM [28] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Loading transient 1.5A ->2.5A Vin=12V, Vout=1.3V Loading Transient V out 40mV 15µs 2.5A L 1.5A Vsw

29 Fully ntegrated Digital AM VRM [29] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Unloading transient 2.5A ->1A Vin=12V, Vout=1.3V, Unloading Transient V out 30mV f SW =1.25MHz V out 70mV f SW =620KHz L 2.2A 20µs 1.5A L 2.5A 20µs 1A Vsw Vsw

30 Fully ntegrated Digital AM VRM [30] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Acknowledgements This research is supported by the division of Vishay Ltd. (Siliconix)

31 Fully ntegrated Digital AM VRM [31] THE ENTER FOR POWER ELETRONS AND MXED-SGNAL, BEN-GURON UNVERSTY Thank You!